Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2015 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 14 | */ |
| 15 | |
Arthur Heymans | 8a1b94c | 2019-05-25 09:47:01 +0200 | [diff] [blame] | 16 | #include <arch/symbols.h> |
Kyösti Mälkki | 8f23b5d | 2019-06-30 21:00:07 +0300 | [diff] [blame^] | 17 | #include <cbmem.h> |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 18 | #include <console/console.h> |
Elyes HAOUAS | 2195f7a | 2019-06-21 07:20:12 +0200 | [diff] [blame] | 19 | #include <commonlib/helpers.h> |
Arthur Heymans | 56e2d7d | 2019-05-23 15:07:49 +0200 | [diff] [blame] | 20 | #include <cpu/intel/romstage.h> |
Nico Huber | d67edca | 2018-11-13 19:28:07 +0100 | [diff] [blame] | 21 | #include <cpu/x86/mtrr.h> |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 22 | #include <fsp/car.h> |
Aaron Durbin | 909c512 | 2015-09-29 17:41:30 -0500 | [diff] [blame] | 23 | #include <fsp/util.h> |
Arthur Heymans | be291e8 | 2019-01-06 07:35:11 +0100 | [diff] [blame] | 24 | #include <fsp/memmap.h> |
Aaron Durbin | 6d720f3 | 2015-12-08 17:00:23 -0600 | [diff] [blame] | 25 | #include <program_loading.h> |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 26 | #include <timestamp.h> |
| 27 | |
Arthur Heymans | be291e8 | 2019-01-06 07:35:11 +0100 | [diff] [blame] | 28 | #define ROMSTAGE_RAM_STACK_SIZE 0x5000 |
Aaron Durbin | 909c512 | 2015-09-29 17:41:30 -0500 | [diff] [blame] | 29 | |
Arthur Heymans | be291e8 | 2019-01-06 07:35:11 +0100 | [diff] [blame] | 30 | /* platform_enter_postcar() determines the stack to use after |
| 31 | * cache-as-ram is torn down as well as the MTRR settings to use, |
| 32 | * and continues execution in postcar stage. */ |
Arthur Heymans | 56e2d7d | 2019-05-23 15:07:49 +0200 | [diff] [blame] | 33 | void platform_enter_postcar(void) |
Aaron Durbin | 909c512 | 2015-09-29 17:41:30 -0500 | [diff] [blame] | 34 | { |
Arthur Heymans | be291e8 | 2019-01-06 07:35:11 +0100 | [diff] [blame] | 35 | struct postcar_frame pcf; |
Kyösti Mälkki | 8f23b5d | 2019-06-30 21:00:07 +0300 | [diff] [blame^] | 36 | uintptr_t top_of_ram; |
Arthur Heymans | be291e8 | 2019-01-06 07:35:11 +0100 | [diff] [blame] | 37 | |
| 38 | if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) |
| 39 | die("Unable to initialize postcar frame.\n"); |
| 40 | /* Cache the ROM as WP just below 4GiB. */ |
| 41 | postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, |
| 42 | MTRR_TYPE_WRPROT); |
| 43 | |
| 44 | /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ |
| 45 | postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); |
| 46 | |
Kyösti Mälkki | 8f23b5d | 2019-06-30 21:00:07 +0300 | [diff] [blame^] | 47 | /* Cache at least 8 MiB below the top of ram, and at most 8 MiB |
| 48 | * above top of the ram. This satisfies MTRR alignment requirement |
| 49 | * with different TSEG size configurations. */ |
| 50 | top_of_ram = ALIGN_DOWN((uintptr_t)cbmem_top(), 8*MiB); |
| 51 | postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 16*MiB, MTRR_TYPE_WRBACK); |
Arthur Heymans | be291e8 | 2019-01-06 07:35:11 +0100 | [diff] [blame] | 52 | |
| 53 | run_postcar_phase(&pcf); |
Aaron Durbin | 909c512 | 2015-09-29 17:41:30 -0500 | [diff] [blame] | 54 | } |
| 55 | |
Arthur Heymans | 59b6542 | 2019-05-23 15:24:30 +0200 | [diff] [blame] | 56 | /* This is the romstage entry called from cpu/intel/car/romstage.c */ |
Arthur Heymans | 56e2d7d | 2019-05-23 15:07:49 +0200 | [diff] [blame] | 57 | void mainboard_romstage_entry(unsigned long bist) |
Aaron Durbin | 909c512 | 2015-09-29 17:41:30 -0500 | [diff] [blame] | 58 | { |
| 59 | /* Need to locate the current FSP_INFO_HEADER. The cache-as-ram |
| 60 | * is still enabled. We can directly access work buffer here. */ |
Aaron Durbin | 7e7a4df | 2015-12-08 14:34:35 -0600 | [diff] [blame] | 61 | struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin"); |
Aaron Durbin | 909c512 | 2015-09-29 17:41:30 -0500 | [diff] [blame] | 62 | |
Jacob Garber | f7f90f7 | 2019-05-28 15:37:37 -0600 | [diff] [blame] | 63 | if (prog_locate(&fsp)) |
| 64 | die_with_post_code(POST_INVALID_CBFS, "Unable to locate fsp.bin"); |
| 65 | |
| 66 | /* This leaks a mapping which this code assumes is benign as |
| 67 | * the flash is memory mapped CPU's address space. */ |
| 68 | FSP_INFO_HEADER *fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp))); |
Aaron Durbin | 909c512 | 2015-09-29 17:41:30 -0500 | [diff] [blame] | 69 | |
John Zhao | d3a7328 | 2019-05-31 09:58:49 -0700 | [diff] [blame] | 70 | if (!fih) |
| 71 | die("Invalid FSP header\n"); |
| 72 | |
Arthur Heymans | be291e8 | 2019-01-06 07:35:11 +0100 | [diff] [blame] | 73 | cache_as_ram_stage_main(fih); |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 74 | } |