Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright 2015 Google Inc. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 14 | */ |
| 15 | |
Arthur Heymans | 8a1b94c | 2019-05-25 09:47:01 +0200 | [diff] [blame] | 16 | #include <arch/symbols.h> |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 17 | #include <console/console.h> |
Arthur Heymans | 56e2d7d | 2019-05-23 15:07:49 +0200 | [diff] [blame] | 18 | #include <cpu/intel/romstage.h> |
Nico Huber | d67edca | 2018-11-13 19:28:07 +0100 | [diff] [blame] | 19 | #include <cpu/x86/mtrr.h> |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 20 | #include <fsp/car.h> |
Aaron Durbin | 909c512 | 2015-09-29 17:41:30 -0500 | [diff] [blame] | 21 | #include <fsp/util.h> |
Arthur Heymans | be291e8 | 2019-01-06 07:35:11 +0100 | [diff] [blame] | 22 | #include <fsp/memmap.h> |
Aaron Durbin | 6d720f3 | 2015-12-08 17:00:23 -0600 | [diff] [blame] | 23 | #include <program_loading.h> |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 24 | #include <timestamp.h> |
| 25 | |
Arthur Heymans | be291e8 | 2019-01-06 07:35:11 +0100 | [diff] [blame] | 26 | #define ROMSTAGE_RAM_STACK_SIZE 0x5000 |
Aaron Durbin | 909c512 | 2015-09-29 17:41:30 -0500 | [diff] [blame] | 27 | |
Arthur Heymans | be291e8 | 2019-01-06 07:35:11 +0100 | [diff] [blame] | 28 | /* platform_enter_postcar() determines the stack to use after |
| 29 | * cache-as-ram is torn down as well as the MTRR settings to use, |
| 30 | * and continues execution in postcar stage. */ |
Arthur Heymans | 56e2d7d | 2019-05-23 15:07:49 +0200 | [diff] [blame] | 31 | void platform_enter_postcar(void) |
Aaron Durbin | 909c512 | 2015-09-29 17:41:30 -0500 | [diff] [blame] | 32 | { |
Arthur Heymans | be291e8 | 2019-01-06 07:35:11 +0100 | [diff] [blame] | 33 | struct postcar_frame pcf; |
| 34 | size_t alignment; |
| 35 | uint32_t aligned_ram; |
| 36 | |
| 37 | if (postcar_frame_init(&pcf, ROMSTAGE_RAM_STACK_SIZE)) |
| 38 | die("Unable to initialize postcar frame.\n"); |
| 39 | /* Cache the ROM as WP just below 4GiB. */ |
| 40 | postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, |
| 41 | MTRR_TYPE_WRPROT); |
| 42 | |
| 43 | /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ |
| 44 | postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); |
| 45 | |
| 46 | /* |
| 47 | * +-------------------------+ Top of RAM (aligned) |
| 48 | * | System Management Mode | |
| 49 | * | code and data | Length: CONFIG_TSEG_SIZE |
| 50 | * | (TSEG) | |
| 51 | * +-------------------------+ SMM base (aligned) |
| 52 | * | | |
| 53 | * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE |
| 54 | * | | |
| 55 | * +-------------------------+ top_of_ram (aligned) |
| 56 | * | | |
| 57 | * | CBMEM Root | |
| 58 | * | | |
| 59 | * +-------------------------+ |
| 60 | * | | |
| 61 | * | FSP Reserved Memory | |
| 62 | * | | |
| 63 | * +-------------------------+ |
| 64 | * | | |
| 65 | * | Various CBMEM Entries | |
| 66 | * | | |
| 67 | * +-------------------------+ top_of_stack (8 byte aligned) |
| 68 | * | | |
| 69 | * | stack (CBMEM Entry) | |
| 70 | * | | |
| 71 | * +-------------------------+ |
| 72 | */ |
| 73 | |
| 74 | alignment = mmap_region_granularity(); |
| 75 | aligned_ram = ALIGN_DOWN(romstage_ram_stack_bottom(), alignment); |
| 76 | postcar_frame_add_mtrr(&pcf, aligned_ram, alignment, MTRR_TYPE_WRBACK); |
| 77 | |
| 78 | if (CONFIG(HAVE_SMI_HANDLER)) { |
| 79 | void *smm_base; |
| 80 | size_t smm_size; |
| 81 | |
| 82 | /* |
| 83 | * Cache the TSEG region at the top of ram. This region is not |
| 84 | * restricted to SMM mode until SMM has been relocated. By |
| 85 | * setting the region to cacheable it provides faster access |
| 86 | * when relocating the SMM handler as well as using the TSEG |
| 87 | * region for other purposes. |
| 88 | */ |
| 89 | smm_region(&smm_base, &smm_size); |
| 90 | postcar_frame_add_mtrr(&pcf, (uintptr_t)smm_base, alignment, |
| 91 | MTRR_TYPE_WRBACK); |
| 92 | } |
| 93 | |
| 94 | run_postcar_phase(&pcf); |
Aaron Durbin | 909c512 | 2015-09-29 17:41:30 -0500 | [diff] [blame] | 95 | } |
| 96 | |
Arthur Heymans | 59b6542 | 2019-05-23 15:24:30 +0200 | [diff] [blame^] | 97 | /* This is the romstage entry called from cpu/intel/car/romstage.c */ |
Arthur Heymans | 56e2d7d | 2019-05-23 15:07:49 +0200 | [diff] [blame] | 98 | void mainboard_romstage_entry(unsigned long bist) |
Aaron Durbin | 909c512 | 2015-09-29 17:41:30 -0500 | [diff] [blame] | 99 | { |
| 100 | /* Need to locate the current FSP_INFO_HEADER. The cache-as-ram |
| 101 | * is still enabled. We can directly access work buffer here. */ |
Aaron Durbin | 7e7a4df | 2015-12-08 14:34:35 -0600 | [diff] [blame] | 102 | struct prog fsp = PROG_INIT(PROG_REFCODE, "fsp.bin"); |
Aaron Durbin | 909c512 | 2015-09-29 17:41:30 -0500 | [diff] [blame] | 103 | |
Arthur Heymans | 59b6542 | 2019-05-23 15:24:30 +0200 | [diff] [blame^] | 104 | if (!CONFIG(C_ENVIRONMENT_BOOTBLOCK)) { |
| 105 | /* Call into pre-console init code then initialize console. */ |
| 106 | car_soc_pre_console_init(); |
| 107 | car_mainboard_pre_console_init(); |
| 108 | console_init(); |
| 109 | |
| 110 | display_mtrrs(); |
| 111 | |
| 112 | car_soc_post_console_init(); |
| 113 | car_mainboard_post_console_init(); |
| 114 | } |
| 115 | |
Jacob Garber | f7f90f7 | 2019-05-28 15:37:37 -0600 | [diff] [blame] | 116 | if (prog_locate(&fsp)) |
| 117 | die_with_post_code(POST_INVALID_CBFS, "Unable to locate fsp.bin"); |
| 118 | |
| 119 | /* This leaks a mapping which this code assumes is benign as |
| 120 | * the flash is memory mapped CPU's address space. */ |
| 121 | FSP_INFO_HEADER *fih = find_fsp((uintptr_t)rdev_mmap_full(prog_rdev(&fsp))); |
Aaron Durbin | 909c512 | 2015-09-29 17:41:30 -0500 | [diff] [blame] | 122 | |
Arthur Heymans | be291e8 | 2019-01-06 07:35:11 +0100 | [diff] [blame] | 123 | cache_as_ram_stage_main(fih); |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 124 | } |
| 125 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 126 | void __weak car_mainboard_pre_console_init(void) |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 127 | { |
| 128 | } |
| 129 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 130 | void __weak car_soc_pre_console_init(void) |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 131 | { |
| 132 | } |
| 133 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 134 | void __weak car_mainboard_post_console_init(void) |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 135 | { |
| 136 | } |
| 137 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 138 | void __weak car_soc_post_console_init(void) |
Aaron Durbin | e6af4be | 2015-09-24 12:26:31 -0500 | [diff] [blame] | 139 | { |
| 140 | } |