fsp1_1: add verstage support
In order to support verstage the cache-as-ram split
is taken advantage of such that verstage has the
cache-as-ram setup and rosmtage has the cache-as-ram
tear down path. The verstage proper just initializes
the console and attempts to run romstage which triggers
the vboot verification of the firmware. In order to
pass the current FSP to use during romstage a global
variable in cache-as-ram is populated before returning
to the assembly code which tears down cache-as-ram.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados with verstage support as well as
VBOOT_DYNAMIC_WORK_BUFFER with direct link in romstage.
Change-Id: I8de74a41387ac914b03c9da67fd80f8b91e9e7ca
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11824
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/drivers/intel/fsp1_1/car.c b/src/drivers/intel/fsp1_1/car.c
index 9f87983..aa728c7 100644
--- a/src/drivers/intel/fsp1_1/car.c
+++ b/src/drivers/intel/fsp1_1/car.c
@@ -17,12 +17,27 @@
* Foundation, Inc.
*/
+#include <arch/early_variables.h>
+#include <assets.h>
#include <console/console.h>
#include <ec/google/chromeec/ec.h>
#include <fsp/car.h>
+#include <fsp/util.h>
#include <soc/intel/common/util.h>
#include <timestamp.h>
+FSP_INFO_HEADER *fih_car CAR_GLOBAL;
+
+/* Save FSP_INFO_HEADER for TempRamExit() call in assembly. */
+static inline void set_fih_car(FSP_INFO_HEADER *fih)
+{
+ /* This variable is written in the raw form because it's only
+ * ever accessed in code that that has the cache-as-ram enabled. The
+ * assembly routine which tears down cache-as-ram utilizes this
+ * variable for determining where to find FSP. */
+ fih_car = fih;
+}
+
asmlinkage void *cache_as_ram_main(struct cache_as_ram_params *car_params)
{
/* Initialize timestamp book keeping only once. */
@@ -52,13 +67,38 @@
car_mainboard_post_console_init();
/* Ensure the EC is in the right mode for recovery */
- if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC))
+ if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) &&
+ !IS_ENABLED(CONFIG_SEPARATE_VERSTAGE))
google_chromeec_early_init();
+ set_fih_car(car_params->fih);
+
/* Return new stack value in ram back to assembly stub. */
return cache_as_ram_stage_main(car_params->fih);
}
+/* Entry point taken when romstage is called after a separate verstage. */
+asmlinkage void *romstage_after_verstage(void)
+{
+ /* Need to locate the current FSP_INFO_HEADER. The cache-as-ram
+ * is still enabled. We can directly access work buffer here. */
+ FSP_INFO_HEADER *fih;
+ struct asset fsp = ASSET_INIT(ASSET_REFCODE, "fsp.bin");
+
+ console_init();
+
+ if (asset_locate(&fsp)) {
+ fih = NULL;
+ printk(BIOS_ERR, "Unable to locate %s\n", asset_name(&fsp));
+ } else
+ fih = find_fsp((uintptr_t)asset_mmap(&fsp));
+
+ set_fih_car(fih);
+
+ /* Return new stack value in ram back to assembly stub. */
+ return cache_as_ram_stage_main(fih);
+}
+
asmlinkage void after_cache_as_ram(void *chipset_context)
{
timestamp_add_now(TS_FSP_TEMP_RAM_EXIT_END);