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Sven Schnellee2ca71e2011-02-14 20:02:47 +00001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2007-2009 coresystems GmbH
5## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
6##
7## This program is free software; you can redistribute it and/or
8## modify it under the terms of the GNU General Public License as
9## published by the Free Software Foundation; version 2 of
10## the License.
11##
12## This program is distributed in the hope that it will be useful,
13## but WITHOUT ANY WARRANTY; without even the implied warranty of
14## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15## GNU General Public License for more details.
16##
Sven Schnellee2ca71e2011-02-14 20:02:47 +000017
18chip northbridge/intel/i945
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +010019 # IGD Displays
20 register "gfx.ndid" = "3"
21 register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
Sven Schnellee2ca71e2011-02-14 20:02:47 +000022
Vladimir Serbinenko26ca08c2014-06-01 00:24:05 +020023 register "gpu_hotplug" = "0x00000220"
24 register "gpu_lvds_use_spread_spectrum_clock" = "1"
Francis Rowe3054ca12015-06-22 17:37:06 +010025 register "gpu_backlight" = "0x879F879E"
Vladimir Serbinenko26ca08c2014-06-01 00:24:05 +020026
Stefan Reinauer0aa37c42013-02-12 15:20:54 -080027 device cpu_cluster 0 on
Sven Schnelle91321022011-03-01 19:58:47 +000028 chip cpu/intel/socket_mFCPGA478
29 device lapic 0 on end
30 end
31 end
Sven Schnellee2ca71e2011-02-14 20:02:47 +000032
Arthur Heymans885c2892016-10-03 17:16:48 +020033 register "pci_mmio_size" = "768"
34
Stefan Reinauer4aff4452013-02-12 14:17:15 -080035 device domain 0 on
Sven Schnelle91321022011-03-01 19:58:47 +000036 device pci 00.0 on # Host bridge
37 subsystemid 0x17aa 0x2017
38 end
39 device pci 02.0 on # VGA controller
40 subsystemid 0x17aa 0x201a
41 end
42 device pci 02.1 on # display controller
43 subsystemid 0x17aa 0x201a
44 end
45 chip southbridge/intel/i82801gx
Sven Schnellee2ca71e2011-02-14 20:02:47 +000046 register "pirqa_routing" = "0x0b"
47 register "pirqb_routing" = "0x0b"
48 register "pirqc_routing" = "0x0b"
49 register "pirqd_routing" = "0x0b"
50 register "pirqe_routing" = "0x0b"
51 register "pirqf_routing" = "0x0b"
52 register "pirqg_routing" = "0x0b"
53 register "pirqh_routing" = "0x0b"
54
55 # GPI routing
56 # 0 No effect (default)
57 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
58 # 2 SCI (if corresponding GPIO_EN bit is also set)
Sven Schnelle91321022011-03-01 19:58:47 +000059 register "gpi13_routing" = "2"
Sven Schnelle8b39e072011-06-12 16:49:13 +020060 register "gpi12_routing" = "1"
Sven Schnelle91321022011-03-01 19:58:47 +000061 register "gpi8_routing" = "2"
Sven Schnellee2ca71e2011-02-14 20:02:47 +000062
Sven Schnellee572ef62011-10-27 13:10:14 +020063 register "sata_ahci" = "0x1"
64 register "sata_ports_implemented" = "0x01"
Sven Schnellee2ca71e2011-02-14 20:02:47 +000065
66 register "gpe0_en" = "0x11000006"
Sven Schnelle8b39e072011-06-12 16:49:13 +020067 register "alt_gp_smi_en" = "0x1000"
Sven Schnelle6eb8bef2011-10-23 16:57:50 +020068
69 register "c4onc3_enable" = "1"
Vladimir Serbinenkoab83ef02014-10-25 15:18:25 +020070
71 register "c3_latency" = "0x23"
72 register "docking_supported" = "1"
73 register "p_cnt_throttling_supported" = "1"
74
Paul Menzel68eff4f2014-03-03 09:18:18 +010075 device pci 1b.0 on # Audio Controller
Sven Schnelle91321022011-03-01 19:58:47 +000076 subsystemid 0x17aa 0x2010
77 end
Sven Schnellee2ca71e2011-02-14 20:02:47 +000078 device pci 1c.0 on end # Ethernet
79 device pci 1c.1 on end # Atheros WLAN
Sven Schnelle91321022011-03-01 19:58:47 +000080 device pci 1d.0 on # USB UHCI
81 subsystemid 0x17aa 0x200a
82 end
83 device pci 1d.1 on # USB UHCI
84 subsystemid 0x17aa 0x200a
85 end
86 device pci 1d.2 on # USB UHCI
87 subsystemid 0x17aa 0x200a
88 end
89 device pci 1d.3 on # USB UHCI
90 subsystemid 0x17aa 0x200a
91 end
92 device pci 1d.7 on # USB2 EHCI
93 subsystemid 0x17aa 0x200b
94 end
Sven Schnellee2ca71e2011-02-14 20:02:47 +000095 device pci 1f.0 on # PCI-LPC bridge
Sven Schnelle91321022011-03-01 19:58:47 +000096 subsystemid 0x17aa 0x2009
Sven Schnellee2ca71e2011-02-14 20:02:47 +000097 chip ec/lenovo/pmh7
98 device pnp ff.1 on # dummy
99 end
Sven Schnelle1fa61eb2011-04-11 19:43:50 +0000100 register "backlight_enable" = "0x01"
Sven Schnelle8d0b86c2011-07-11 18:36:16 +0200101 register "dock_event_enable" = "0x01"
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000102 end
Sven Schnelleffcd1432011-04-11 19:43:32 +0000103 chip ec/lenovo/h8
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000104 device pnp ff.2 on # dummy
105 io 0x60 = 0x62
106 io 0x62 = 0x66
107 io 0x64 = 0x1600
108 io 0x66 = 0x1604
109 end
Sven Schnelleffcd1432011-04-11 19:43:32 +0000110
111 register "config0" = "0xa6"
112 register "config1" = "0x05"
113 register "config2" = "0xa0"
Sven Schnelle8d0b86c2011-07-11 18:36:16 +0200114 register "config3" = "0x01"
Sven Schnelleffcd1432011-04-11 19:43:32 +0000115
116 register "beepmask0" = "0xfe"
117 register "beepmask1" = "0x96"
Vladimir Serbinenko9a3b9c42014-01-11 20:56:47 +0100118 register "has_power_management_beeps" = "1"
Sven Schnelleffcd1432011-04-11 19:43:32 +0000119
120 register "event2_enable" = "0xff"
121 register "event3_enable" = "0xff"
122 register "event4_enable" = "0xf4"
123 register "event5_enable" = "0x3c"
Sven Schnelle8d0b86c2011-07-11 18:36:16 +0200124 register "event6_enable" = "0x80"
125 register "event7_enable" = "0x01"
Sven Schnelle8d0b86c2011-07-11 18:36:16 +0200126 register "event8_enable" = "0x01"
127 register "event9_enable" = "0xff"
128 register "eventa_enable" = "0xff"
129 register "eventb_enable" = "0xff"
130 register "eventc_enable" = "0xff"
131 register "eventd_enable" = "0xff"
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000132 end
133 chip superio/nsc/pc87382
134 device pnp 164e.2 on # IR
135 io 0x60 = 0x2f8
136 end
137
Vladimir Serbinenkof2b3cd62014-02-15 17:00:46 +0100138 device pnp 164e.3 on # Digitizer
139 io 0x60 = 0x200
140 irq 0x29 = 0xb0
141 irq 0x70 = 0x5
142 irq 0xf0 = 0x82
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000143 end
144
145 device pnp 164e.7 on # GPIO
146 io 0x60 = 0x1680
147 end
148
149 device pnp 164e.19 on # DLPC
150 io 0x60 = 0x164c
151 end
152 end
153
154 chip superio/nsc/pc87392
155 device pnp 2e.0 off #FDC
156 end
157
158 device pnp 2e.1 on # Parallel Port
159 io 0x60 = 0x3bc
160 irq 0x70 = 7
161 end
162
163 device pnp 2e.2 off # Serial Port / IR
164 io 0x60 = 0x2f8
165 irq 0x70 = 4
166 end
167
168 device pnp 2e.3 on # Serial Port
169 io 0x60 = 0x3f8
170 irq 0x70 = 4
171 end
172
173 device pnp 2e.7 on # GPIO
174 io 0x60 = 0x1620
175 end
176
177 device pnp 2e.a off # WDT
178 end
179 end
180 end
Sven Schnelle50270b82011-04-27 19:48:05 +0000181 device pci 1f.1 on # IDE
Sven Schnelle91321022011-03-01 19:58:47 +0000182 subsystemid 0x17aa 0x200c
183 end
184 device pci 1f.2 on # SATA
185 subsystemid 0x17aa 0x200d
186 end
187 device pci 1f.3 on # SMBUS
188 subsystemid 0x17aa 0x200f
Sven Schnelle6eb8bef2011-10-23 16:57:50 +0200189 chip drivers/ics/954309
190 register "reg0" = "0x2e"
191 register "reg1" = "0xf7"
192 register "reg2" = "0x3c"
193 register "reg3" = "0x20"
194 register "reg4" = "0x01"
195 register "reg5" = "0x00"
196 register "reg6" = "0x1b"
197 register "reg7" = "0x01"
198 register "reg8" = "0x54"
199 register "reg9" = "0xff"
200 register "reg10" = "0xff"
201 register "reg11" = "0x07"
202 device i2c 69 on end
203 end
Vladimir Serbinenko62adc4c2014-01-23 09:06:08 +0100204 # eeprom, 8 virtual devices, same chip
205 chip drivers/i2c/at24rf08c
206 device i2c 54 on end
207 device i2c 55 on end
208 device i2c 56 on end
209 device i2c 57 on end
210 device i2c 5c on end
211 device i2c 5d on end
212 device i2c 5e on end
213 device i2c 5f on end
214 end
Sven Schnelle91321022011-03-01 19:58:47 +0000215 end
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000216 end
217 chip southbridge/ricoh/rl5c476
218 end
219 end
220end