blob: f47fdaeab6583668e866e9a402fc40927d21272a [file] [log] [blame]
Sven Schnellee2ca71e2011-02-14 20:02:47 +00001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2007-2009 coresystems GmbH
5## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
6##
7## This program is free software; you can redistribute it and/or
8## modify it under the terms of the GNU General Public License as
9## published by the Free Software Foundation; version 2 of
10## the License.
11##
12## This program is distributed in the hope that it will be useful,
13## but WITHOUT ANY WARRANTY; without even the implied warranty of
14## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15## GNU General Public License for more details.
16##
17## You should have received a copy of the GNU General Public License
18## along with this program; if not, write to the Free Software
19## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
20## MA 02110-1301 USA
21##
22
23chip northbridge/intel/i945
24
Sven Schnelle91321022011-03-01 19:58:47 +000025 device lapic_cluster 0 on
26 chip cpu/intel/socket_mFCPGA478
27 device lapic 0 on end
28 end
29 end
Sven Schnellee2ca71e2011-02-14 20:02:47 +000030
Sven Schnelle91321022011-03-01 19:58:47 +000031 device pci_domain 0 on
32 device pci 00.0 on # Host bridge
33 subsystemid 0x17aa 0x2017
34 end
35 device pci 02.0 on # VGA controller
36 subsystemid 0x17aa 0x201a
37 end
38 device pci 02.1 on # display controller
39 subsystemid 0x17aa 0x201a
40 end
41 chip southbridge/intel/i82801gx
Sven Schnellee2ca71e2011-02-14 20:02:47 +000042 register "pirqa_routing" = "0x0b"
43 register "pirqb_routing" = "0x0b"
44 register "pirqc_routing" = "0x0b"
45 register "pirqd_routing" = "0x0b"
46 register "pirqe_routing" = "0x0b"
47 register "pirqf_routing" = "0x0b"
48 register "pirqg_routing" = "0x0b"
49 register "pirqh_routing" = "0x0b"
50
51 # GPI routing
52 # 0 No effect (default)
53 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
54 # 2 SCI (if corresponding GPIO_EN bit is also set)
Sven Schnelle91321022011-03-01 19:58:47 +000055 register "gpi13_routing" = "2"
56 register "gpi12_routing" = "2"
57 register "gpi8_routing" = "2"
Sven Schnellee2ca71e2011-02-14 20:02:47 +000058
Sven Schnelle91321022011-03-01 19:58:47 +000059 register "sata_ahci" = "0x0"
Sven Schnellee2ca71e2011-02-14 20:02:47 +000060
61 register "gpe0_en" = "0x11000006"
62
Sven Schnelle91321022011-03-01 19:58:47 +000063 device pci 1b.0 on # Audio Cnotroller
64 subsystemid 0x17aa 0x2010
65 end
Sven Schnellee2ca71e2011-02-14 20:02:47 +000066 device pci 1c.0 on end # Ethernet
67 device pci 1c.1 on end # Atheros WLAN
Sven Schnelle91321022011-03-01 19:58:47 +000068 device pci 1d.0 on # USB UHCI
69 subsystemid 0x17aa 0x200a
70 end
71 device pci 1d.1 on # USB UHCI
72 subsystemid 0x17aa 0x200a
73 end
74 device pci 1d.2 on # USB UHCI
75 subsystemid 0x17aa 0x200a
76 end
77 device pci 1d.3 on # USB UHCI
78 subsystemid 0x17aa 0x200a
79 end
80 device pci 1d.7 on # USB2 EHCI
81 subsystemid 0x17aa 0x200b
82 end
Sven Schnellee2ca71e2011-02-14 20:02:47 +000083 device pci 1f.0 on # PCI-LPC bridge
Sven Schnelle91321022011-03-01 19:58:47 +000084 subsystemid 0x17aa 0x2009
Sven Schnellee2ca71e2011-02-14 20:02:47 +000085 chip ec/lenovo/pmh7
86 device pnp ff.1 on # dummy
87 end
88 end
Sven Schnelleffcd1432011-04-11 19:43:32 +000089 chip ec/lenovo/h8
Sven Schnellee2ca71e2011-02-14 20:02:47 +000090 device pnp ff.2 on # dummy
91 io 0x60 = 0x62
92 io 0x62 = 0x66
93 io 0x64 = 0x1600
94 io 0x66 = 0x1604
95 end
Sven Schnelleffcd1432011-04-11 19:43:32 +000096
97 register "config0" = "0xa6"
98 register "config1" = "0x05"
99 register "config2" = "0xa0"
100 register "config3" = "0x05"
101
102 register "beepmask0" = "0xfe"
103 register "beepmask1" = "0x96"
104
105 register "event2_enable" = "0xff"
106 register "event3_enable" = "0xff"
107 register "event4_enable" = "0xf4"
108 register "event5_enable" = "0x3c"
109
110 register "wlan_enable" = "0x01"
111 register "trackpoint_enable" = "0x03"
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000112 end
113 chip superio/nsc/pc87382
114 device pnp 164e.2 on # IR
115 io 0x60 = 0x2f8
116 end
117
118 device pnp 164e.3 off # Serial Port
119 io 0x60 = 0x3f8
120 end
121
122 device pnp 164e.7 on # GPIO
123 io 0x60 = 0x1680
124 end
125
126 device pnp 164e.19 on # DLPC
127 io 0x60 = 0x164c
128 end
129 end
130
131 chip superio/nsc/pc87392
132 device pnp 2e.0 off #FDC
133 end
134
135 device pnp 2e.1 on # Parallel Port
136 io 0x60 = 0x3bc
137 irq 0x70 = 7
138 end
139
140 device pnp 2e.2 off # Serial Port / IR
141 io 0x60 = 0x2f8
142 irq 0x70 = 4
143 end
144
145 device pnp 2e.3 on # Serial Port
146 io 0x60 = 0x3f8
147 irq 0x70 = 4
148 end
149
150 device pnp 2e.7 on # GPIO
151 io 0x60 = 0x1620
152 end
153
154 device pnp 2e.a off # WDT
155 end
156 end
157 end
Sven Schnelle91321022011-03-01 19:58:47 +0000158 device pci 1f.1 off # IDE
159 subsystemid 0x17aa 0x200c
160 end
161 device pci 1f.2 on # SATA
162 subsystemid 0x17aa 0x200d
163 end
164 device pci 1f.3 on # SMBUS
165 subsystemid 0x17aa 0x200f
166 end
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000167 end
168 chip southbridge/ricoh/rl5c476
169 end
170 end
171end