blob: 91daf3a65e8db8bf4e098604753a45e943408c51 [file] [log] [blame]
Sven Schnellee2ca71e2011-02-14 20:02:47 +00001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2007-2009 coresystems GmbH
5## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
6##
7## This program is free software; you can redistribute it and/or
8## modify it under the terms of the GNU General Public License as
9## published by the Free Software Foundation; version 2 of
10## the License.
11##
12## This program is distributed in the hope that it will be useful,
13## but WITHOUT ANY WARRANTY; without even the implied warranty of
14## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15## GNU General Public License for more details.
16##
17## You should have received a copy of the GNU General Public License
18## along with this program; if not, write to the Free Software
19## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
20## MA 02110-1301 USA
21##
22
23chip northbridge/intel/i945
24
Stefan Reinauer0aa37c42013-02-12 15:20:54 -080025 device cpu_cluster 0 on
Sven Schnelle91321022011-03-01 19:58:47 +000026 chip cpu/intel/socket_mFCPGA478
27 device lapic 0 on end
28 end
29 end
Sven Schnellee2ca71e2011-02-14 20:02:47 +000030
Stefan Reinauer4aff4452013-02-12 14:17:15 -080031 device domain 0 on
Sven Schnelle91321022011-03-01 19:58:47 +000032 device pci 00.0 on # Host bridge
33 subsystemid 0x17aa 0x2017
34 end
35 device pci 02.0 on # VGA controller
36 subsystemid 0x17aa 0x201a
37 end
38 device pci 02.1 on # display controller
39 subsystemid 0x17aa 0x201a
40 end
41 chip southbridge/intel/i82801gx
Sven Schnellee2ca71e2011-02-14 20:02:47 +000042 register "pirqa_routing" = "0x0b"
43 register "pirqb_routing" = "0x0b"
44 register "pirqc_routing" = "0x0b"
45 register "pirqd_routing" = "0x0b"
46 register "pirqe_routing" = "0x0b"
47 register "pirqf_routing" = "0x0b"
48 register "pirqg_routing" = "0x0b"
49 register "pirqh_routing" = "0x0b"
50
51 # GPI routing
52 # 0 No effect (default)
53 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
54 # 2 SCI (if corresponding GPIO_EN bit is also set)
Sven Schnelle91321022011-03-01 19:58:47 +000055 register "gpi13_routing" = "2"
Sven Schnelle8b39e072011-06-12 16:49:13 +020056 register "gpi12_routing" = "1"
Sven Schnelle91321022011-03-01 19:58:47 +000057 register "gpi8_routing" = "2"
Sven Schnellee2ca71e2011-02-14 20:02:47 +000058
Sven Schnellee572ef62011-10-27 13:10:14 +020059 register "sata_ahci" = "0x1"
60 register "sata_ports_implemented" = "0x01"
Sven Schnellee2ca71e2011-02-14 20:02:47 +000061
62 register "gpe0_en" = "0x11000006"
Sven Schnelle8b39e072011-06-12 16:49:13 +020063 register "alt_gp_smi_en" = "0x1000"
Sven Schnelle6eb8bef2011-10-23 16:57:50 +020064
65 register "c4onc3_enable" = "1"
Sven Schnelle91321022011-03-01 19:58:47 +000066 device pci 1b.0 on # Audio Cnotroller
67 subsystemid 0x17aa 0x2010
68 end
Sven Schnellee2ca71e2011-02-14 20:02:47 +000069 device pci 1c.0 on end # Ethernet
70 device pci 1c.1 on end # Atheros WLAN
Sven Schnelle91321022011-03-01 19:58:47 +000071 device pci 1d.0 on # USB UHCI
72 subsystemid 0x17aa 0x200a
73 end
74 device pci 1d.1 on # USB UHCI
75 subsystemid 0x17aa 0x200a
76 end
77 device pci 1d.2 on # USB UHCI
78 subsystemid 0x17aa 0x200a
79 end
80 device pci 1d.3 on # USB UHCI
81 subsystemid 0x17aa 0x200a
82 end
83 device pci 1d.7 on # USB2 EHCI
84 subsystemid 0x17aa 0x200b
85 end
Sven Schnellee2ca71e2011-02-14 20:02:47 +000086 device pci 1f.0 on # PCI-LPC bridge
Sven Schnelle91321022011-03-01 19:58:47 +000087 subsystemid 0x17aa 0x2009
Sven Schnellee2ca71e2011-02-14 20:02:47 +000088 chip ec/lenovo/pmh7
89 device pnp ff.1 on # dummy
90 end
Sven Schnelle1fa61eb2011-04-11 19:43:50 +000091 register "backlight_enable" = "0x01"
Sven Schnelle8d0b86c2011-07-11 18:36:16 +020092 register "dock_event_enable" = "0x01"
Sven Schnellee2ca71e2011-02-14 20:02:47 +000093 end
Sven Schnelleffcd1432011-04-11 19:43:32 +000094 chip ec/lenovo/h8
Sven Schnellee2ca71e2011-02-14 20:02:47 +000095 device pnp ff.2 on # dummy
96 io 0x60 = 0x62
97 io 0x62 = 0x66
98 io 0x64 = 0x1600
99 io 0x66 = 0x1604
100 end
Sven Schnelleffcd1432011-04-11 19:43:32 +0000101
102 register "config0" = "0xa6"
103 register "config1" = "0x05"
104 register "config2" = "0xa0"
Sven Schnelle8d0b86c2011-07-11 18:36:16 +0200105 register "config3" = "0x01"
Sven Schnelleffcd1432011-04-11 19:43:32 +0000106
107 register "beepmask0" = "0xfe"
108 register "beepmask1" = "0x96"
109
110 register "event2_enable" = "0xff"
111 register "event3_enable" = "0xff"
112 register "event4_enable" = "0xf4"
113 register "event5_enable" = "0x3c"
Sven Schnelle8d0b86c2011-07-11 18:36:16 +0200114 register "event6_enable" = "0x80"
115 register "event7_enable" = "0x01"
Sven Schnelle95ebe662011-04-28 09:29:06 +0000116 register "eventc_enable" = "0x3c"
Sven Schnelle8d0b86c2011-07-11 18:36:16 +0200117 register "event8_enable" = "0x01"
118 register "event9_enable" = "0xff"
119 register "eventa_enable" = "0xff"
120 register "eventb_enable" = "0xff"
121 register "eventc_enable" = "0xff"
122 register "eventd_enable" = "0xff"
Sven Schnelleffcd1432011-04-11 19:43:32 +0000123
124 register "wlan_enable" = "0x01"
125 register "trackpoint_enable" = "0x03"
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000126 end
127 chip superio/nsc/pc87382
128 device pnp 164e.2 on # IR
129 io 0x60 = 0x2f8
130 end
131
132 device pnp 164e.3 off # Serial Port
133 io 0x60 = 0x3f8
134 end
135
136 device pnp 164e.7 on # GPIO
137 io 0x60 = 0x1680
138 end
139
140 device pnp 164e.19 on # DLPC
141 io 0x60 = 0x164c
142 end
143 end
144
145 chip superio/nsc/pc87392
146 device pnp 2e.0 off #FDC
147 end
148
149 device pnp 2e.1 on # Parallel Port
150 io 0x60 = 0x3bc
151 irq 0x70 = 7
152 end
153
154 device pnp 2e.2 off # Serial Port / IR
155 io 0x60 = 0x2f8
156 irq 0x70 = 4
157 end
158
159 device pnp 2e.3 on # Serial Port
160 io 0x60 = 0x3f8
161 irq 0x70 = 4
162 end
163
164 device pnp 2e.7 on # GPIO
165 io 0x60 = 0x1620
166 end
167
168 device pnp 2e.a off # WDT
169 end
170 end
171 end
Sven Schnelle50270b82011-04-27 19:48:05 +0000172 device pci 1f.1 on # IDE
Sven Schnelle91321022011-03-01 19:58:47 +0000173 subsystemid 0x17aa 0x200c
174 end
175 device pci 1f.2 on # SATA
176 subsystemid 0x17aa 0x200d
177 end
178 device pci 1f.3 on # SMBUS
179 subsystemid 0x17aa 0x200f
Sven Schnelle6eb8bef2011-10-23 16:57:50 +0200180 chip drivers/ics/954309
181 register "reg0" = "0x2e"
182 register "reg1" = "0xf7"
183 register "reg2" = "0x3c"
184 register "reg3" = "0x20"
185 register "reg4" = "0x01"
186 register "reg5" = "0x00"
187 register "reg6" = "0x1b"
188 register "reg7" = "0x01"
189 register "reg8" = "0x54"
190 register "reg9" = "0xff"
191 register "reg10" = "0xff"
192 register "reg11" = "0x07"
193 device i2c 69 on end
194 end
195
Sven Schnelle91321022011-03-01 19:58:47 +0000196 end
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000197 end
198 chip southbridge/ricoh/rl5c476
199 end
200 end
201end