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Sven Schnellee2ca71e2011-02-14 20:02:47 +00001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2007-2009 coresystems GmbH
5## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
6##
7## This program is free software; you can redistribute it and/or
8## modify it under the terms of the GNU General Public License as
9## published by the Free Software Foundation; version 2 of
10## the License.
11##
12## This program is distributed in the hope that it will be useful,
13## but WITHOUT ANY WARRANTY; without even the implied warranty of
14## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15## GNU General Public License for more details.
16##
17## You should have received a copy of the GNU General Public License
18## along with this program; if not, write to the Free Software
19## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
20## MA 02110-1301 USA
21##
22
23chip northbridge/intel/i945
24
Vladimir Serbinenko26ca08c2014-06-01 00:24:05 +020025 register "gpu_hotplug" = "0x00000220"
26 register "gpu_lvds_use_spread_spectrum_clock" = "1"
27 register "gpu_lvds_is_dual_channel" = "0"
28 register "gpu_backlight" = "0x1280128"
29
Stefan Reinauer0aa37c42013-02-12 15:20:54 -080030 device cpu_cluster 0 on
Sven Schnelle91321022011-03-01 19:58:47 +000031 chip cpu/intel/socket_mFCPGA478
32 device lapic 0 on end
33 end
34 end
Sven Schnellee2ca71e2011-02-14 20:02:47 +000035
Stefan Reinauer4aff4452013-02-12 14:17:15 -080036 device domain 0 on
Sven Schnelle91321022011-03-01 19:58:47 +000037 device pci 00.0 on # Host bridge
38 subsystemid 0x17aa 0x2017
39 end
40 device pci 02.0 on # VGA controller
41 subsystemid 0x17aa 0x201a
42 end
43 device pci 02.1 on # display controller
44 subsystemid 0x17aa 0x201a
45 end
46 chip southbridge/intel/i82801gx
Sven Schnellee2ca71e2011-02-14 20:02:47 +000047 register "pirqa_routing" = "0x0b"
48 register "pirqb_routing" = "0x0b"
49 register "pirqc_routing" = "0x0b"
50 register "pirqd_routing" = "0x0b"
51 register "pirqe_routing" = "0x0b"
52 register "pirqf_routing" = "0x0b"
53 register "pirqg_routing" = "0x0b"
54 register "pirqh_routing" = "0x0b"
55
56 # GPI routing
57 # 0 No effect (default)
58 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
59 # 2 SCI (if corresponding GPIO_EN bit is also set)
Sven Schnelle91321022011-03-01 19:58:47 +000060 register "gpi13_routing" = "2"
Sven Schnelle8b39e072011-06-12 16:49:13 +020061 register "gpi12_routing" = "1"
Sven Schnelle91321022011-03-01 19:58:47 +000062 register "gpi8_routing" = "2"
Sven Schnellee2ca71e2011-02-14 20:02:47 +000063
Sven Schnellee572ef62011-10-27 13:10:14 +020064 register "sata_ahci" = "0x1"
65 register "sata_ports_implemented" = "0x01"
Sven Schnellee2ca71e2011-02-14 20:02:47 +000066
67 register "gpe0_en" = "0x11000006"
Sven Schnelle8b39e072011-06-12 16:49:13 +020068 register "alt_gp_smi_en" = "0x1000"
Sven Schnelle6eb8bef2011-10-23 16:57:50 +020069
70 register "c4onc3_enable" = "1"
Paul Menzel68eff4f2014-03-03 09:18:18 +010071 device pci 1b.0 on # Audio Controller
Sven Schnelle91321022011-03-01 19:58:47 +000072 subsystemid 0x17aa 0x2010
73 end
Sven Schnellee2ca71e2011-02-14 20:02:47 +000074 device pci 1c.0 on end # Ethernet
75 device pci 1c.1 on end # Atheros WLAN
Sven Schnelle91321022011-03-01 19:58:47 +000076 device pci 1d.0 on # USB UHCI
77 subsystemid 0x17aa 0x200a
78 end
79 device pci 1d.1 on # USB UHCI
80 subsystemid 0x17aa 0x200a
81 end
82 device pci 1d.2 on # USB UHCI
83 subsystemid 0x17aa 0x200a
84 end
85 device pci 1d.3 on # USB UHCI
86 subsystemid 0x17aa 0x200a
87 end
88 device pci 1d.7 on # USB2 EHCI
89 subsystemid 0x17aa 0x200b
90 end
Sven Schnellee2ca71e2011-02-14 20:02:47 +000091 device pci 1f.0 on # PCI-LPC bridge
Sven Schnelle91321022011-03-01 19:58:47 +000092 subsystemid 0x17aa 0x2009
Sven Schnellee2ca71e2011-02-14 20:02:47 +000093 chip ec/lenovo/pmh7
94 device pnp ff.1 on # dummy
95 end
Sven Schnelle1fa61eb2011-04-11 19:43:50 +000096 register "backlight_enable" = "0x01"
Sven Schnelle8d0b86c2011-07-11 18:36:16 +020097 register "dock_event_enable" = "0x01"
Sven Schnellee2ca71e2011-02-14 20:02:47 +000098 end
Sven Schnelleffcd1432011-04-11 19:43:32 +000099 chip ec/lenovo/h8
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000100 device pnp ff.2 on # dummy
101 io 0x60 = 0x62
102 io 0x62 = 0x66
103 io 0x64 = 0x1600
104 io 0x66 = 0x1604
105 end
Sven Schnelleffcd1432011-04-11 19:43:32 +0000106
107 register "config0" = "0xa6"
108 register "config1" = "0x05"
109 register "config2" = "0xa0"
Sven Schnelle8d0b86c2011-07-11 18:36:16 +0200110 register "config3" = "0x01"
Sven Schnelleffcd1432011-04-11 19:43:32 +0000111
112 register "beepmask0" = "0xfe"
113 register "beepmask1" = "0x96"
Vladimir Serbinenko9a3b9c42014-01-11 20:56:47 +0100114 register "has_power_management_beeps" = "1"
Sven Schnelleffcd1432011-04-11 19:43:32 +0000115
116 register "event2_enable" = "0xff"
117 register "event3_enable" = "0xff"
118 register "event4_enable" = "0xf4"
119 register "event5_enable" = "0x3c"
Sven Schnelle8d0b86c2011-07-11 18:36:16 +0200120 register "event6_enable" = "0x80"
121 register "event7_enable" = "0x01"
Sven Schnelle95ebe662011-04-28 09:29:06 +0000122 register "eventc_enable" = "0x3c"
Sven Schnelle8d0b86c2011-07-11 18:36:16 +0200123 register "event8_enable" = "0x01"
124 register "event9_enable" = "0xff"
125 register "eventa_enable" = "0xff"
126 register "eventb_enable" = "0xff"
127 register "eventc_enable" = "0xff"
128 register "eventd_enable" = "0xff"
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000129 end
130 chip superio/nsc/pc87382
131 device pnp 164e.2 on # IR
132 io 0x60 = 0x2f8
133 end
134
Vladimir Serbinenkof2b3cd62014-02-15 17:00:46 +0100135 device pnp 164e.3 on # Digitizer
136 io 0x60 = 0x200
137 irq 0x29 = 0xb0
138 irq 0x70 = 0x5
139 irq 0xf0 = 0x82
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000140 end
141
142 device pnp 164e.7 on # GPIO
143 io 0x60 = 0x1680
144 end
145
146 device pnp 164e.19 on # DLPC
147 io 0x60 = 0x164c
148 end
149 end
150
151 chip superio/nsc/pc87392
152 device pnp 2e.0 off #FDC
153 end
154
155 device pnp 2e.1 on # Parallel Port
156 io 0x60 = 0x3bc
157 irq 0x70 = 7
158 end
159
160 device pnp 2e.2 off # Serial Port / IR
161 io 0x60 = 0x2f8
162 irq 0x70 = 4
163 end
164
165 device pnp 2e.3 on # Serial Port
166 io 0x60 = 0x3f8
167 irq 0x70 = 4
168 end
169
170 device pnp 2e.7 on # GPIO
171 io 0x60 = 0x1620
172 end
173
174 device pnp 2e.a off # WDT
175 end
176 end
177 end
Sven Schnelle50270b82011-04-27 19:48:05 +0000178 device pci 1f.1 on # IDE
Sven Schnelle91321022011-03-01 19:58:47 +0000179 subsystemid 0x17aa 0x200c
180 end
181 device pci 1f.2 on # SATA
182 subsystemid 0x17aa 0x200d
183 end
184 device pci 1f.3 on # SMBUS
185 subsystemid 0x17aa 0x200f
Sven Schnelle6eb8bef2011-10-23 16:57:50 +0200186 chip drivers/ics/954309
187 register "reg0" = "0x2e"
188 register "reg1" = "0xf7"
189 register "reg2" = "0x3c"
190 register "reg3" = "0x20"
191 register "reg4" = "0x01"
192 register "reg5" = "0x00"
193 register "reg6" = "0x1b"
194 register "reg7" = "0x01"
195 register "reg8" = "0x54"
196 register "reg9" = "0xff"
197 register "reg10" = "0xff"
198 register "reg11" = "0x07"
199 device i2c 69 on end
200 end
Vladimir Serbinenko62adc4c2014-01-23 09:06:08 +0100201 # eeprom, 8 virtual devices, same chip
202 chip drivers/i2c/at24rf08c
203 device i2c 54 on end
204 device i2c 55 on end
205 device i2c 56 on end
206 device i2c 57 on end
207 device i2c 5c on end
208 device i2c 5d on end
209 device i2c 5e on end
210 device i2c 5f on end
211 end
Sven Schnelle91321022011-03-01 19:58:47 +0000212 end
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000213 end
214 chip southbridge/ricoh/rl5c476
215 end
216 end
217end