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Sven Schnellee2ca71e2011-02-14 20:02:47 +00001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2007-2009 coresystems GmbH
5## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org>
6##
7## This program is free software; you can redistribute it and/or
8## modify it under the terms of the GNU General Public License as
9## published by the Free Software Foundation; version 2 of
10## the License.
11##
12## This program is distributed in the hope that it will be useful,
13## but WITHOUT ANY WARRANTY; without even the implied warranty of
14## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15## GNU General Public License for more details.
16##
17## You should have received a copy of the GNU General Public License
18## along with this program; if not, write to the Free Software
Patrick Georgib890a122015-03-26 15:17:45 +010019## Foundation, Inc.
Sven Schnellee2ca71e2011-02-14 20:02:47 +000020##
21
22chip northbridge/intel/i945
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +010023 # IGD Displays
24 register "gfx.ndid" = "3"
25 register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }"
Sven Schnellee2ca71e2011-02-14 20:02:47 +000026
Vladimir Serbinenko26ca08c2014-06-01 00:24:05 +020027 register "gpu_hotplug" = "0x00000220"
28 register "gpu_lvds_use_spread_spectrum_clock" = "1"
29 register "gpu_lvds_is_dual_channel" = "0"
30 register "gpu_backlight" = "0x1280128"
31
Stefan Reinauer0aa37c42013-02-12 15:20:54 -080032 device cpu_cluster 0 on
Sven Schnelle91321022011-03-01 19:58:47 +000033 chip cpu/intel/socket_mFCPGA478
34 device lapic 0 on end
35 end
36 end
Sven Schnellee2ca71e2011-02-14 20:02:47 +000037
Stefan Reinauer4aff4452013-02-12 14:17:15 -080038 device domain 0 on
Sven Schnelle91321022011-03-01 19:58:47 +000039 device pci 00.0 on # Host bridge
40 subsystemid 0x17aa 0x2017
41 end
42 device pci 02.0 on # VGA controller
43 subsystemid 0x17aa 0x201a
44 end
45 device pci 02.1 on # display controller
46 subsystemid 0x17aa 0x201a
47 end
48 chip southbridge/intel/i82801gx
Sven Schnellee2ca71e2011-02-14 20:02:47 +000049 register "pirqa_routing" = "0x0b"
50 register "pirqb_routing" = "0x0b"
51 register "pirqc_routing" = "0x0b"
52 register "pirqd_routing" = "0x0b"
53 register "pirqe_routing" = "0x0b"
54 register "pirqf_routing" = "0x0b"
55 register "pirqg_routing" = "0x0b"
56 register "pirqh_routing" = "0x0b"
57
58 # GPI routing
59 # 0 No effect (default)
60 # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
61 # 2 SCI (if corresponding GPIO_EN bit is also set)
Sven Schnelle91321022011-03-01 19:58:47 +000062 register "gpi13_routing" = "2"
Sven Schnelle8b39e072011-06-12 16:49:13 +020063 register "gpi12_routing" = "1"
Sven Schnelle91321022011-03-01 19:58:47 +000064 register "gpi8_routing" = "2"
Sven Schnellee2ca71e2011-02-14 20:02:47 +000065
Sven Schnellee572ef62011-10-27 13:10:14 +020066 register "sata_ahci" = "0x1"
67 register "sata_ports_implemented" = "0x01"
Sven Schnellee2ca71e2011-02-14 20:02:47 +000068
69 register "gpe0_en" = "0x11000006"
Sven Schnelle8b39e072011-06-12 16:49:13 +020070 register "alt_gp_smi_en" = "0x1000"
Sven Schnelle6eb8bef2011-10-23 16:57:50 +020071
72 register "c4onc3_enable" = "1"
Vladimir Serbinenkoab83ef02014-10-25 15:18:25 +020073
74 register "c3_latency" = "0x23"
75 register "docking_supported" = "1"
76 register "p_cnt_throttling_supported" = "1"
77
Paul Menzel68eff4f2014-03-03 09:18:18 +010078 device pci 1b.0 on # Audio Controller
Sven Schnelle91321022011-03-01 19:58:47 +000079 subsystemid 0x17aa 0x2010
80 end
Sven Schnellee2ca71e2011-02-14 20:02:47 +000081 device pci 1c.0 on end # Ethernet
82 device pci 1c.1 on end # Atheros WLAN
Sven Schnelle91321022011-03-01 19:58:47 +000083 device pci 1d.0 on # USB UHCI
84 subsystemid 0x17aa 0x200a
85 end
86 device pci 1d.1 on # USB UHCI
87 subsystemid 0x17aa 0x200a
88 end
89 device pci 1d.2 on # USB UHCI
90 subsystemid 0x17aa 0x200a
91 end
92 device pci 1d.3 on # USB UHCI
93 subsystemid 0x17aa 0x200a
94 end
95 device pci 1d.7 on # USB2 EHCI
96 subsystemid 0x17aa 0x200b
97 end
Sven Schnellee2ca71e2011-02-14 20:02:47 +000098 device pci 1f.0 on # PCI-LPC bridge
Sven Schnelle91321022011-03-01 19:58:47 +000099 subsystemid 0x17aa 0x2009
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000100 chip ec/lenovo/pmh7
101 device pnp ff.1 on # dummy
102 end
Sven Schnelle1fa61eb2011-04-11 19:43:50 +0000103 register "backlight_enable" = "0x01"
Sven Schnelle8d0b86c2011-07-11 18:36:16 +0200104 register "dock_event_enable" = "0x01"
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000105 end
Sven Schnelleffcd1432011-04-11 19:43:32 +0000106 chip ec/lenovo/h8
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000107 device pnp ff.2 on # dummy
108 io 0x60 = 0x62
109 io 0x62 = 0x66
110 io 0x64 = 0x1600
111 io 0x66 = 0x1604
112 end
Sven Schnelleffcd1432011-04-11 19:43:32 +0000113
114 register "config0" = "0xa6"
115 register "config1" = "0x05"
116 register "config2" = "0xa0"
Sven Schnelle8d0b86c2011-07-11 18:36:16 +0200117 register "config3" = "0x01"
Sven Schnelleffcd1432011-04-11 19:43:32 +0000118
119 register "beepmask0" = "0xfe"
120 register "beepmask1" = "0x96"
Vladimir Serbinenko9a3b9c42014-01-11 20:56:47 +0100121 register "has_power_management_beeps" = "1"
Sven Schnelleffcd1432011-04-11 19:43:32 +0000122
123 register "event2_enable" = "0xff"
124 register "event3_enable" = "0xff"
125 register "event4_enable" = "0xf4"
126 register "event5_enable" = "0x3c"
Sven Schnelle8d0b86c2011-07-11 18:36:16 +0200127 register "event6_enable" = "0x80"
128 register "event7_enable" = "0x01"
Sven Schnelle8d0b86c2011-07-11 18:36:16 +0200129 register "event8_enable" = "0x01"
130 register "event9_enable" = "0xff"
131 register "eventa_enable" = "0xff"
132 register "eventb_enable" = "0xff"
133 register "eventc_enable" = "0xff"
134 register "eventd_enable" = "0xff"
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000135 end
136 chip superio/nsc/pc87382
137 device pnp 164e.2 on # IR
138 io 0x60 = 0x2f8
139 end
140
Vladimir Serbinenkof2b3cd62014-02-15 17:00:46 +0100141 device pnp 164e.3 on # Digitizer
142 io 0x60 = 0x200
143 irq 0x29 = 0xb0
144 irq 0x70 = 0x5
145 irq 0xf0 = 0x82
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000146 end
147
148 device pnp 164e.7 on # GPIO
149 io 0x60 = 0x1680
150 end
151
152 device pnp 164e.19 on # DLPC
153 io 0x60 = 0x164c
154 end
155 end
156
157 chip superio/nsc/pc87392
158 device pnp 2e.0 off #FDC
159 end
160
161 device pnp 2e.1 on # Parallel Port
162 io 0x60 = 0x3bc
163 irq 0x70 = 7
164 end
165
166 device pnp 2e.2 off # Serial Port / IR
167 io 0x60 = 0x2f8
168 irq 0x70 = 4
169 end
170
171 device pnp 2e.3 on # Serial Port
172 io 0x60 = 0x3f8
173 irq 0x70 = 4
174 end
175
176 device pnp 2e.7 on # GPIO
177 io 0x60 = 0x1620
178 end
179
180 device pnp 2e.a off # WDT
181 end
182 end
183 end
Sven Schnelle50270b82011-04-27 19:48:05 +0000184 device pci 1f.1 on # IDE
Sven Schnelle91321022011-03-01 19:58:47 +0000185 subsystemid 0x17aa 0x200c
186 end
187 device pci 1f.2 on # SATA
188 subsystemid 0x17aa 0x200d
189 end
190 device pci 1f.3 on # SMBUS
191 subsystemid 0x17aa 0x200f
Sven Schnelle6eb8bef2011-10-23 16:57:50 +0200192 chip drivers/ics/954309
193 register "reg0" = "0x2e"
194 register "reg1" = "0xf7"
195 register "reg2" = "0x3c"
196 register "reg3" = "0x20"
197 register "reg4" = "0x01"
198 register "reg5" = "0x00"
199 register "reg6" = "0x1b"
200 register "reg7" = "0x01"
201 register "reg8" = "0x54"
202 register "reg9" = "0xff"
203 register "reg10" = "0xff"
204 register "reg11" = "0x07"
205 device i2c 69 on end
206 end
Vladimir Serbinenko62adc4c2014-01-23 09:06:08 +0100207 # eeprom, 8 virtual devices, same chip
208 chip drivers/i2c/at24rf08c
209 device i2c 54 on end
210 device i2c 55 on end
211 device i2c 56 on end
212 device i2c 57 on end
213 device i2c 5c on end
214 device i2c 5d on end
215 device i2c 5e on end
216 device i2c 5f on end
217 end
Sven Schnelle91321022011-03-01 19:58:47 +0000218 end
Sven Schnellee2ca71e2011-02-14 20:02:47 +0000219 end
220 chip southbridge/ricoh/rl5c476
221 end
222 end
223end