Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 1 | ## |
| 2 | ## This file is part of the coreboot project. |
| 3 | ## |
| 4 | ## Copyright (C) 2007-2009 coresystems GmbH |
| 5 | ## Copyright (C) 2011 Sven Schnelle <svens@stackframe.org> |
| 6 | ## |
| 7 | ## This program is free software; you can redistribute it and/or |
| 8 | ## modify it under the terms of the GNU General Public License as |
| 9 | ## published by the Free Software Foundation; version 2 of |
| 10 | ## the License. |
| 11 | ## |
| 12 | ## This program is distributed in the hope that it will be useful, |
| 13 | ## but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | ## GNU General Public License for more details. |
| 16 | ## |
| 17 | ## You should have received a copy of the GNU General Public License |
| 18 | ## along with this program; if not, write to the Free Software |
| 19 | ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 20 | ## MA 02110-1301 USA |
| 21 | ## |
| 22 | |
| 23 | chip northbridge/intel/i945 |
| 24 | |
Vladimir Serbinenko | 26ca08c | 2014-06-01 00:24:05 +0200 | [diff] [blame] | 25 | register "gpu_hotplug" = "0x00000220" |
| 26 | register "gpu_lvds_use_spread_spectrum_clock" = "1" |
| 27 | register "gpu_lvds_is_dual_channel" = "0" |
| 28 | register "gpu_backlight" = "0x1280128" |
| 29 | |
Stefan Reinauer | 0aa37c4 | 2013-02-12 15:20:54 -0800 | [diff] [blame] | 30 | device cpu_cluster 0 on |
Sven Schnelle | 9132102 | 2011-03-01 19:58:47 +0000 | [diff] [blame] | 31 | chip cpu/intel/socket_mFCPGA478 |
| 32 | device lapic 0 on end |
| 33 | end |
| 34 | end |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 35 | |
Stefan Reinauer | 4aff445 | 2013-02-12 14:17:15 -0800 | [diff] [blame] | 36 | device domain 0 on |
Sven Schnelle | 9132102 | 2011-03-01 19:58:47 +0000 | [diff] [blame] | 37 | device pci 00.0 on # Host bridge |
| 38 | subsystemid 0x17aa 0x2017 |
| 39 | end |
| 40 | device pci 02.0 on # VGA controller |
| 41 | subsystemid 0x17aa 0x201a |
| 42 | end |
| 43 | device pci 02.1 on # display controller |
| 44 | subsystemid 0x17aa 0x201a |
| 45 | end |
| 46 | chip southbridge/intel/i82801gx |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 47 | register "pirqa_routing" = "0x0b" |
| 48 | register "pirqb_routing" = "0x0b" |
| 49 | register "pirqc_routing" = "0x0b" |
| 50 | register "pirqd_routing" = "0x0b" |
| 51 | register "pirqe_routing" = "0x0b" |
| 52 | register "pirqf_routing" = "0x0b" |
| 53 | register "pirqg_routing" = "0x0b" |
| 54 | register "pirqh_routing" = "0x0b" |
| 55 | |
| 56 | # GPI routing |
| 57 | # 0 No effect (default) |
| 58 | # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) |
| 59 | # 2 SCI (if corresponding GPIO_EN bit is also set) |
Sven Schnelle | 9132102 | 2011-03-01 19:58:47 +0000 | [diff] [blame] | 60 | register "gpi13_routing" = "2" |
Sven Schnelle | 8b39e07 | 2011-06-12 16:49:13 +0200 | [diff] [blame] | 61 | register "gpi12_routing" = "1" |
Sven Schnelle | 9132102 | 2011-03-01 19:58:47 +0000 | [diff] [blame] | 62 | register "gpi8_routing" = "2" |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 63 | |
Sven Schnelle | e572ef6 | 2011-10-27 13:10:14 +0200 | [diff] [blame] | 64 | register "sata_ahci" = "0x1" |
| 65 | register "sata_ports_implemented" = "0x01" |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 66 | |
| 67 | register "gpe0_en" = "0x11000006" |
Sven Schnelle | 8b39e07 | 2011-06-12 16:49:13 +0200 | [diff] [blame] | 68 | register "alt_gp_smi_en" = "0x1000" |
Sven Schnelle | 6eb8bef | 2011-10-23 16:57:50 +0200 | [diff] [blame] | 69 | |
| 70 | register "c4onc3_enable" = "1" |
Vladimir Serbinenko | ab83ef0 | 2014-10-25 15:18:25 +0200 | [diff] [blame^] | 71 | |
| 72 | register "c3_latency" = "0x23" |
| 73 | register "docking_supported" = "1" |
| 74 | register "p_cnt_throttling_supported" = "1" |
| 75 | |
Paul Menzel | 68eff4f | 2014-03-03 09:18:18 +0100 | [diff] [blame] | 76 | device pci 1b.0 on # Audio Controller |
Sven Schnelle | 9132102 | 2011-03-01 19:58:47 +0000 | [diff] [blame] | 77 | subsystemid 0x17aa 0x2010 |
| 78 | end |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 79 | device pci 1c.0 on end # Ethernet |
| 80 | device pci 1c.1 on end # Atheros WLAN |
Sven Schnelle | 9132102 | 2011-03-01 19:58:47 +0000 | [diff] [blame] | 81 | device pci 1d.0 on # USB UHCI |
| 82 | subsystemid 0x17aa 0x200a |
| 83 | end |
| 84 | device pci 1d.1 on # USB UHCI |
| 85 | subsystemid 0x17aa 0x200a |
| 86 | end |
| 87 | device pci 1d.2 on # USB UHCI |
| 88 | subsystemid 0x17aa 0x200a |
| 89 | end |
| 90 | device pci 1d.3 on # USB UHCI |
| 91 | subsystemid 0x17aa 0x200a |
| 92 | end |
| 93 | device pci 1d.7 on # USB2 EHCI |
| 94 | subsystemid 0x17aa 0x200b |
| 95 | end |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 96 | device pci 1f.0 on # PCI-LPC bridge |
Sven Schnelle | 9132102 | 2011-03-01 19:58:47 +0000 | [diff] [blame] | 97 | subsystemid 0x17aa 0x2009 |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 98 | chip ec/lenovo/pmh7 |
| 99 | device pnp ff.1 on # dummy |
| 100 | end |
Sven Schnelle | 1fa61eb | 2011-04-11 19:43:50 +0000 | [diff] [blame] | 101 | register "backlight_enable" = "0x01" |
Sven Schnelle | 8d0b86c | 2011-07-11 18:36:16 +0200 | [diff] [blame] | 102 | register "dock_event_enable" = "0x01" |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 103 | end |
Sven Schnelle | ffcd143 | 2011-04-11 19:43:32 +0000 | [diff] [blame] | 104 | chip ec/lenovo/h8 |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 105 | device pnp ff.2 on # dummy |
| 106 | io 0x60 = 0x62 |
| 107 | io 0x62 = 0x66 |
| 108 | io 0x64 = 0x1600 |
| 109 | io 0x66 = 0x1604 |
| 110 | end |
Sven Schnelle | ffcd143 | 2011-04-11 19:43:32 +0000 | [diff] [blame] | 111 | |
| 112 | register "config0" = "0xa6" |
| 113 | register "config1" = "0x05" |
| 114 | register "config2" = "0xa0" |
Sven Schnelle | 8d0b86c | 2011-07-11 18:36:16 +0200 | [diff] [blame] | 115 | register "config3" = "0x01" |
Sven Schnelle | ffcd143 | 2011-04-11 19:43:32 +0000 | [diff] [blame] | 116 | |
| 117 | register "beepmask0" = "0xfe" |
| 118 | register "beepmask1" = "0x96" |
Vladimir Serbinenko | 9a3b9c4 | 2014-01-11 20:56:47 +0100 | [diff] [blame] | 119 | register "has_power_management_beeps" = "1" |
Sven Schnelle | ffcd143 | 2011-04-11 19:43:32 +0000 | [diff] [blame] | 120 | |
| 121 | register "event2_enable" = "0xff" |
| 122 | register "event3_enable" = "0xff" |
| 123 | register "event4_enable" = "0xf4" |
| 124 | register "event5_enable" = "0x3c" |
Sven Schnelle | 8d0b86c | 2011-07-11 18:36:16 +0200 | [diff] [blame] | 125 | register "event6_enable" = "0x80" |
| 126 | register "event7_enable" = "0x01" |
Sven Schnelle | 95ebe66 | 2011-04-28 09:29:06 +0000 | [diff] [blame] | 127 | register "eventc_enable" = "0x3c" |
Sven Schnelle | 8d0b86c | 2011-07-11 18:36:16 +0200 | [diff] [blame] | 128 | register "event8_enable" = "0x01" |
| 129 | register "event9_enable" = "0xff" |
| 130 | register "eventa_enable" = "0xff" |
| 131 | register "eventb_enable" = "0xff" |
| 132 | register "eventc_enable" = "0xff" |
| 133 | register "eventd_enable" = "0xff" |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 134 | end |
| 135 | chip superio/nsc/pc87382 |
| 136 | device pnp 164e.2 on # IR |
| 137 | io 0x60 = 0x2f8 |
| 138 | end |
| 139 | |
Vladimir Serbinenko | f2b3cd6 | 2014-02-15 17:00:46 +0100 | [diff] [blame] | 140 | device pnp 164e.3 on # Digitizer |
| 141 | io 0x60 = 0x200 |
| 142 | irq 0x29 = 0xb0 |
| 143 | irq 0x70 = 0x5 |
| 144 | irq 0xf0 = 0x82 |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 145 | end |
| 146 | |
| 147 | device pnp 164e.7 on # GPIO |
| 148 | io 0x60 = 0x1680 |
| 149 | end |
| 150 | |
| 151 | device pnp 164e.19 on # DLPC |
| 152 | io 0x60 = 0x164c |
| 153 | end |
| 154 | end |
| 155 | |
| 156 | chip superio/nsc/pc87392 |
| 157 | device pnp 2e.0 off #FDC |
| 158 | end |
| 159 | |
| 160 | device pnp 2e.1 on # Parallel Port |
| 161 | io 0x60 = 0x3bc |
| 162 | irq 0x70 = 7 |
| 163 | end |
| 164 | |
| 165 | device pnp 2e.2 off # Serial Port / IR |
| 166 | io 0x60 = 0x2f8 |
| 167 | irq 0x70 = 4 |
| 168 | end |
| 169 | |
| 170 | device pnp 2e.3 on # Serial Port |
| 171 | io 0x60 = 0x3f8 |
| 172 | irq 0x70 = 4 |
| 173 | end |
| 174 | |
| 175 | device pnp 2e.7 on # GPIO |
| 176 | io 0x60 = 0x1620 |
| 177 | end |
| 178 | |
| 179 | device pnp 2e.a off # WDT |
| 180 | end |
| 181 | end |
| 182 | end |
Sven Schnelle | 50270b8 | 2011-04-27 19:48:05 +0000 | [diff] [blame] | 183 | device pci 1f.1 on # IDE |
Sven Schnelle | 9132102 | 2011-03-01 19:58:47 +0000 | [diff] [blame] | 184 | subsystemid 0x17aa 0x200c |
| 185 | end |
| 186 | device pci 1f.2 on # SATA |
| 187 | subsystemid 0x17aa 0x200d |
| 188 | end |
| 189 | device pci 1f.3 on # SMBUS |
| 190 | subsystemid 0x17aa 0x200f |
Sven Schnelle | 6eb8bef | 2011-10-23 16:57:50 +0200 | [diff] [blame] | 191 | chip drivers/ics/954309 |
| 192 | register "reg0" = "0x2e" |
| 193 | register "reg1" = "0xf7" |
| 194 | register "reg2" = "0x3c" |
| 195 | register "reg3" = "0x20" |
| 196 | register "reg4" = "0x01" |
| 197 | register "reg5" = "0x00" |
| 198 | register "reg6" = "0x1b" |
| 199 | register "reg7" = "0x01" |
| 200 | register "reg8" = "0x54" |
| 201 | register "reg9" = "0xff" |
| 202 | register "reg10" = "0xff" |
| 203 | register "reg11" = "0x07" |
| 204 | device i2c 69 on end |
| 205 | end |
Vladimir Serbinenko | 62adc4c | 2014-01-23 09:06:08 +0100 | [diff] [blame] | 206 | # eeprom, 8 virtual devices, same chip |
| 207 | chip drivers/i2c/at24rf08c |
| 208 | device i2c 54 on end |
| 209 | device i2c 55 on end |
| 210 | device i2c 56 on end |
| 211 | device i2c 57 on end |
| 212 | device i2c 5c on end |
| 213 | device i2c 5d on end |
| 214 | device i2c 5e on end |
| 215 | device i2c 5f on end |
| 216 | end |
Sven Schnelle | 9132102 | 2011-03-01 19:58:47 +0000 | [diff] [blame] | 217 | end |
Sven Schnelle | e2ca71e | 2011-02-14 20:02:47 +0000 | [diff] [blame] | 218 | end |
| 219 | chip southbridge/ricoh/rl5c476 |
| 220 | end |
| 221 | end |
| 222 | end |