Angel Pons | a21dff6 | 2020-04-03 01:22:24 +0200 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 3 | |
Arthur Heymans | c583920 | 2019-11-12 23:48:42 +0100 | [diff] [blame] | 4 | #include <bootblock_common.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 5 | #include <device/pci_ops.h> |
Kyösti Mälkki | 3855c01 | 2019-03-03 08:45:19 +0200 | [diff] [blame] | 6 | #include <device/pnp_ops.h> |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 7 | #include <device/pnp_def.h> |
Kyösti Mälkki | cbf9571 | 2020-01-05 08:05:45 +0200 | [diff] [blame] | 8 | #include <option.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 9 | #include <northbridge/intel/i945/i945.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 10 | #include <southbridge/intel/i82801gx/i82801gx.h> |
Elyes HAOUAS | 5d4cf36 | 2018-08-06 09:58:28 +0200 | [diff] [blame] | 11 | #include <superio/winbond/common/winbond.h> |
| 12 | #include <superio/winbond/w83627thg/w83627thg.h> |
| 13 | |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame] | 14 | /* Override the default lpc decode ranges */ |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 15 | void mainboard_lpc_decode(void) |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 16 | { |
Patrick Georgi | a470019 | 2011-01-27 07:39:38 +0000 | [diff] [blame] | 17 | int lpt_en = 0; |
Kyösti Mälkki | bee82ab | 2019-12-26 10:57:43 +0200 | [diff] [blame] | 18 | u8 val; |
| 19 | |
| 20 | if (get_option(&val, "lpt") == CB_SUCCESS && val) |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 21 | lpt_en = LPT_LPC_EN; /* enable LPT */ |
| 22 | |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame] | 23 | pci_update_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 24 | } |
| 25 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 26 | /* This box has two superios, so enabling serial becomes slightly excessive. |
| 27 | * We disable a lot of stuff to make sure that there are no conflicts between |
| 28 | * the two. Also set up the GPIOs from the beginning. This is the "no schematic |
| 29 | * but safe anyways" method. |
| 30 | */ |
Arthur Heymans | c583920 | 2019-11-12 23:48:42 +0100 | [diff] [blame] | 31 | void bootblock_mainboard_early_init(void) |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 32 | { |
Antonello Dettori | 9ec1123 | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 33 | pnp_devfn_t dev; |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 34 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 35 | dev = PNP_DEV(0x2e, W83627THG_SP1); |
Elyes HAOUAS | 5d4cf36 | 2018-08-06 09:58:28 +0200 | [diff] [blame] | 36 | pnp_enter_conf_state(dev); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 37 | |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 38 | pnp_write_config(dev, 0x24, 0xc6); /* PNPCSV */ |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 39 | |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 40 | pnp_write_config(dev, 0x29, 0x43); /* GPIO settings */ |
| 41 | pnp_write_config(dev, 0x2a, 0x40); /* GPIO settings */ |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 42 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 43 | dev = PNP_DEV(0x2e, W83627THG_SP1); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 44 | pnp_set_logical_device(dev); |
| 45 | pnp_set_enable(dev, 0); |
| 46 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); |
| 47 | pnp_set_irq(dev, PNP_IDX_IRQ0, 4); |
| 48 | pnp_set_enable(dev, 1); |
| 49 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 50 | dev = PNP_DEV(0x2e, W83627THG_SP2); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 51 | pnp_set_logical_device(dev); |
| 52 | pnp_set_enable(dev, 0); |
| 53 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); |
| 54 | pnp_set_irq(dev, PNP_IDX_IRQ0, 3); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 55 | pnp_set_enable(dev, 1); |
| 56 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 57 | dev = PNP_DEV(0x2e, W83627THG_KBC); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 58 | pnp_set_logical_device(dev); |
| 59 | pnp_set_enable(dev, 0); |
| 60 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); |
| 61 | pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 62 | pnp_set_enable(dev, 1); |
| 63 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 64 | dev = PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 65 | pnp_set_logical_device(dev); |
| 66 | pnp_set_enable(dev, 0); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 67 | pnp_write_config(dev, 0xf5, 0xff); /* invert all GPIOs */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 68 | pnp_set_enable(dev, 1); |
| 69 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 70 | dev = PNP_DEV(0x2e, W83627THG_GPIO2); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 71 | pnp_set_logical_device(dev); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 72 | pnp_set_enable(dev, 1); /* Just enable it */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 73 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 74 | dev = PNP_DEV(0x2e, W83627THG_GPIO3); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 75 | pnp_set_logical_device(dev); |
| 76 | pnp_set_enable(dev, 0); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 77 | pnp_write_config(dev, 0xf0, 0xfb); /* GPIO bit 2 is output */ |
| 78 | pnp_write_config(dev, 0xf1, 0x00); /* GPIO bit 2 is 0 */ |
| 79 | pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO3+4. pnp_set_enable is not sufficient */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 80 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 81 | dev = PNP_DEV(0x2e, W83627THG_FDC); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 82 | pnp_set_logical_device(dev); |
| 83 | pnp_set_enable(dev, 0); |
| 84 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 85 | dev = PNP_DEV(0x2e, W83627THG_PP); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 86 | pnp_set_logical_device(dev); |
| 87 | pnp_set_enable(dev, 0); |
| 88 | |
Stefan Reinauer | 54309d6 | 2009-01-20 22:53:10 +0000 | [diff] [blame] | 89 | /* Enable HWM */ |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 90 | dev = PNP_DEV(0x2e, W83627THG_HWM); |
Stefan Reinauer | 54309d6 | 2009-01-20 22:53:10 +0000 | [diff] [blame] | 91 | pnp_set_logical_device(dev); |
| 92 | pnp_set_enable(dev, 0); |
| 93 | pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); |
| 94 | pnp_set_enable(dev, 1); |
| 95 | |
Elyes HAOUAS | 5d4cf36 | 2018-08-06 09:58:28 +0200 | [diff] [blame] | 96 | pnp_exit_conf_state(dev); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 97 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 98 | dev = PNP_DEV(0x4e, W83627THG_SP1); |
Elyes HAOUAS | 5d4cf36 | 2018-08-06 09:58:28 +0200 | [diff] [blame] | 99 | pnp_enter_conf_state(dev); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 100 | |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 101 | pnp_set_logical_device(dev); /* Set COM3 to sane non-conflicting values */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 102 | pnp_set_enable(dev, 0); |
| 103 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8); |
| 104 | pnp_set_irq(dev, PNP_IDX_IRQ0, 11); |
| 105 | pnp_set_enable(dev, 1); |
| 106 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 107 | dev = PNP_DEV(0x4e, W83627THG_SP2); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 108 | pnp_set_logical_device(dev); /* Set COM4 to sane non-conflicting values */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 109 | pnp_set_enable(dev, 0); |
| 110 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8); |
| 111 | pnp_set_irq(dev, PNP_IDX_IRQ0, 10); |
| 112 | pnp_set_enable(dev, 1); |
| 113 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 114 | dev = PNP_DEV(0x4e, W83627THG_FDC); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 115 | pnp_set_logical_device(dev); |
| 116 | pnp_set_enable(dev, 0); |
| 117 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 118 | dev = PNP_DEV(0x4e, W83627THG_PP); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 119 | pnp_set_logical_device(dev); |
| 120 | pnp_set_enable(dev, 0); |
| 121 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 122 | dev = PNP_DEV(0x4e, W83627THG_KBC); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 123 | pnp_set_logical_device(dev); |
| 124 | pnp_set_enable(dev, 0); |
| 125 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x00); |
| 126 | pnp_set_iobase(dev, PNP_IDX_IO1, 0x00); |
| 127 | |
Elyes HAOUAS | 5d4cf36 | 2018-08-06 09:58:28 +0200 | [diff] [blame] | 128 | pnp_exit_conf_state(dev); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 129 | } |
| 130 | |
Arthur Heymans | dc584c3 | 2019-11-12 20:37:21 +0100 | [diff] [blame] | 131 | void mainboard_late_rcba_config(void) |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 132 | { |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 133 | /* Device 1f interrupt pin register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 134 | RCBA32(D31IP) = 0x00042210; |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 135 | /* Device 1d interrupt pin register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 136 | RCBA32(D28IP) = 0x00214321; |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 137 | |
| 138 | /* dev irq route register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 139 | RCBA16(D31IR) = 0x0132; |
| 140 | RCBA16(D30IR) = 0x3241; |
| 141 | RCBA16(D29IR) = 0x0237; |
| 142 | RCBA16(D28IR) = 0x3210; |
| 143 | RCBA16(D27IR) = 0x3210; |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 144 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 145 | /* Enable PCIe Root Port Clock Gate */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 146 | } |