Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 3 | * |
Stefan Reinauer | de3206a | 2010-02-22 06:09:43 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007-2010 coresystems GmbH |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 5 | * |
Uwe Hermann | 2bb4acf | 2010-03-01 17:19:55 +0000 | [diff] [blame] | 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
Uwe Hermann | 2bb4acf | 2010-03-01 17:19:55 +0000 | [diff] [blame] | 17 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 18 | */ |
| 19 | |
Myles Watson | 1d6d45e | 2009-11-06 17:02:51 +0000 | [diff] [blame] | 20 | // __PRE_RAM__ means: use "unsigned" for device, not a struct. |
Stefan Reinauer | 5e32823 | 2010-03-29 19:19:16 +0000 | [diff] [blame] | 21 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 22 | #include <stdint.h> |
Patrick Georgi | 12aba82 | 2009-04-30 07:07:22 +0000 | [diff] [blame] | 23 | #include <string.h> |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 24 | #include <lib.h> |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 25 | #include <arch/io.h> |
| 26 | #include <arch/romcc_io.h> |
| 27 | #include <device/pci_def.h> |
| 28 | #include <device/pnp_def.h> |
| 29 | #include <cpu/x86/lapic.h> |
Patrick Georgi | 5692c57 | 2010-10-05 13:40:31 +0000 | [diff] [blame] | 30 | #include <usbdebug.h> |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 31 | #include "superio/winbond/w83627thg/w83627thg.h" |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 32 | #include <pc80/mc146818rtc.h> |
Stefan Reinauer | 10ec0fe | 2010-09-25 10:40:47 +0000 | [diff] [blame] | 33 | #include "option_table.h" |
Stefan Reinauer | de3206a | 2010-02-22 06:09:43 +0000 | [diff] [blame] | 34 | #include <console/console.h> |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 35 | #include <cpu/x86/bist.h> |
stepan | 8301d83 | 2010-12-08 07:07:33 +0000 | [diff] [blame] | 36 | #include "superio/winbond/w83627thg/early_serial.c" |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 37 | #include "northbridge/intel/i945/i945.h" |
| 38 | #include "northbridge/intel/i945/raminit.h" |
Stefan Reinauer | a5fdadf | 2009-07-21 21:58:20 +0000 | [diff] [blame] | 39 | #include "southbridge/intel/i82801gx/i82801gx.h" |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 40 | |
Uwe Hermann | 57b2ff8 | 2010-11-21 17:29:59 +0000 | [diff] [blame] | 41 | #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) |
| 42 | |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 43 | void setup_ich7_gpios(void) |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 44 | { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 45 | printk(BIOS_DEBUG, " GPIOS..."); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 46 | /* General Registers */ |
| 47 | outl(0x1f1ff7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ |
| 48 | outl(0xe0e8efc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ |
| 49 | outl(0xebffeeff, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ |
| 50 | /* Output Control Registers */ |
| 51 | outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ |
| 52 | /* Input Control Registers */ |
| 53 | outl(0x00002180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ |
Stefan Reinauer | e1025d0 | 2009-03-11 15:20:36 +0000 | [diff] [blame] | 54 | outl(0x000100ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 55 | outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ |
| 56 | outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ |
| 57 | } |
| 58 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 59 | static void ich7_enable_lpc(void) |
| 60 | { |
Patrick Georgi | a470019 | 2011-01-27 07:39:38 +0000 | [diff] [blame^] | 61 | int lpt_en = 0; |
| 62 | if (read_option(CMOS_VSTART_lpt, CMOS_VLEN_lpt, 0) != 0) { |
| 63 | lpt_en = 1<<2; // enable LPT |
| 64 | } |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 65 | // Enable Serial IRQ |
| 66 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); |
| 67 | // Set COM1/COM2 decode range |
| 68 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); |
| 69 | // Enable COM1/COM2/KBD/SuperIO1+2 |
Patrick Georgi | a470019 | 2011-01-27 07:39:38 +0000 | [diff] [blame^] | 70 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b | lpt_en); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 71 | // Enable HWM at 0xa00 |
Stefan Reinauer | e1025d0 | 2009-03-11 15:20:36 +0000 | [diff] [blame] | 72 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 73 | // COM3 decode |
| 74 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9); |
| 75 | // COM4 decode |
| 76 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 77 | // io 0x300 decode |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 78 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); |
| 79 | } |
| 80 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 81 | /* This box has two superios, so enabling serial becomes slightly excessive. |
| 82 | * We disable a lot of stuff to make sure that there are no conflicts between |
| 83 | * the two. Also set up the GPIOs from the beginning. This is the "no schematic |
| 84 | * but safe anyways" method. |
| 85 | */ |
| 86 | static void early_superio_config_w83627thg(void) |
| 87 | { |
| 88 | device_t dev; |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 89 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 90 | dev=PNP_DEV(0x2e, W83627THG_SP1); |
| 91 | pnp_enter_ext_func_mode(dev); |
| 92 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 93 | pnp_write_config(dev, 0x24, 0xc6); // PNPCSV |
| 94 | |
| 95 | pnp_write_config(dev, 0x29, 0x43); // GPIO settings |
| 96 | pnp_write_config(dev, 0x2a, 0x40); // GPIO settings |
| 97 | |
| 98 | dev=PNP_DEV(0x2e, W83627THG_SP1); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 99 | pnp_set_logical_device(dev); |
| 100 | pnp_set_enable(dev, 0); |
| 101 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); |
| 102 | pnp_set_irq(dev, PNP_IDX_IRQ0, 4); |
| 103 | pnp_set_enable(dev, 1); |
| 104 | |
| 105 | dev=PNP_DEV(0x2e, W83627THG_SP2); |
| 106 | pnp_set_logical_device(dev); |
| 107 | pnp_set_enable(dev, 0); |
| 108 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); |
| 109 | pnp_set_irq(dev, PNP_IDX_IRQ0, 3); |
| 110 | // pnp_write_config(dev, 0xf1, 4); // IRMODE0 |
| 111 | pnp_set_enable(dev, 1); |
| 112 | |
| 113 | dev=PNP_DEV(0x2e, W83627THG_KBC); |
| 114 | pnp_set_logical_device(dev); |
| 115 | pnp_set_enable(dev, 0); |
| 116 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); |
| 117 | pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); |
| 118 | // pnp_write_config(dev, 0xf0, 0x82); |
| 119 | pnp_set_enable(dev, 1); |
| 120 | |
| 121 | dev=PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1); |
| 122 | pnp_set_logical_device(dev); |
| 123 | pnp_set_enable(dev, 0); |
| 124 | pnp_write_config(dev, 0xf5, 0xff); // invert all GPIOs |
| 125 | pnp_set_enable(dev, 1); |
| 126 | |
| 127 | dev=PNP_DEV(0x2e, W83627THG_GPIO2); |
| 128 | pnp_set_logical_device(dev); |
| 129 | pnp_set_enable(dev, 1); // Just enable it |
| 130 | |
| 131 | dev=PNP_DEV(0x2e, W83627THG_GPIO3); |
| 132 | pnp_set_logical_device(dev); |
| 133 | pnp_set_enable(dev, 0); |
| 134 | pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output |
| 135 | pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 |
| 136 | pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient |
| 137 | |
| 138 | dev=PNP_DEV(0x2e, W83627THG_FDC); |
| 139 | pnp_set_logical_device(dev); |
| 140 | pnp_set_enable(dev, 0); |
| 141 | |
| 142 | dev=PNP_DEV(0x2e, W83627THG_PP); |
| 143 | pnp_set_logical_device(dev); |
| 144 | pnp_set_enable(dev, 0); |
| 145 | |
Stefan Reinauer | 54309d6 | 2009-01-20 22:53:10 +0000 | [diff] [blame] | 146 | /* Enable HWM */ |
| 147 | dev=PNP_DEV(0x2e, W83627THG_HWM); |
| 148 | pnp_set_logical_device(dev); |
| 149 | pnp_set_enable(dev, 0); |
| 150 | pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); |
| 151 | pnp_set_enable(dev, 1); |
| 152 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 153 | pnp_exit_ext_func_mode(dev); |
| 154 | |
| 155 | dev=PNP_DEV(0x4e, W83627THG_SP1); |
| 156 | pnp_enter_ext_func_mode(dev); |
| 157 | |
| 158 | pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values |
| 159 | pnp_set_enable(dev, 0); |
| 160 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8); |
| 161 | pnp_set_irq(dev, PNP_IDX_IRQ0, 11); |
| 162 | pnp_set_enable(dev, 1); |
| 163 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 164 | dev=PNP_DEV(0x4e, W83627THG_SP2); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 165 | pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values |
| 166 | pnp_set_enable(dev, 0); |
| 167 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8); |
| 168 | pnp_set_irq(dev, PNP_IDX_IRQ0, 10); |
| 169 | pnp_set_enable(dev, 1); |
| 170 | |
| 171 | dev=PNP_DEV(0x4e, W83627THG_FDC); |
| 172 | pnp_set_logical_device(dev); |
| 173 | pnp_set_enable(dev, 0); |
| 174 | |
| 175 | dev=PNP_DEV(0x4e, W83627THG_PP); |
| 176 | pnp_set_logical_device(dev); |
| 177 | pnp_set_enable(dev, 0); |
| 178 | |
| 179 | dev=PNP_DEV(0x4e, W83627THG_KBC); |
| 180 | pnp_set_logical_device(dev); |
| 181 | pnp_set_enable(dev, 0); |
| 182 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x00); |
| 183 | pnp_set_iobase(dev, PNP_IDX_IO1, 0x00); |
| 184 | |
| 185 | pnp_exit_ext_func_mode(dev); |
| 186 | } |
| 187 | |
| 188 | static void rcba_config(void) |
| 189 | { |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 190 | u32 reg32; |
| 191 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 192 | /* Set up virtual channel 0 */ |
| 193 | //RCBA32(0x0014) = 0x80000001; |
| 194 | //RCBA32(0x001c) = 0x03128010; |
| 195 | |
| 196 | /* Device 1f interrupt pin register */ |
| 197 | RCBA32(0x3100) = 0x00042210; |
| 198 | /* Device 1d interrupt pin register */ |
| 199 | RCBA32(0x310c) = 0x00214321; |
| 200 | |
| 201 | /* dev irq route register */ |
| 202 | RCBA16(0x3140) = 0x0132; |
| 203 | RCBA16(0x3142) = 0x3241; |
| 204 | RCBA16(0x3144) = 0x0237; |
| 205 | RCBA16(0x3146) = 0x3210; |
| 206 | RCBA16(0x3148) = 0x3210; |
| 207 | |
| 208 | /* Enable IOAPIC */ |
| 209 | RCBA8(0x31ff) = 0x03; |
| 210 | |
| 211 | /* Enable upper 128bytes of CMOS */ |
| 212 | RCBA32(0x3400) = (1 << 2); |
| 213 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 214 | /* Now, this is a bit ugly. As per PCI specification, function 0 of a |
| 215 | * device always has to be implemented. So disabling ethernet port 1 |
| 216 | * would essentially disable all three ethernet ports of the mainboard. |
| 217 | * It's possible to rename the ports to achieve compatibility to the |
| 218 | * PCI spec but this will confuse all (static!) tables containing |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 219 | * interrupt routing information. |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 220 | * To avoid this, we enable (unused) port 6 and swap it with port 1 |
| 221 | * in the case that ethernet port 1 is disabled. Since no devices |
| 222 | * are connected to that port, we don't have to worry about interrupt |
| 223 | * routing. |
| 224 | */ |
| 225 | int port_shuffle = 0; |
| 226 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 227 | /* Disable unused devices */ |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 228 | reg32 = FD_ACMOD|FD_ACAUD|FD_PATA; |
| 229 | reg32 |= FD_PCIE6|FD_PCIE5|FD_PCIE4; |
| 230 | |
| 231 | if (read_option(CMOS_VSTART_ethernet1, CMOS_VLEN_ethernet1, 0) != 0) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 232 | printk(BIOS_DEBUG, "Disabling ethernet adapter 1.\n"); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 233 | reg32 |= FD_PCIE1; |
| 234 | } |
| 235 | if (read_option(CMOS_VSTART_ethernet2, CMOS_VLEN_ethernet2, 0) != 0) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 236 | printk(BIOS_DEBUG, "Disabling ethernet adapter 2.\n"); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 237 | reg32 |= FD_PCIE2; |
| 238 | } else { |
| 239 | if (reg32 & FD_PCIE1) |
| 240 | port_shuffle = 1; |
| 241 | } |
| 242 | if (read_option(CMOS_VSTART_ethernet3, CMOS_VLEN_ethernet3, 0) != 0) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 243 | printk(BIOS_DEBUG, "Disabling ethernet adapter 3.\n"); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 244 | reg32 |= FD_PCIE3; |
| 245 | } else { |
| 246 | if (reg32 & FD_PCIE1) |
| 247 | port_shuffle = 1; |
| 248 | } |
| 249 | |
| 250 | if (port_shuffle) { |
| 251 | /* Enable PCIE6 again */ |
| 252 | reg32 &= ~FD_PCIE6; |
| 253 | /* Swap PCIE6 and PCIE1 */ |
| 254 | RCBA32(RPFN) = 0x00043215; |
| 255 | } |
| 256 | |
| 257 | reg32 |= 1; |
| 258 | |
| 259 | RCBA32(0x3418) = reg32; |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 260 | |
| 261 | /* Enable PCIe Root Port Clock Gate */ |
| 262 | // RCBA32(0x341c) = 0x00000001; |
| 263 | } |
| 264 | |
| 265 | static void early_ich7_init(void) |
| 266 | { |
| 267 | uint8_t reg8; |
| 268 | uint32_t reg32; |
| 269 | |
| 270 | // program secondary mlt XXX byte? |
| 271 | pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); |
| 272 | |
| 273 | // reset rtc power status |
| 274 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); |
| 275 | reg8 &= ~(1 << 2); |
| 276 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); |
| 277 | |
| 278 | // usb transient disconnect |
| 279 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); |
| 280 | reg8 |= (3 << 0); |
| 281 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); |
| 282 | |
| 283 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); |
| 284 | reg32 |= (1 << 29) | (1 << 17); |
| 285 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); |
| 286 | |
| 287 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); |
| 288 | reg32 |= (1 << 31) | (1 << 27); |
| 289 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); |
| 290 | |
| 291 | RCBA32(0x0088) = 0x0011d000; |
| 292 | RCBA16(0x01fc) = 0x060f; |
| 293 | RCBA32(0x01f4) = 0x86000040; |
| 294 | RCBA32(0x0214) = 0x10030549; |
| 295 | RCBA32(0x0218) = 0x00020504; |
| 296 | RCBA8(0x0220) = 0xc5; |
| 297 | reg32 = RCBA32(0x3410); |
| 298 | reg32 |= (1 << 6); |
| 299 | RCBA32(0x3410) = reg32; |
| 300 | reg32 = RCBA32(0x3430); |
| 301 | reg32 &= ~(3 << 0); |
| 302 | reg32 |= (1 << 0); |
| 303 | RCBA32(0x3430) = reg32; |
| 304 | RCBA32(0x3418) |= (1 << 0); |
| 305 | RCBA16(0x0200) = 0x2008; |
| 306 | RCBA8(0x2027) = 0x0d; |
| 307 | RCBA16(0x3e08) |= (1 << 7); |
| 308 | RCBA16(0x3e48) |= (1 << 7); |
| 309 | RCBA32(0x3e0e) |= (1 << 7); |
| 310 | RCBA32(0x3e4e) |= (1 << 7); |
| 311 | |
| 312 | // next step only on ich7m b0 and later: |
| 313 | reg32 = RCBA32(0x2034); |
| 314 | reg32 &= ~(0x0f << 16); |
| 315 | reg32 |= (5 << 16); |
| 316 | RCBA32(0x2034) = reg32; |
| 317 | } |
| 318 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 319 | #include <cbmem.h> |
| 320 | |
Stefan Reinauer | 3e1f524 | 2010-04-12 23:04:29 +0000 | [diff] [blame] | 321 | void main(unsigned long bist) |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 322 | { |
Stefan Reinauer | a5fdadf | 2009-07-21 21:58:20 +0000 | [diff] [blame] | 323 | u32 reg32; |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 324 | int boot_mode = 0; |
| 325 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 326 | if (bist == 0) |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 327 | enable_lapic(); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 328 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 329 | /* Force PCIRST# */ |
| 330 | pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); |
Stefan Reinauer | bc8613e | 2010-08-25 18:35:42 +0000 | [diff] [blame] | 331 | udelay(200 * 1000); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 332 | pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 333 | |
Stefan Reinauer | bc8613e | 2010-08-25 18:35:42 +0000 | [diff] [blame] | 334 | ich7_enable_lpc(); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 335 | early_superio_config_w83627thg(); |
| 336 | |
| 337 | /* Set up the console */ |
| 338 | uart_init(); |
Stefan Reinauer | a5fdadf | 2009-07-21 21:58:20 +0000 | [diff] [blame] | 339 | |
Stefan Reinauer | 7e00a44 | 2010-05-25 17:09:05 +0000 | [diff] [blame] | 340 | #if CONFIG_USBDEBUG |
Uwe Hermann | 370d979 | 2010-09-25 14:23:31 +0000 | [diff] [blame] | 341 | i82801gx_enable_usbdebug(1); |
Stefan Reinauer | 75a05dc | 2010-05-25 16:35:51 +0000 | [diff] [blame] | 342 | early_usbdebug_init(); |
Stefan Reinauer | a5fdadf | 2009-07-21 21:58:20 +0000 | [diff] [blame] | 343 | #endif |
| 344 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 345 | console_init(); |
| 346 | |
| 347 | /* Halt if there was a built in self test failure */ |
| 348 | report_bist_failure(bist); |
| 349 | |
| 350 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 351 | printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); |
| 352 | outb(0x6, 0xcf9); |
| 353 | while (1) asm("hlt"); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 354 | } |
| 355 | |
| 356 | /* Perform some early chipset initialization required |
| 357 | * before RAM initialization can work |
| 358 | */ |
| 359 | i945_early_initialization(); |
| 360 | |
Stefan Reinauer | a5fdadf | 2009-07-21 21:58:20 +0000 | [diff] [blame] | 361 | /* Read PM1_CNT */ |
| 362 | reg32 = inl(DEFAULT_PMBASE + 0x04); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 363 | printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); |
Stefan Reinauer | a5fdadf | 2009-07-21 21:58:20 +0000 | [diff] [blame] | 364 | if (((reg32 >> 10) & 7) == 5) { |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 365 | #if CONFIG_HAVE_ACPI_RESUME |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 366 | printk(BIOS_DEBUG, "Resume from S3 detected.\n"); |
Stefan Reinauer | a5fdadf | 2009-07-21 21:58:20 +0000 | [diff] [blame] | 367 | boot_mode = 2; |
| 368 | /* Clear SLP_TYPE. This will break stage2 but |
| 369 | * we care for that when we get there. |
| 370 | */ |
| 371 | outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 372 | |
Stefan Reinauer | a5fdadf | 2009-07-21 21:58:20 +0000 | [diff] [blame] | 373 | #else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 374 | printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); |
Stefan Reinauer | a5fdadf | 2009-07-21 21:58:20 +0000 | [diff] [blame] | 375 | #endif |
| 376 | } |
| 377 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 378 | /* Enable SPD ROMs and DDR-II DRAM */ |
| 379 | enable_smbus(); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 380 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 381 | #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 382 | dump_spd_registers(); |
| 383 | #endif |
| 384 | |
| 385 | sdram_initialize(boot_mode); |
| 386 | |
| 387 | /* Perform some initialization that must run before stage2 */ |
| 388 | early_ich7_init(); |
| 389 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 390 | /* This should probably go away. Until now it is required |
| 391 | * and mainboard specific |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 392 | */ |
| 393 | rcba_config(); |
| 394 | |
| 395 | /* Chipset Errata! */ |
| 396 | fixup_i945_errata(); |
| 397 | |
| 398 | /* Initialize the internal PCIe links before we go into stage2 */ |
| 399 | i945_late_initialization(); |
| 400 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 401 | #if !CONFIG_HAVE_ACPI_RESUME |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 402 | #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 |
Uwe Hermann | 01ce601 | 2010-03-05 10:03:50 +0000 | [diff] [blame] | 403 | #if CONFIG_DEBUG_RAM_SETUP |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 404 | sdram_dump_mchbar_registers(); |
| 405 | #endif |
| 406 | |
| 407 | { |
| 408 | /* This will not work if TSEG is in place! */ |
| 409 | u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); |
| 410 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 411 | printk(BIOS_DEBUG, "TOM: 0x%08x\n", tom); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 412 | ram_check(0x00000000, 0x000a0000); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 413 | //ram_check(0x00100000, tom); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 414 | } |
| 415 | #endif |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 416 | #endif |
| 417 | |
Stefan Reinauer | e0d607a | 2010-03-28 21:31:30 +0000 | [diff] [blame] | 418 | quick_ram_check(); |
| 419 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 420 | MCHBAR16(SSKPD) = 0xCAFE; |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 421 | |
| 422 | #if CONFIG_HAVE_ACPI_RESUME |
| 423 | /* Start address of high memory tables */ |
| 424 | unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; |
| 425 | |
| 426 | /* If there is no high memory area, we didn't boot before, so |
| 427 | * this is not a resume. In that case we just create the cbmem toc. |
| 428 | */ |
| 429 | if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { |
| 430 | void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); |
| 431 | |
| 432 | /* copy 1MB - 64K to high tables ram_base to prevent memory corruption |
| 433 | * through stage 2. We could keep stuff like stack and heap in high tables |
| 434 | * memory completely, but that's a wonderful clean up task for another |
| 435 | * day. |
| 436 | */ |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 437 | if (resume_backup_memory) |
Stefan Reinauer | de3206a | 2010-02-22 06:09:43 +0000 | [diff] [blame] | 438 | memcpy(resume_backup_memory, (void *)CONFIG_RAMBASE, HIGH_MEMORY_SAVE); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 439 | |
| 440 | /* Magic for S3 resume */ |
| 441 | pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); |
| 442 | } |
| 443 | #endif |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 444 | } |