Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2008 coresystems GmbH |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 19 | * MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | // __ROMCC__ means: use "unsigned" for device, not a struct. |
| 23 | #define __ROMCC__ |
| 24 | |
| 25 | #include <stdint.h> |
| 26 | #include <arch/io.h> |
| 27 | #include <arch/romcc_io.h> |
| 28 | #include <device/pci_def.h> |
| 29 | #include <device/pnp_def.h> |
| 30 | #include <cpu/x86/lapic.h> |
| 31 | |
| 32 | #include "superio/winbond/w83627thg/w83627thg.h" |
| 33 | |
| 34 | #include "option_table.h" |
| 35 | #include "pc80/mc146818rtc_early.c" |
| 36 | |
| 37 | #include "pc80/serial.c" |
| 38 | #include "arch/i386/lib/console.c" |
| 39 | #include <cpu/x86/bist.h> |
| 40 | |
| 41 | #include "ram/ramtest.c" |
| 42 | #include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" |
| 43 | #include "reset.c" |
| 44 | #include "superio/winbond/w83627thg/w83627thg_early_serial.c" |
| 45 | |
| 46 | #include "northbridge/intel/i945/udelay.c" |
| 47 | |
| 48 | #if CONFIG_USE_INIT == 0 |
| 49 | #include "lib/memcpy.c" |
| 50 | #endif |
| 51 | |
| 52 | #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) |
| 53 | |
| 54 | #include "northbridge/intel/i945/ich7.h" |
| 55 | static void setup_ich7_gpios(void) |
| 56 | { |
| 57 | /* TODO: This is highly board specific and should be moved */ |
| 58 | printk_debug(" GPIOS..."); |
| 59 | /* General Registers */ |
| 60 | outl(0x1f1ff7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ |
| 61 | outl(0xe0e8efc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ |
| 62 | outl(0xebffeeff, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ |
| 63 | /* Output Control Registers */ |
| 64 | outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ |
| 65 | /* Input Control Registers */ |
| 66 | outl(0x00002180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ |
| 67 | outl(0x000000ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ |
| 68 | outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ |
| 69 | outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ |
| 70 | } |
| 71 | |
| 72 | #include "northbridge/intel/i945/early_init.c" |
| 73 | |
| 74 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 75 | { |
| 76 | return smbus_read_byte(device, address); |
| 77 | } |
| 78 | |
| 79 | /* Usually system firmware turns off system memory clock signals to |
| 80 | * unused SO-DIMM slots to reduce EMI and power consumption. |
| 81 | * However, the Kontron 986LCD-M does not like unused clock signals to |
| 82 | * be disabled. If other similar mainboard occur, it would make sense |
| 83 | * to make this an entry in the sysinfo structure, and pre-initialize that |
| 84 | * structure in the mainboard's auto.c main() function. For now a |
| 85 | * #define will do. |
| 86 | */ |
| 87 | #define OVERRIDE_CLOCK_DISABLE 1 |
| 88 | #include "northbridge/intel/i945/raminit.h" |
| 89 | #include "northbridge/intel/i945/raminit.c" |
| 90 | #include "northbridge/intel/i945/reset_test.c" |
| 91 | #include "northbridge/intel/i945/errata.c" |
| 92 | #include "debug.c" |
| 93 | |
| 94 | static void ich7_enable_lpc(void) |
| 95 | { |
| 96 | // Enable Serial IRQ |
| 97 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); |
| 98 | // Set COM1/COM2 decode range |
| 99 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); |
| 100 | // Enable COM1/COM2/KBD/SuperIO1+2 |
| 101 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b); |
| 102 | // Enable HWM at 0xa00 |
| 103 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x0a01); |
| 104 | // COM3 decode |
| 105 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9); |
| 106 | // COM4 decode |
| 107 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9); |
| 108 | // io 0x300 decode |
| 109 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); |
| 110 | } |
| 111 | |
| 112 | |
| 113 | /* This box has two superios, so enabling serial becomes slightly excessive. |
| 114 | * We disable a lot of stuff to make sure that there are no conflicts between |
| 115 | * the two. Also set up the GPIOs from the beginning. This is the "no schematic |
| 116 | * but safe anyways" method. |
| 117 | */ |
| 118 | static void early_superio_config_w83627thg(void) |
| 119 | { |
| 120 | device_t dev; |
| 121 | |
| 122 | dev=PNP_DEV(0x2e, W83627THG_SP1); |
| 123 | pnp_enter_ext_func_mode(dev); |
| 124 | |
| 125 | pnp_set_logical_device(dev); |
| 126 | pnp_set_enable(dev, 0); |
| 127 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); |
| 128 | pnp_set_irq(dev, PNP_IDX_IRQ0, 4); |
| 129 | pnp_set_enable(dev, 1); |
| 130 | |
| 131 | dev=PNP_DEV(0x2e, W83627THG_SP2); |
| 132 | pnp_set_logical_device(dev); |
| 133 | pnp_set_enable(dev, 0); |
| 134 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); |
| 135 | pnp_set_irq(dev, PNP_IDX_IRQ0, 3); |
| 136 | // pnp_write_config(dev, 0xf1, 4); // IRMODE0 |
| 137 | pnp_set_enable(dev, 1); |
| 138 | |
| 139 | dev=PNP_DEV(0x2e, W83627THG_KBC); |
| 140 | pnp_set_logical_device(dev); |
| 141 | pnp_set_enable(dev, 0); |
| 142 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); |
| 143 | pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); |
| 144 | // pnp_write_config(dev, 0xf0, 0x82); |
| 145 | pnp_set_enable(dev, 1); |
| 146 | |
| 147 | dev=PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1); |
| 148 | pnp_set_logical_device(dev); |
| 149 | pnp_set_enable(dev, 0); |
| 150 | pnp_write_config(dev, 0xf5, 0xff); // invert all GPIOs |
| 151 | pnp_set_enable(dev, 1); |
| 152 | |
| 153 | dev=PNP_DEV(0x2e, W83627THG_GPIO2); |
| 154 | pnp_set_logical_device(dev); |
| 155 | pnp_set_enable(dev, 1); // Just enable it |
| 156 | |
| 157 | dev=PNP_DEV(0x2e, W83627THG_GPIO3); |
| 158 | pnp_set_logical_device(dev); |
| 159 | pnp_set_enable(dev, 0); |
| 160 | pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output |
| 161 | pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 |
| 162 | pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient |
| 163 | |
| 164 | dev=PNP_DEV(0x2e, W83627THG_FDC); |
| 165 | pnp_set_logical_device(dev); |
| 166 | pnp_set_enable(dev, 0); |
| 167 | |
| 168 | dev=PNP_DEV(0x2e, W83627THG_PP); |
| 169 | pnp_set_logical_device(dev); |
| 170 | pnp_set_enable(dev, 0); |
| 171 | |
Stefan Reinauer | 54309d6 | 2009-01-20 22:53:10 +0000 | [diff] [blame^] | 172 | /* Enable HWM */ |
| 173 | dev=PNP_DEV(0x2e, W83627THG_HWM); |
| 174 | pnp_set_logical_device(dev); |
| 175 | pnp_set_enable(dev, 0); |
| 176 | pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); |
| 177 | pnp_set_enable(dev, 1); |
| 178 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 179 | pnp_exit_ext_func_mode(dev); |
| 180 | |
| 181 | dev=PNP_DEV(0x4e, W83627THG_SP1); |
| 182 | pnp_enter_ext_func_mode(dev); |
| 183 | |
| 184 | pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values |
| 185 | pnp_set_enable(dev, 0); |
| 186 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8); |
| 187 | pnp_set_irq(dev, PNP_IDX_IRQ0, 11); |
| 188 | pnp_set_enable(dev, 1); |
| 189 | |
| 190 | dev=PNP_DEV(0x4e, W83627THG_SP2); |
| 191 | pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values |
| 192 | pnp_set_enable(dev, 0); |
| 193 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8); |
| 194 | pnp_set_irq(dev, PNP_IDX_IRQ0, 10); |
| 195 | pnp_set_enable(dev, 1); |
| 196 | |
| 197 | dev=PNP_DEV(0x4e, W83627THG_FDC); |
| 198 | pnp_set_logical_device(dev); |
| 199 | pnp_set_enable(dev, 0); |
| 200 | |
| 201 | dev=PNP_DEV(0x4e, W83627THG_PP); |
| 202 | pnp_set_logical_device(dev); |
| 203 | pnp_set_enable(dev, 0); |
| 204 | |
| 205 | dev=PNP_DEV(0x4e, W83627THG_KBC); |
| 206 | pnp_set_logical_device(dev); |
| 207 | pnp_set_enable(dev, 0); |
| 208 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x00); |
| 209 | pnp_set_iobase(dev, PNP_IDX_IO1, 0x00); |
| 210 | |
| 211 | pnp_exit_ext_func_mode(dev); |
| 212 | } |
| 213 | |
| 214 | static void rcba_config(void) |
| 215 | { |
| 216 | /* Set up virtual channel 0 */ |
| 217 | //RCBA32(0x0014) = 0x80000001; |
| 218 | //RCBA32(0x001c) = 0x03128010; |
| 219 | |
| 220 | /* Device 1f interrupt pin register */ |
| 221 | RCBA32(0x3100) = 0x00042210; |
| 222 | /* Device 1d interrupt pin register */ |
| 223 | RCBA32(0x310c) = 0x00214321; |
| 224 | |
| 225 | /* dev irq route register */ |
| 226 | RCBA16(0x3140) = 0x0132; |
| 227 | RCBA16(0x3142) = 0x3241; |
| 228 | RCBA16(0x3144) = 0x0237; |
| 229 | RCBA16(0x3146) = 0x3210; |
| 230 | RCBA16(0x3148) = 0x3210; |
| 231 | |
| 232 | /* Enable IOAPIC */ |
| 233 | RCBA8(0x31ff) = 0x03; |
| 234 | |
| 235 | /* Enable upper 128bytes of CMOS */ |
| 236 | RCBA32(0x3400) = (1 << 2); |
| 237 | |
| 238 | /* Disable unused devices */ |
| 239 | RCBA32(0x3418) = 0x000e0063; |
| 240 | |
| 241 | /* Enable PCIe Root Port Clock Gate */ |
| 242 | // RCBA32(0x341c) = 0x00000001; |
| 243 | } |
| 244 | |
| 245 | static void early_ich7_init(void) |
| 246 | { |
| 247 | uint8_t reg8; |
| 248 | uint32_t reg32; |
| 249 | |
| 250 | // program secondary mlt XXX byte? |
| 251 | pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); |
| 252 | |
| 253 | // reset rtc power status |
| 254 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); |
| 255 | reg8 &= ~(1 << 2); |
| 256 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); |
| 257 | |
| 258 | // usb transient disconnect |
| 259 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); |
| 260 | reg8 |= (3 << 0); |
| 261 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); |
| 262 | |
| 263 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); |
| 264 | reg32 |= (1 << 29) | (1 << 17); |
| 265 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); |
| 266 | |
| 267 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); |
| 268 | reg32 |= (1 << 31) | (1 << 27); |
| 269 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); |
| 270 | |
| 271 | RCBA32(0x0088) = 0x0011d000; |
| 272 | RCBA16(0x01fc) = 0x060f; |
| 273 | RCBA32(0x01f4) = 0x86000040; |
| 274 | RCBA32(0x0214) = 0x10030549; |
| 275 | RCBA32(0x0218) = 0x00020504; |
| 276 | RCBA8(0x0220) = 0xc5; |
| 277 | reg32 = RCBA32(0x3410); |
| 278 | reg32 |= (1 << 6); |
| 279 | RCBA32(0x3410) = reg32; |
| 280 | reg32 = RCBA32(0x3430); |
| 281 | reg32 &= ~(3 << 0); |
| 282 | reg32 |= (1 << 0); |
| 283 | RCBA32(0x3430) = reg32; |
| 284 | RCBA32(0x3418) |= (1 << 0); |
| 285 | RCBA16(0x0200) = 0x2008; |
| 286 | RCBA8(0x2027) = 0x0d; |
| 287 | RCBA16(0x3e08) |= (1 << 7); |
| 288 | RCBA16(0x3e48) |= (1 << 7); |
| 289 | RCBA32(0x3e0e) |= (1 << 7); |
| 290 | RCBA32(0x3e4e) |= (1 << 7); |
| 291 | |
| 292 | // next step only on ich7m b0 and later: |
| 293 | reg32 = RCBA32(0x2034); |
| 294 | reg32 &= ~(0x0f << 16); |
| 295 | reg32 |= (5 << 16); |
| 296 | RCBA32(0x2034) = reg32; |
| 297 | } |
| 298 | |
| 299 | #if USE_FALLBACK_IMAGE == 1 |
| 300 | #include "southbridge/intel/i82801gx/cmos_failover.c" |
| 301 | #endif |
| 302 | |
| 303 | void real_main(unsigned long bist) |
| 304 | { |
| 305 | int boot_mode = 0; |
| 306 | |
| 307 | if (bist == 0) { |
| 308 | enable_lapic(); |
| 309 | } |
| 310 | |
| 311 | ich7_enable_lpc(); |
| 312 | early_superio_config_w83627thg(); |
| 313 | |
| 314 | /* Set up the console */ |
| 315 | uart_init(); |
| 316 | console_init(); |
| 317 | |
| 318 | /* Halt if there was a built in self test failure */ |
| 319 | report_bist_failure(bist); |
| 320 | |
| 321 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
| 322 | printk_debug("soft reset detected.\n"); |
| 323 | boot_mode = 1; |
| 324 | } |
| 325 | |
| 326 | /* Perform some early chipset initialization required |
| 327 | * before RAM initialization can work |
| 328 | */ |
| 329 | i945_early_initialization(); |
| 330 | |
| 331 | /* Enable SPD ROMs and DDR-II DRAM */ |
| 332 | enable_smbus(); |
| 333 | |
| 334 | #if DEFAULT_CONSOLE_LOGLEVEL > 8 |
| 335 | dump_spd_registers(); |
| 336 | #endif |
| 337 | |
| 338 | sdram_initialize(boot_mode); |
| 339 | |
| 340 | /* Perform some initialization that must run before stage2 */ |
| 341 | early_ich7_init(); |
| 342 | |
| 343 | /* This should probably go away. Until now it is required |
| 344 | * and mainboard specific |
| 345 | */ |
| 346 | rcba_config(); |
| 347 | |
| 348 | /* Chipset Errata! */ |
| 349 | fixup_i945_errata(); |
| 350 | |
| 351 | /* Initialize the internal PCIe links before we go into stage2 */ |
| 352 | i945_late_initialization(); |
| 353 | |
| 354 | #if DEFAULT_CONSOLE_LOGLEVEL > 8 |
| 355 | #if defined(DEBUG_RAM_SETUP) |
| 356 | sdram_dump_mchbar_registers(); |
| 357 | #endif |
| 358 | |
| 359 | { |
| 360 | /* This will not work if TSEG is in place! */ |
| 361 | u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); |
| 362 | |
| 363 | printk_debug("TOM: 0x%08x\n", tom); |
| 364 | ram_check(0x00000000, 0x000a0000); |
| 365 | ram_check(0x00100000, tom); |
| 366 | } |
| 367 | #endif |
| 368 | MCHBAR16(SSKPD) = 0xCAFE; |
| 369 | } |
| 370 | |
| 371 | #include "cpu/intel/model_6ex/cache_as_ram_disable.c" |