Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 3 | * |
Stefan Reinauer | de3206a | 2010-02-22 06:09:43 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007-2010 coresystems GmbH |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 5 | * |
Uwe Hermann | 2bb4acf | 2010-03-01 17:19:55 +0000 | [diff] [blame] | 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 16 | #include <stdint.h> |
Elyes HAOUAS | d07048a | 2019-04-21 20:17:11 +0200 | [diff] [blame] | 17 | #include <cf9_reset.h> |
Elyes HAOUAS | 5d4cf36 | 2018-08-06 09:58:28 +0200 | [diff] [blame] | 18 | #include <console/console.h> |
Kyösti Mälkki | cd7a70f | 2019-08-17 20:51:08 +0300 | [diff] [blame] | 19 | #include <arch/romstage.h> |
Elyes HAOUAS | 5d4cf36 | 2018-08-06 09:58:28 +0200 | [diff] [blame] | 20 | #include <cpu/x86/lapic.h> |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 21 | #include <device/pci_def.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 22 | #include <device/pci_ops.h> |
Kyösti Mälkki | 3855c01 | 2019-03-03 08:45:19 +0200 | [diff] [blame] | 23 | #include <device/pnp_ops.h> |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 24 | #include <device/pnp_def.h> |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 25 | #include <pc80/mc146818rtc.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 26 | #include <northbridge/intel/i945/i945.h> |
| 27 | #include <northbridge/intel/i945/raminit.h> |
| 28 | #include <southbridge/intel/i82801gx/i82801gx.h> |
Patrick Rudolph | 425e75a | 2019-03-24 15:06:17 +0100 | [diff] [blame] | 29 | #include <southbridge/intel/common/pmclib.h> |
Elyes HAOUAS | 5d4cf36 | 2018-08-06 09:58:28 +0200 | [diff] [blame] | 30 | #include <superio/winbond/common/winbond.h> |
| 31 | #include <superio/winbond/w83627thg/w83627thg.h> |
| 32 | |
| 33 | #include "option_table.h" |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 34 | |
Uwe Hermann | 57b2ff8 | 2010-11-21 17:29:59 +0000 | [diff] [blame] | 35 | #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) |
| 36 | |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame^] | 37 | /* Override the default lpc decode ranges */ |
| 38 | static void mb_lpc_decode(void) |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 39 | { |
Patrick Georgi | a470019 | 2011-01-27 07:39:38 +0000 | [diff] [blame] | 40 | int lpt_en = 0; |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 41 | if (read_option(lpt, 0) != 0) |
| 42 | lpt_en = LPT_LPC_EN; /* enable LPT */ |
| 43 | |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame^] | 44 | pci_update_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 45 | } |
| 46 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 47 | /* This box has two superios, so enabling serial becomes slightly excessive. |
| 48 | * We disable a lot of stuff to make sure that there are no conflicts between |
| 49 | * the two. Also set up the GPIOs from the beginning. This is the "no schematic |
| 50 | * but safe anyways" method. |
| 51 | */ |
| 52 | static void early_superio_config_w83627thg(void) |
| 53 | { |
Antonello Dettori | 9ec1123 | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 54 | pnp_devfn_t dev; |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 55 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 56 | dev = PNP_DEV(0x2e, W83627THG_SP1); |
Elyes HAOUAS | 5d4cf36 | 2018-08-06 09:58:28 +0200 | [diff] [blame] | 57 | pnp_enter_conf_state(dev); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 58 | |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 59 | pnp_write_config(dev, 0x24, 0xc6); /* PNPCSV */ |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 60 | |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 61 | pnp_write_config(dev, 0x29, 0x43); /* GPIO settings */ |
| 62 | pnp_write_config(dev, 0x2a, 0x40); /* GPIO settings */ |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 63 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 64 | dev = PNP_DEV(0x2e, W83627THG_SP1); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 65 | pnp_set_logical_device(dev); |
| 66 | pnp_set_enable(dev, 0); |
| 67 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); |
| 68 | pnp_set_irq(dev, PNP_IDX_IRQ0, 4); |
| 69 | pnp_set_enable(dev, 1); |
| 70 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 71 | dev = PNP_DEV(0x2e, W83627THG_SP2); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 72 | pnp_set_logical_device(dev); |
| 73 | pnp_set_enable(dev, 0); |
| 74 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); |
| 75 | pnp_set_irq(dev, PNP_IDX_IRQ0, 3); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 76 | pnp_set_enable(dev, 1); |
| 77 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 78 | dev = PNP_DEV(0x2e, W83627THG_KBC); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 79 | pnp_set_logical_device(dev); |
| 80 | pnp_set_enable(dev, 0); |
| 81 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); |
| 82 | pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 83 | pnp_set_enable(dev, 1); |
| 84 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 85 | dev = PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 86 | pnp_set_logical_device(dev); |
| 87 | pnp_set_enable(dev, 0); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 88 | pnp_write_config(dev, 0xf5, 0xff); /* invert all GPIOs */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 89 | pnp_set_enable(dev, 1); |
| 90 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 91 | dev = PNP_DEV(0x2e, W83627THG_GPIO2); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 92 | pnp_set_logical_device(dev); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 93 | pnp_set_enable(dev, 1); /* Just enable it */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 94 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 95 | dev = PNP_DEV(0x2e, W83627THG_GPIO3); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 96 | pnp_set_logical_device(dev); |
| 97 | pnp_set_enable(dev, 0); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 98 | pnp_write_config(dev, 0xf0, 0xfb); /* GPIO bit 2 is output */ |
| 99 | pnp_write_config(dev, 0xf1, 0x00); /* GPIO bit 2 is 0 */ |
| 100 | pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO3+4. pnp_set_enable is not sufficient */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 101 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 102 | dev = PNP_DEV(0x2e, W83627THG_FDC); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 103 | pnp_set_logical_device(dev); |
| 104 | pnp_set_enable(dev, 0); |
| 105 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 106 | dev = PNP_DEV(0x2e, W83627THG_PP); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 107 | pnp_set_logical_device(dev); |
| 108 | pnp_set_enable(dev, 0); |
| 109 | |
Stefan Reinauer | 54309d6 | 2009-01-20 22:53:10 +0000 | [diff] [blame] | 110 | /* Enable HWM */ |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 111 | dev = PNP_DEV(0x2e, W83627THG_HWM); |
Stefan Reinauer | 54309d6 | 2009-01-20 22:53:10 +0000 | [diff] [blame] | 112 | pnp_set_logical_device(dev); |
| 113 | pnp_set_enable(dev, 0); |
| 114 | pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); |
| 115 | pnp_set_enable(dev, 1); |
| 116 | |
Elyes HAOUAS | 5d4cf36 | 2018-08-06 09:58:28 +0200 | [diff] [blame] | 117 | pnp_exit_conf_state(dev); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 118 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 119 | dev = PNP_DEV(0x4e, W83627THG_SP1); |
Elyes HAOUAS | 5d4cf36 | 2018-08-06 09:58:28 +0200 | [diff] [blame] | 120 | pnp_enter_conf_state(dev); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 121 | |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 122 | pnp_set_logical_device(dev); /* Set COM3 to sane non-conflicting values */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 123 | pnp_set_enable(dev, 0); |
| 124 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8); |
| 125 | pnp_set_irq(dev, PNP_IDX_IRQ0, 11); |
| 126 | pnp_set_enable(dev, 1); |
| 127 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 128 | dev = PNP_DEV(0x4e, W83627THG_SP2); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 129 | pnp_set_logical_device(dev); /* Set COM4 to sane non-conflicting values */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 130 | pnp_set_enable(dev, 0); |
| 131 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8); |
| 132 | pnp_set_irq(dev, PNP_IDX_IRQ0, 10); |
| 133 | pnp_set_enable(dev, 1); |
| 134 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 135 | dev = PNP_DEV(0x4e, W83627THG_FDC); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 136 | pnp_set_logical_device(dev); |
| 137 | pnp_set_enable(dev, 0); |
| 138 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 139 | dev = PNP_DEV(0x4e, W83627THG_PP); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 140 | pnp_set_logical_device(dev); |
| 141 | pnp_set_enable(dev, 0); |
| 142 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 143 | dev = PNP_DEV(0x4e, W83627THG_KBC); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 144 | pnp_set_logical_device(dev); |
| 145 | pnp_set_enable(dev, 0); |
| 146 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x00); |
| 147 | pnp_set_iobase(dev, PNP_IDX_IO1, 0x00); |
| 148 | |
Elyes HAOUAS | 5d4cf36 | 2018-08-06 09:58:28 +0200 | [diff] [blame] | 149 | pnp_exit_conf_state(dev); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 150 | } |
| 151 | |
| 152 | static void rcba_config(void) |
| 153 | { |
| 154 | /* Set up virtual channel 0 */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 155 | |
| 156 | /* Device 1f interrupt pin register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 157 | RCBA32(D31IP) = 0x00042210; |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 158 | /* Device 1d interrupt pin register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 159 | RCBA32(D28IP) = 0x00214321; |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 160 | |
| 161 | /* dev irq route register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 162 | RCBA16(D31IR) = 0x0132; |
| 163 | RCBA16(D30IR) = 0x3241; |
| 164 | RCBA16(D29IR) = 0x0237; |
| 165 | RCBA16(D28IR) = 0x3210; |
| 166 | RCBA16(D27IR) = 0x3210; |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 167 | |
| 168 | /* Enable IOAPIC */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame] | 169 | RCBA8(OIC) = 0x03; |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 170 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 171 | /* Enable PCIe Root Port Clock Gate */ |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 172 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 173 | } |
| 174 | |
| 175 | static void early_ich7_init(void) |
| 176 | { |
| 177 | uint8_t reg8; |
| 178 | uint32_t reg32; |
| 179 | |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 180 | /* program secondary mlt XXX byte? */ |
Elyes HAOUAS | 6df210b | 2019-10-25 14:05:17 +0200 | [diff] [blame] | 181 | pci_write_config8(PCI_DEV(0, 0x1e, 0), SMLT, 0x20); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 182 | |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 183 | /* reset rtc power status */ |
Elyes HAOUAS | 6df210b | 2019-10-25 14:05:17 +0200 | [diff] [blame] | 184 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3); |
| 185 | reg8 &= ~RTC_BATTERY_DEAD; |
| 186 | pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 187 | |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 188 | /* usb transient disconnect */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 189 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); |
| 190 | reg8 |= (3 << 0); |
| 191 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); |
| 192 | |
| 193 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); |
| 194 | reg32 |= (1 << 29) | (1 << 17); |
| 195 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); |
| 196 | |
| 197 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); |
| 198 | reg32 |= (1 << 31) | (1 << 27); |
| 199 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); |
| 200 | |
Arthur Heymans | 2437fe9 | 2019-10-04 13:59:29 +0200 | [diff] [blame] | 201 | ich7_setup_cir(); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 202 | } |
| 203 | |
Kyösti Mälkki | 157b189 | 2019-08-16 14:02:25 +0300 | [diff] [blame] | 204 | void mainboard_romstage_entry(void) |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 205 | { |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 206 | int s3resume = 0; |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 207 | |
Kyösti Mälkki | 157b189 | 2019-08-16 14:02:25 +0300 | [diff] [blame] | 208 | enable_lapic(); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 209 | |
Arthur Heymans | fecf777 | 2019-11-09 14:19:04 +0100 | [diff] [blame^] | 210 | i82801gx_lpc_setup(); |
| 211 | mb_lpc_decode(); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 212 | early_superio_config_w83627thg(); |
| 213 | |
| 214 | /* Set up the console */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 215 | console_init(); |
| 216 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 217 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
Elyes HAOUAS | d07048a | 2019-04-21 20:17:11 +0200 | [diff] [blame] | 218 | system_reset(); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 219 | } |
| 220 | |
| 221 | /* Perform some early chipset initialization required |
| 222 | * before RAM initialization can work |
| 223 | */ |
| 224 | i945_early_initialization(); |
| 225 | |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 226 | s3resume = southbridge_detect_s3_resume(); |
Stefan Reinauer | a5fdadf | 2009-07-21 21:58:20 +0000 | [diff] [blame] | 227 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 228 | /* Enable SPD ROMs and DDR-II DRAM */ |
| 229 | enable_smbus(); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 230 | |
Kyösti Mälkki | 346d201 | 2019-03-23 10:07:16 +0200 | [diff] [blame] | 231 | if (CONFIG(DEBUG_RAM_SETUP)) |
| 232 | dump_spd_registers(); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 233 | |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 234 | sdram_initialize(s3resume ? 2 : 0, NULL); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 235 | |
| 236 | /* Perform some initialization that must run before stage2 */ |
| 237 | early_ich7_init(); |
| 238 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 239 | /* This should probably go away. Until now it is required |
| 240 | * and mainboard specific |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 241 | */ |
| 242 | rcba_config(); |
| 243 | |
| 244 | /* Chipset Errata! */ |
| 245 | fixup_i945_errata(); |
| 246 | |
| 247 | /* Initialize the internal PCIe links before we go into stage2 */ |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 248 | i945_late_initialization(s3resume); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 249 | } |