Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame^] | 4 | * Copyright (C) 2007-2009 coresystems GmbH |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the GNU General Public License as |
| 8 | * published by the Free Software Foundation; version 2 of |
| 9 | * the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
| 15 | * |
| 16 | * You should have received a copy of the GNU General Public License |
| 17 | * along with this program; if not, write to the Free Software |
| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, |
| 19 | * MA 02110-1301 USA |
| 20 | */ |
| 21 | |
| 22 | // __ROMCC__ means: use "unsigned" for device, not a struct. |
| 23 | #define __ROMCC__ |
| 24 | |
| 25 | #include <stdint.h> |
Patrick Georgi | 12aba82 | 2009-04-30 07:07:22 +0000 | [diff] [blame] | 26 | #include <string.h> |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 27 | #include <arch/io.h> |
| 28 | #include <arch/romcc_io.h> |
| 29 | #include <device/pci_def.h> |
| 30 | #include <device/pnp_def.h> |
| 31 | #include <cpu/x86/lapic.h> |
| 32 | |
| 33 | #include "superio/winbond/w83627thg/w83627thg.h" |
| 34 | |
| 35 | #include "option_table.h" |
| 36 | #include "pc80/mc146818rtc_early.c" |
| 37 | |
| 38 | #include "pc80/serial.c" |
| 39 | #include "arch/i386/lib/console.c" |
| 40 | #include <cpu/x86/bist.h> |
| 41 | |
Stefan Reinauer | a5fdadf | 2009-07-21 21:58:20 +0000 | [diff] [blame] | 42 | #if CONFIG_USBDEBUG_DIRECT |
| 43 | #define DBGP_DEFAULT 1 |
| 44 | #include "southbridge/intel/i82801gx/i82801gx_usb_debug.c" |
| 45 | #include "pc80/usbdebug_direct_serial.c" |
| 46 | #endif |
| 47 | |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 48 | #include "lib/ramtest.c" |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 49 | #include "southbridge/intel/i82801gx/i82801gx_early_smbus.c" |
| 50 | #include "reset.c" |
| 51 | #include "superio/winbond/w83627thg/w83627thg_early_serial.c" |
| 52 | |
| 53 | #include "northbridge/intel/i945/udelay.c" |
| 54 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 55 | #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) |
| 56 | |
Stefan Reinauer | a5fdadf | 2009-07-21 21:58:20 +0000 | [diff] [blame] | 57 | #include "southbridge/intel/i82801gx/i82801gx.h" |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 58 | static void setup_ich7_gpios(void) |
| 59 | { |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 60 | printk_debug(" GPIOS..."); |
| 61 | /* General Registers */ |
| 62 | outl(0x1f1ff7c0, DEFAULT_GPIOBASE + 0x00); /* GPIO_USE_SEL */ |
| 63 | outl(0xe0e8efc3, DEFAULT_GPIOBASE + 0x04); /* GP_IO_SEL */ |
| 64 | outl(0xebffeeff, DEFAULT_GPIOBASE + 0x0c); /* GP_LVL */ |
| 65 | /* Output Control Registers */ |
| 66 | outl(0x00000000, DEFAULT_GPIOBASE + 0x18); /* GPO_BLINK */ |
| 67 | /* Input Control Registers */ |
| 68 | outl(0x00002180, DEFAULT_GPIOBASE + 0x2c); /* GPI_INV */ |
Stefan Reinauer | e1025d0 | 2009-03-11 15:20:36 +0000 | [diff] [blame] | 69 | outl(0x000100ff, DEFAULT_GPIOBASE + 0x30); /* GPIO_USE_SEL2 */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 70 | outl(0x00000030, DEFAULT_GPIOBASE + 0x34); /* GP_IO_SEL2 */ |
| 71 | outl(0x00010035, DEFAULT_GPIOBASE + 0x38); /* GP_LVL */ |
| 72 | } |
| 73 | |
| 74 | #include "northbridge/intel/i945/early_init.c" |
| 75 | |
| 76 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 77 | { |
| 78 | return smbus_read_byte(device, address); |
| 79 | } |
| 80 | |
| 81 | /* Usually system firmware turns off system memory clock signals to |
| 82 | * unused SO-DIMM slots to reduce EMI and power consumption. |
| 83 | * However, the Kontron 986LCD-M does not like unused clock signals to |
| 84 | * be disabled. If other similar mainboard occur, it would make sense |
| 85 | * to make this an entry in the sysinfo structure, and pre-initialize that |
| 86 | * structure in the mainboard's auto.c main() function. For now a |
| 87 | * #define will do. |
| 88 | */ |
| 89 | #define OVERRIDE_CLOCK_DISABLE 1 |
Stefan Reinauer | e1025d0 | 2009-03-11 15:20:36 +0000 | [diff] [blame] | 90 | |
| 91 | #define CHANNEL_XOR_RANDOMIZATION 1 |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 92 | #include "northbridge/intel/i945/raminit.h" |
| 93 | #include "northbridge/intel/i945/raminit.c" |
| 94 | #include "northbridge/intel/i945/reset_test.c" |
| 95 | #include "northbridge/intel/i945/errata.c" |
| 96 | #include "debug.c" |
| 97 | |
| 98 | static void ich7_enable_lpc(void) |
| 99 | { |
| 100 | // Enable Serial IRQ |
| 101 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); |
| 102 | // Set COM1/COM2 decode range |
| 103 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); |
| 104 | // Enable COM1/COM2/KBD/SuperIO1+2 |
| 105 | pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x340b); |
| 106 | // Enable HWM at 0xa00 |
Stefan Reinauer | e1025d0 | 2009-03-11 15:20:36 +0000 | [diff] [blame] | 107 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x00fc0a01); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 108 | // COM3 decode |
| 109 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000403e9); |
| 110 | // COM4 decode |
| 111 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000402e9); |
| 112 | // io 0x300 decode |
| 113 | pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000301); |
| 114 | } |
| 115 | |
| 116 | |
| 117 | /* This box has two superios, so enabling serial becomes slightly excessive. |
| 118 | * We disable a lot of stuff to make sure that there are no conflicts between |
| 119 | * the two. Also set up the GPIOs from the beginning. This is the "no schematic |
| 120 | * but safe anyways" method. |
| 121 | */ |
| 122 | static void early_superio_config_w83627thg(void) |
| 123 | { |
| 124 | device_t dev; |
| 125 | |
| 126 | dev=PNP_DEV(0x2e, W83627THG_SP1); |
| 127 | pnp_enter_ext_func_mode(dev); |
| 128 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame^] | 129 | pnp_write_config(dev, 0x24, 0xc6); // PNPCSV |
| 130 | |
| 131 | pnp_write_config(dev, 0x29, 0x43); // GPIO settings |
| 132 | pnp_write_config(dev, 0x2a, 0x40); // GPIO settings |
| 133 | |
| 134 | dev=PNP_DEV(0x2e, W83627THG_SP1); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 135 | pnp_set_logical_device(dev); |
| 136 | pnp_set_enable(dev, 0); |
| 137 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); |
| 138 | pnp_set_irq(dev, PNP_IDX_IRQ0, 4); |
| 139 | pnp_set_enable(dev, 1); |
| 140 | |
| 141 | dev=PNP_DEV(0x2e, W83627THG_SP2); |
| 142 | pnp_set_logical_device(dev); |
| 143 | pnp_set_enable(dev, 0); |
| 144 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); |
| 145 | pnp_set_irq(dev, PNP_IDX_IRQ0, 3); |
| 146 | // pnp_write_config(dev, 0xf1, 4); // IRMODE0 |
| 147 | pnp_set_enable(dev, 1); |
| 148 | |
| 149 | dev=PNP_DEV(0x2e, W83627THG_KBC); |
| 150 | pnp_set_logical_device(dev); |
| 151 | pnp_set_enable(dev, 0); |
| 152 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); |
| 153 | pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); |
| 154 | // pnp_write_config(dev, 0xf0, 0x82); |
| 155 | pnp_set_enable(dev, 1); |
| 156 | |
| 157 | dev=PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1); |
| 158 | pnp_set_logical_device(dev); |
| 159 | pnp_set_enable(dev, 0); |
| 160 | pnp_write_config(dev, 0xf5, 0xff); // invert all GPIOs |
| 161 | pnp_set_enable(dev, 1); |
| 162 | |
| 163 | dev=PNP_DEV(0x2e, W83627THG_GPIO2); |
| 164 | pnp_set_logical_device(dev); |
| 165 | pnp_set_enable(dev, 1); // Just enable it |
| 166 | |
| 167 | dev=PNP_DEV(0x2e, W83627THG_GPIO3); |
| 168 | pnp_set_logical_device(dev); |
| 169 | pnp_set_enable(dev, 0); |
| 170 | pnp_write_config(dev, 0xf0, 0xfb); // GPIO bit 2 is output |
| 171 | pnp_write_config(dev, 0xf1, 0x00); // GPIO bit 2 is 0 |
| 172 | pnp_write_config(dev, 0x30, 0x03); // Enable GPIO3+4. pnp_set_enable is not sufficient |
| 173 | |
| 174 | dev=PNP_DEV(0x2e, W83627THG_FDC); |
| 175 | pnp_set_logical_device(dev); |
| 176 | pnp_set_enable(dev, 0); |
| 177 | |
| 178 | dev=PNP_DEV(0x2e, W83627THG_PP); |
| 179 | pnp_set_logical_device(dev); |
| 180 | pnp_set_enable(dev, 0); |
| 181 | |
Stefan Reinauer | 54309d6 | 2009-01-20 22:53:10 +0000 | [diff] [blame] | 182 | /* Enable HWM */ |
| 183 | dev=PNP_DEV(0x2e, W83627THG_HWM); |
| 184 | pnp_set_logical_device(dev); |
| 185 | pnp_set_enable(dev, 0); |
| 186 | pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); |
| 187 | pnp_set_enable(dev, 1); |
| 188 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 189 | pnp_exit_ext_func_mode(dev); |
| 190 | |
| 191 | dev=PNP_DEV(0x4e, W83627THG_SP1); |
| 192 | pnp_enter_ext_func_mode(dev); |
| 193 | |
| 194 | pnp_set_logical_device(dev); // Set COM3 to sane non-conflicting values |
| 195 | pnp_set_enable(dev, 0); |
| 196 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8); |
| 197 | pnp_set_irq(dev, PNP_IDX_IRQ0, 11); |
| 198 | pnp_set_enable(dev, 1); |
| 199 | |
| 200 | dev=PNP_DEV(0x4e, W83627THG_SP2); |
| 201 | pnp_set_logical_device(dev); // Set COM4 to sane non-conflicting values |
| 202 | pnp_set_enable(dev, 0); |
| 203 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8); |
| 204 | pnp_set_irq(dev, PNP_IDX_IRQ0, 10); |
| 205 | pnp_set_enable(dev, 1); |
| 206 | |
| 207 | dev=PNP_DEV(0x4e, W83627THG_FDC); |
| 208 | pnp_set_logical_device(dev); |
| 209 | pnp_set_enable(dev, 0); |
| 210 | |
| 211 | dev=PNP_DEV(0x4e, W83627THG_PP); |
| 212 | pnp_set_logical_device(dev); |
| 213 | pnp_set_enable(dev, 0); |
| 214 | |
| 215 | dev=PNP_DEV(0x4e, W83627THG_KBC); |
| 216 | pnp_set_logical_device(dev); |
| 217 | pnp_set_enable(dev, 0); |
| 218 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x00); |
| 219 | pnp_set_iobase(dev, PNP_IDX_IO1, 0x00); |
| 220 | |
| 221 | pnp_exit_ext_func_mode(dev); |
| 222 | } |
| 223 | |
| 224 | static void rcba_config(void) |
| 225 | { |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame^] | 226 | u32 reg32; |
| 227 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 228 | /* Set up virtual channel 0 */ |
| 229 | //RCBA32(0x0014) = 0x80000001; |
| 230 | //RCBA32(0x001c) = 0x03128010; |
| 231 | |
| 232 | /* Device 1f interrupt pin register */ |
| 233 | RCBA32(0x3100) = 0x00042210; |
| 234 | /* Device 1d interrupt pin register */ |
| 235 | RCBA32(0x310c) = 0x00214321; |
| 236 | |
| 237 | /* dev irq route register */ |
| 238 | RCBA16(0x3140) = 0x0132; |
| 239 | RCBA16(0x3142) = 0x3241; |
| 240 | RCBA16(0x3144) = 0x0237; |
| 241 | RCBA16(0x3146) = 0x3210; |
| 242 | RCBA16(0x3148) = 0x3210; |
| 243 | |
| 244 | /* Enable IOAPIC */ |
| 245 | RCBA8(0x31ff) = 0x03; |
| 246 | |
| 247 | /* Enable upper 128bytes of CMOS */ |
| 248 | RCBA32(0x3400) = (1 << 2); |
| 249 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame^] | 250 | /* Now, this is a bit ugly. As per PCI specification, function 0 of a |
| 251 | * device always has to be implemented. So disabling ethernet port 1 |
| 252 | * would essentially disable all three ethernet ports of the mainboard. |
| 253 | * It's possible to rename the ports to achieve compatibility to the |
| 254 | * PCI spec but this will confuse all (static!) tables containing |
| 255 | * interrupt routing information. |
| 256 | * To avoid this, we enable (unused) port 6 and swap it with port 1 |
| 257 | * in the case that ethernet port 1 is disabled. Since no devices |
| 258 | * are connected to that port, we don't have to worry about interrupt |
| 259 | * routing. |
| 260 | */ |
| 261 | int port_shuffle = 0; |
| 262 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 263 | /* Disable unused devices */ |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame^] | 264 | reg32 = FD_ACMOD|FD_ACAUD|FD_PATA; |
| 265 | reg32 |= FD_PCIE6|FD_PCIE5|FD_PCIE4; |
| 266 | |
| 267 | if (read_option(CMOS_VSTART_ethernet1, CMOS_VLEN_ethernet1, 0) != 0) { |
| 268 | printk_debug("Disabling ethernet adapter 1.\n"); |
| 269 | reg32 |= FD_PCIE1; |
| 270 | } |
| 271 | if (read_option(CMOS_VSTART_ethernet2, CMOS_VLEN_ethernet2, 0) != 0) { |
| 272 | printk_debug("Disabling ethernet adapter 2.\n"); |
| 273 | reg32 |= FD_PCIE2; |
| 274 | } else { |
| 275 | if (reg32 & FD_PCIE1) |
| 276 | port_shuffle = 1; |
| 277 | } |
| 278 | if (read_option(CMOS_VSTART_ethernet3, CMOS_VLEN_ethernet3, 0) != 0) { |
| 279 | printk_debug("Disabling ethernet adapter 3.\n"); |
| 280 | reg32 |= FD_PCIE3; |
| 281 | } else { |
| 282 | if (reg32 & FD_PCIE1) |
| 283 | port_shuffle = 1; |
| 284 | } |
| 285 | |
| 286 | if (port_shuffle) { |
| 287 | /* Enable PCIE6 again */ |
| 288 | reg32 &= ~FD_PCIE6; |
| 289 | /* Swap PCIE6 and PCIE1 */ |
| 290 | RCBA32(RPFN) = 0x00043215; |
| 291 | } |
| 292 | |
| 293 | reg32 |= 1; |
| 294 | |
| 295 | RCBA32(0x3418) = reg32; |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 296 | |
| 297 | /* Enable PCIe Root Port Clock Gate */ |
| 298 | // RCBA32(0x341c) = 0x00000001; |
| 299 | } |
| 300 | |
| 301 | static void early_ich7_init(void) |
| 302 | { |
| 303 | uint8_t reg8; |
| 304 | uint32_t reg32; |
| 305 | |
| 306 | // program secondary mlt XXX byte? |
| 307 | pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); |
| 308 | |
| 309 | // reset rtc power status |
| 310 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); |
| 311 | reg8 &= ~(1 << 2); |
| 312 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); |
| 313 | |
| 314 | // usb transient disconnect |
| 315 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); |
| 316 | reg8 |= (3 << 0); |
| 317 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); |
| 318 | |
| 319 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); |
| 320 | reg32 |= (1 << 29) | (1 << 17); |
| 321 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); |
| 322 | |
| 323 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); |
| 324 | reg32 |= (1 << 31) | (1 << 27); |
| 325 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); |
| 326 | |
| 327 | RCBA32(0x0088) = 0x0011d000; |
| 328 | RCBA16(0x01fc) = 0x060f; |
| 329 | RCBA32(0x01f4) = 0x86000040; |
| 330 | RCBA32(0x0214) = 0x10030549; |
| 331 | RCBA32(0x0218) = 0x00020504; |
| 332 | RCBA8(0x0220) = 0xc5; |
| 333 | reg32 = RCBA32(0x3410); |
| 334 | reg32 |= (1 << 6); |
| 335 | RCBA32(0x3410) = reg32; |
| 336 | reg32 = RCBA32(0x3430); |
| 337 | reg32 &= ~(3 << 0); |
| 338 | reg32 |= (1 << 0); |
| 339 | RCBA32(0x3430) = reg32; |
| 340 | RCBA32(0x3418) |= (1 << 0); |
| 341 | RCBA16(0x0200) = 0x2008; |
| 342 | RCBA8(0x2027) = 0x0d; |
| 343 | RCBA16(0x3e08) |= (1 << 7); |
| 344 | RCBA16(0x3e48) |= (1 << 7); |
| 345 | RCBA32(0x3e0e) |= (1 << 7); |
| 346 | RCBA32(0x3e4e) |= (1 << 7); |
| 347 | |
| 348 | // next step only on ich7m b0 and later: |
| 349 | reg32 = RCBA32(0x2034); |
| 350 | reg32 &= ~(0x0f << 16); |
| 351 | reg32 |= (5 << 16); |
| 352 | RCBA32(0x2034) = reg32; |
| 353 | } |
| 354 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 355 | #if CONFIG_USE_FALLBACK_IMAGE == 1 |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 356 | #include "southbridge/intel/i82801gx/cmos_failover.c" |
| 357 | #endif |
| 358 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame^] | 359 | #include <cbmem.h> |
| 360 | |
| 361 | // Now, this needs to be included because it relies on the symbol |
| 362 | // __ROMCC_ being set during CAR stage (in order to compile the |
| 363 | // BSS free versions of the functions). Either rewrite the code |
| 364 | // to be always BSS free, or invent a flag that's better suited than |
| 365 | // __ROMCC__ to determine whether we're in ram init stage (stage 1) |
| 366 | // |
| 367 | #include "lib/cbmem.c" |
| 368 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 369 | void real_main(unsigned long bist) |
| 370 | { |
Stefan Reinauer | a5fdadf | 2009-07-21 21:58:20 +0000 | [diff] [blame] | 371 | u32 reg32; |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 372 | int boot_mode = 0; |
| 373 | |
| 374 | if (bist == 0) { |
| 375 | enable_lapic(); |
| 376 | } |
| 377 | |
| 378 | ich7_enable_lpc(); |
| 379 | early_superio_config_w83627thg(); |
| 380 | |
| 381 | /* Set up the console */ |
| 382 | uart_init(); |
Stefan Reinauer | a5fdadf | 2009-07-21 21:58:20 +0000 | [diff] [blame] | 383 | |
| 384 | #if CONFIG_USBDEBUG_DIRECT |
| 385 | i82801gx_enable_usbdebug_direct(DBGP_DEFAULT); |
| 386 | early_usbdebug_direct_init(); |
| 387 | #endif |
| 388 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 389 | console_init(); |
| 390 | |
| 391 | /* Halt if there was a built in self test failure */ |
| 392 | report_bist_failure(bist); |
| 393 | |
| 394 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
| 395 | printk_debug("soft reset detected.\n"); |
| 396 | boot_mode = 1; |
| 397 | } |
| 398 | |
| 399 | /* Perform some early chipset initialization required |
| 400 | * before RAM initialization can work |
| 401 | */ |
| 402 | i945_early_initialization(); |
| 403 | |
Stefan Reinauer | a5fdadf | 2009-07-21 21:58:20 +0000 | [diff] [blame] | 404 | /* Read PM1_CNT */ |
| 405 | reg32 = inl(DEFAULT_PMBASE + 0x04); |
| 406 | printk_debug("PM1_CNT: %08x\n", reg32); |
| 407 | if (((reg32 >> 10) & 7) == 5) { |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame^] | 408 | #if CONFIG_HAVE_ACPI_RESUME |
Stefan Reinauer | a5fdadf | 2009-07-21 21:58:20 +0000 | [diff] [blame] | 409 | printk_debug("Resume from S3 detected.\n"); |
| 410 | boot_mode = 2; |
| 411 | /* Clear SLP_TYPE. This will break stage2 but |
| 412 | * we care for that when we get there. |
| 413 | */ |
| 414 | outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame^] | 415 | |
Stefan Reinauer | a5fdadf | 2009-07-21 21:58:20 +0000 | [diff] [blame] | 416 | #else |
| 417 | printk_debug("Resume from S3 detected, but disabled.\n"); |
| 418 | #endif |
| 419 | } |
| 420 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 421 | /* Enable SPD ROMs and DDR-II DRAM */ |
| 422 | enable_smbus(); |
| 423 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 424 | #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 425 | dump_spd_registers(); |
| 426 | #endif |
| 427 | |
| 428 | sdram_initialize(boot_mode); |
| 429 | |
| 430 | /* Perform some initialization that must run before stage2 */ |
| 431 | early_ich7_init(); |
| 432 | |
| 433 | /* This should probably go away. Until now it is required |
| 434 | * and mainboard specific |
| 435 | */ |
| 436 | rcba_config(); |
| 437 | |
| 438 | /* Chipset Errata! */ |
| 439 | fixup_i945_errata(); |
| 440 | |
| 441 | /* Initialize the internal PCIe links before we go into stage2 */ |
| 442 | i945_late_initialization(); |
| 443 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame^] | 444 | #if !CONFIG_HAVE_ACPI_RESUME |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 445 | #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 446 | #if defined(DEBUG_RAM_SETUP) |
| 447 | sdram_dump_mchbar_registers(); |
| 448 | #endif |
| 449 | |
| 450 | { |
| 451 | /* This will not work if TSEG is in place! */ |
| 452 | u32 tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); |
| 453 | |
| 454 | printk_debug("TOM: 0x%08x\n", tom); |
| 455 | ram_check(0x00000000, 0x000a0000); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame^] | 456 | //ram_check(0x00100000, tom); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 457 | } |
| 458 | #endif |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame^] | 459 | #endif |
| 460 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 461 | MCHBAR16(SSKPD) = 0xCAFE; |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame^] | 462 | |
| 463 | #if CONFIG_HAVE_ACPI_RESUME |
| 464 | /* Start address of high memory tables */ |
| 465 | unsigned long high_ram_base = get_top_of_ram() - HIGH_MEMORY_SIZE; |
| 466 | |
| 467 | /* If there is no high memory area, we didn't boot before, so |
| 468 | * this is not a resume. In that case we just create the cbmem toc. |
| 469 | */ |
| 470 | if ((boot_mode == 2) && cbmem_reinit((u64)high_ram_base)) { |
| 471 | void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); |
| 472 | |
| 473 | /* copy 1MB - 64K to high tables ram_base to prevent memory corruption |
| 474 | * through stage 2. We could keep stuff like stack and heap in high tables |
| 475 | * memory completely, but that's a wonderful clean up task for another |
| 476 | * day. |
| 477 | */ |
| 478 | if (resume_backup_memory) |
| 479 | memcpy(resume_backup_memory, CONFIG_RAMBASE, HIGH_MEMORY_SAVE); |
| 480 | |
| 481 | /* Magic for S3 resume */ |
| 482 | pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); |
| 483 | } |
| 484 | #endif |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 485 | } |
| 486 | |
| 487 | #include "cpu/intel/model_6ex/cache_as_ram_disable.c" |