Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 3 | * |
Stefan Reinauer | de3206a | 2010-02-22 06:09:43 +0000 | [diff] [blame] | 4 | * Copyright (C) 2007-2010 coresystems GmbH |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 5 | * |
Uwe Hermann | 2bb4acf | 2010-03-01 17:19:55 +0000 | [diff] [blame] | 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; version 2 of the License. |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 14 | */ |
| 15 | |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 16 | /* __PRE_RAM__ means: use "unsigned" for device, not a struct. */ |
Stefan Reinauer | 5e32823 | 2010-03-29 19:19:16 +0000 | [diff] [blame] | 17 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 18 | #include <stdint.h> |
Patrick Georgi | 12aba82 | 2009-04-30 07:07:22 +0000 | [diff] [blame] | 19 | #include <string.h> |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 20 | #include <lib.h> |
Kyösti Mälkki | 12d681b | 2014-06-14 18:51:34 +0300 | [diff] [blame] | 21 | #include <arch/acpi.h> |
Kyösti Mälkki | a7c9611 | 2013-10-13 20:41:57 +0300 | [diff] [blame] | 22 | #include <cbmem.h> |
Paul Menzel | 6c20b65 | 2016-12-29 22:54:02 +0100 | [diff] [blame] | 23 | #include <timestamp.h> |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 24 | #include <arch/io.h> |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 25 | #include <device/pci_def.h> |
| 26 | #include <device/pnp_def.h> |
| 27 | #include <cpu/x86/lapic.h> |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 28 | #include <pc80/mc146818rtc.h> |
Stefan Reinauer | 10ec0fe | 2010-09-25 10:40:47 +0000 | [diff] [blame] | 29 | #include "option_table.h" |
Stefan Reinauer | de3206a | 2010-02-22 06:09:43 +0000 | [diff] [blame] | 30 | #include <console/console.h> |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 31 | #include <cpu/x86/bist.h> |
Kyösti Mälkki | 15fa992 | 2016-06-17 10:00:28 +0300 | [diff] [blame] | 32 | #include <cpu/intel/romstage.h> |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 33 | #include <halt.h> |
Edward O'Callaghan | 4f5a525 | 2014-04-03 14:40:24 +1100 | [diff] [blame] | 34 | #include <superio/winbond/w83627thg/w83627thg.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 35 | #include <northbridge/intel/i945/i945.h> |
| 36 | #include <northbridge/intel/i945/raminit.h> |
| 37 | #include <southbridge/intel/i82801gx/i82801gx.h> |
Patrick Georgi | d083595 | 2010-10-05 09:07:10 +0000 | [diff] [blame] | 38 | |
Uwe Hermann | 57b2ff8 | 2010-11-21 17:29:59 +0000 | [diff] [blame] | 39 | #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) |
| 40 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 41 | static void ich7_enable_lpc(void) |
| 42 | { |
Patrick Georgi | a470019 | 2011-01-27 07:39:38 +0000 | [diff] [blame] | 43 | int lpt_en = 0; |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame^] | 44 | if (read_option(lpt, 0) != 0) |
| 45 | lpt_en = LPT_LPC_EN; /* enable LPT */ |
| 46 | |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 47 | /* Enable Serial IRQ */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame^] | 48 | pci_write_config8(PCI_DEV(0, 0x1f, 0), SERIRQ_CNTL, 0xd0); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 49 | /* Set COM1/COM2 decode range */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame^] | 50 | pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0010); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 51 | /* Enable COM1/COM2/KBD/SuperIO1+2 */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame^] | 52 | pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_EN, CNF2_LPC_EN |
| 53 | | CNF1_LPC_EN | KBC_LPC_EN | FDD_LPC_EN | COMA_LPC_EN |
| 54 | | COMB_LPC_EN | lpt_en); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 55 | /* Enable HWM at 0xa00 */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame^] | 56 | pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x00fc0a01); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 57 | /* COM3 decode */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame^] | 58 | pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN2_DEC, 0x000403e9); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 59 | /* COM4 decode */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame^] | 60 | pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN3_DEC, 0x000402e9); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 61 | /* io 0x300 decode */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame^] | 62 | pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN4_DEC, 0x00000301); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 63 | } |
| 64 | |
Edward O'Callaghan | 2c55b70 | 2014-05-13 23:29:22 +1000 | [diff] [blame] | 65 | /* TODO: superio code should really not be in mainboard */ |
Antonello Dettori | 9ec1123 | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 66 | static void pnp_enter_func_mode(pnp_devfn_t dev) |
Edward O'Callaghan | 2c55b70 | 2014-05-13 23:29:22 +1000 | [diff] [blame] | 67 | { |
| 68 | u16 port = dev >> 8; |
| 69 | outb(0x87, port); |
| 70 | outb(0x87, port); |
| 71 | } |
| 72 | |
Antonello Dettori | 9ec1123 | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 73 | static void pnp_exit_func_mode(pnp_devfn_t dev) |
Edward O'Callaghan | 2c55b70 | 2014-05-13 23:29:22 +1000 | [diff] [blame] | 74 | { |
| 75 | u16 port = dev >> 8; |
| 76 | outb(0xaa, port); |
| 77 | } |
| 78 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 79 | /* This box has two superios, so enabling serial becomes slightly excessive. |
| 80 | * We disable a lot of stuff to make sure that there are no conflicts between |
| 81 | * the two. Also set up the GPIOs from the beginning. This is the "no schematic |
| 82 | * but safe anyways" method. |
| 83 | */ |
| 84 | static void early_superio_config_w83627thg(void) |
| 85 | { |
Antonello Dettori | 9ec1123 | 2016-11-08 18:44:46 +0100 | [diff] [blame] | 86 | pnp_devfn_t dev; |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 87 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 88 | dev = PNP_DEV(0x2e, W83627THG_SP1); |
Edward O'Callaghan | 2c55b70 | 2014-05-13 23:29:22 +1000 | [diff] [blame] | 89 | pnp_enter_func_mode(dev); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 90 | |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 91 | pnp_write_config(dev, 0x24, 0xc6); /* PNPCSV */ |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 92 | |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 93 | pnp_write_config(dev, 0x29, 0x43); /* GPIO settings */ |
| 94 | pnp_write_config(dev, 0x2a, 0x40); /* GPIO settings */ |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 95 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 96 | dev = PNP_DEV(0x2e, W83627THG_SP1); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 97 | pnp_set_logical_device(dev); |
| 98 | pnp_set_enable(dev, 0); |
| 99 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x3f8); |
| 100 | pnp_set_irq(dev, PNP_IDX_IRQ0, 4); |
| 101 | pnp_set_enable(dev, 1); |
| 102 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 103 | dev = PNP_DEV(0x2e, W83627THG_SP2); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 104 | pnp_set_logical_device(dev); |
| 105 | pnp_set_enable(dev, 0); |
| 106 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x2f8); |
| 107 | pnp_set_irq(dev, PNP_IDX_IRQ0, 3); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 108 | pnp_set_enable(dev, 1); |
| 109 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 110 | dev = PNP_DEV(0x2e, W83627THG_KBC); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 111 | pnp_set_logical_device(dev); |
| 112 | pnp_set_enable(dev, 0); |
| 113 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x60); |
| 114 | pnp_set_iobase(dev, PNP_IDX_IO1, 0x64); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 115 | pnp_set_enable(dev, 1); |
| 116 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 117 | dev = PNP_DEV(0x2e, W83627THG_GAME_MIDI_GPIO1); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 118 | pnp_set_logical_device(dev); |
| 119 | pnp_set_enable(dev, 0); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 120 | pnp_write_config(dev, 0xf5, 0xff); /* invert all GPIOs */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 121 | pnp_set_enable(dev, 1); |
| 122 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 123 | dev = PNP_DEV(0x2e, W83627THG_GPIO2); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 124 | pnp_set_logical_device(dev); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 125 | pnp_set_enable(dev, 1); /* Just enable it */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 126 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 127 | dev = PNP_DEV(0x2e, W83627THG_GPIO3); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 128 | pnp_set_logical_device(dev); |
| 129 | pnp_set_enable(dev, 0); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 130 | pnp_write_config(dev, 0xf0, 0xfb); /* GPIO bit 2 is output */ |
| 131 | pnp_write_config(dev, 0xf1, 0x00); /* GPIO bit 2 is 0 */ |
| 132 | pnp_write_config(dev, 0x30, 0x03); /* Enable GPIO3+4. pnp_set_enable is not sufficient */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 133 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 134 | dev = PNP_DEV(0x2e, W83627THG_FDC); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 135 | pnp_set_logical_device(dev); |
| 136 | pnp_set_enable(dev, 0); |
| 137 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 138 | dev = PNP_DEV(0x2e, W83627THG_PP); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 139 | pnp_set_logical_device(dev); |
| 140 | pnp_set_enable(dev, 0); |
| 141 | |
Stefan Reinauer | 54309d6 | 2009-01-20 22:53:10 +0000 | [diff] [blame] | 142 | /* Enable HWM */ |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 143 | dev = PNP_DEV(0x2e, W83627THG_HWM); |
Stefan Reinauer | 54309d6 | 2009-01-20 22:53:10 +0000 | [diff] [blame] | 144 | pnp_set_logical_device(dev); |
| 145 | pnp_set_enable(dev, 0); |
| 146 | pnp_set_iobase(dev, PNP_IDX_IO0, 0xa00); |
| 147 | pnp_set_enable(dev, 1); |
| 148 | |
Edward O'Callaghan | 2c55b70 | 2014-05-13 23:29:22 +1000 | [diff] [blame] | 149 | pnp_exit_func_mode(dev); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 150 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 151 | dev = PNP_DEV(0x4e, W83627THG_SP1); |
Edward O'Callaghan | 2c55b70 | 2014-05-13 23:29:22 +1000 | [diff] [blame] | 152 | pnp_enter_func_mode(dev); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 153 | |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 154 | pnp_set_logical_device(dev); /* Set COM3 to sane non-conflicting values */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 155 | pnp_set_enable(dev, 0); |
| 156 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x3e8); |
| 157 | pnp_set_irq(dev, PNP_IDX_IRQ0, 11); |
| 158 | pnp_set_enable(dev, 1); |
| 159 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 160 | dev = PNP_DEV(0x4e, W83627THG_SP2); |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 161 | pnp_set_logical_device(dev); /* Set COM4 to sane non-conflicting values */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 162 | pnp_set_enable(dev, 0); |
| 163 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x2e8); |
| 164 | pnp_set_irq(dev, PNP_IDX_IRQ0, 10); |
| 165 | pnp_set_enable(dev, 1); |
| 166 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 167 | dev = PNP_DEV(0x4e, W83627THG_FDC); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 168 | pnp_set_logical_device(dev); |
| 169 | pnp_set_enable(dev, 0); |
| 170 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 171 | dev = PNP_DEV(0x4e, W83627THG_PP); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 172 | pnp_set_logical_device(dev); |
| 173 | pnp_set_enable(dev, 0); |
| 174 | |
Elyes HAOUAS | 531b87a | 2016-09-19 09:46:33 -0600 | [diff] [blame] | 175 | dev = PNP_DEV(0x4e, W83627THG_KBC); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 176 | pnp_set_logical_device(dev); |
| 177 | pnp_set_enable(dev, 0); |
| 178 | pnp_set_iobase(dev, PNP_IDX_IO0, 0x00); |
| 179 | pnp_set_iobase(dev, PNP_IDX_IO1, 0x00); |
| 180 | |
Edward O'Callaghan | 2c55b70 | 2014-05-13 23:29:22 +1000 | [diff] [blame] | 181 | pnp_exit_func_mode(dev); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 182 | } |
| 183 | |
| 184 | static void rcba_config(void) |
| 185 | { |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 186 | u32 reg32; |
| 187 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 188 | /* Set up virtual channel 0 */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 189 | |
| 190 | /* Device 1f interrupt pin register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame^] | 191 | RCBA32(D31IP) = 0x00042210; |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 192 | /* Device 1d interrupt pin register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame^] | 193 | RCBA32(D28IP) = 0x00214321; |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 194 | |
| 195 | /* dev irq route register */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame^] | 196 | RCBA16(D31IR) = 0x0132; |
| 197 | RCBA16(D30IR) = 0x3241; |
| 198 | RCBA16(D29IR) = 0x0237; |
| 199 | RCBA16(D28IR) = 0x3210; |
| 200 | RCBA16(D27IR) = 0x3210; |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 201 | |
| 202 | /* Enable IOAPIC */ |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame^] | 203 | RCBA8(OIC) = 0x03; |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 204 | |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 205 | /* Now, this is a bit ugly. As per PCI specification, function 0 of a |
| 206 | * device always has to be implemented. So disabling ethernet port 1 |
| 207 | * would essentially disable all three ethernet ports of the mainboard. |
| 208 | * It's possible to rename the ports to achieve compatibility to the |
| 209 | * PCI spec but this will confuse all (static!) tables containing |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 210 | * interrupt routing information. |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 211 | * To avoid this, we enable (unused) port 6 and swap it with port 1 |
| 212 | * in the case that ethernet port 1 is disabled. Since no devices |
| 213 | * are connected to that port, we don't have to worry about interrupt |
| 214 | * routing. |
| 215 | */ |
| 216 | int port_shuffle = 0; |
| 217 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 218 | /* Disable unused devices */ |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 219 | reg32 = FD_ACMOD|FD_ACAUD|FD_PATA; |
| 220 | reg32 |= FD_PCIE6|FD_PCIE5|FD_PCIE4; |
| 221 | |
Patrick Georgi | b251753 | 2011-05-10 21:53:13 +0000 | [diff] [blame] | 222 | if (read_option(ethernet1, 0) != 0) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 223 | printk(BIOS_DEBUG, "Disabling ethernet adapter 1.\n"); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 224 | reg32 |= FD_PCIE1; |
| 225 | } |
Patrick Georgi | b251753 | 2011-05-10 21:53:13 +0000 | [diff] [blame] | 226 | if (read_option(ethernet2, 0) != 0) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 227 | printk(BIOS_DEBUG, "Disabling ethernet adapter 2.\n"); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 228 | reg32 |= FD_PCIE2; |
| 229 | } else { |
| 230 | if (reg32 & FD_PCIE1) |
| 231 | port_shuffle = 1; |
| 232 | } |
Patrick Georgi | b251753 | 2011-05-10 21:53:13 +0000 | [diff] [blame] | 233 | if (read_option(ethernet3, 0) != 0) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 234 | printk(BIOS_DEBUG, "Disabling ethernet adapter 3.\n"); |
Stefan Reinauer | aca6ec6 | 2009-10-26 17:12:21 +0000 | [diff] [blame] | 235 | reg32 |= FD_PCIE3; |
| 236 | } else { |
| 237 | if (reg32 & FD_PCIE1) |
| 238 | port_shuffle = 1; |
| 239 | } |
| 240 | |
| 241 | if (port_shuffle) { |
| 242 | /* Enable PCIE6 again */ |
| 243 | reg32 &= ~FD_PCIE6; |
| 244 | /* Swap PCIE6 and PCIE1 */ |
| 245 | RCBA32(RPFN) = 0x00043215; |
| 246 | } |
| 247 | |
| 248 | reg32 |= 1; |
| 249 | |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame^] | 250 | RCBA32(FD) = reg32; |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 251 | |
| 252 | /* Enable PCIe Root Port Clock Gate */ |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 253 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 254 | } |
| 255 | |
| 256 | static void early_ich7_init(void) |
| 257 | { |
| 258 | uint8_t reg8; |
| 259 | uint32_t reg32; |
| 260 | |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 261 | /* program secondary mlt XXX byte? */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 262 | pci_write_config8(PCI_DEV(0, 0x1e, 0), 0x1b, 0x20); |
| 263 | |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 264 | /* reset rtc power status */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 265 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); |
| 266 | reg8 &= ~(1 << 2); |
| 267 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, reg8); |
| 268 | |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 269 | /* usb transient disconnect */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 270 | reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xad); |
| 271 | reg8 |= (3 << 0); |
| 272 | pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xad, reg8); |
| 273 | |
| 274 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xfc); |
| 275 | reg32 |= (1 << 29) | (1 << 17); |
| 276 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xfc, reg32); |
| 277 | |
| 278 | reg32 = pci_read_config32(PCI_DEV(0, 0x1d, 7), 0xdc); |
| 279 | reg32 |= (1 << 31) | (1 << 27); |
| 280 | pci_write_config32(PCI_DEV(0, 0x1d, 7), 0xdc, reg32); |
| 281 | |
| 282 | RCBA32(0x0088) = 0x0011d000; |
| 283 | RCBA16(0x01fc) = 0x060f; |
| 284 | RCBA32(0x01f4) = 0x86000040; |
| 285 | RCBA32(0x0214) = 0x10030549; |
| 286 | RCBA32(0x0218) = 0x00020504; |
| 287 | RCBA8(0x0220) = 0xc5; |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame^] | 288 | reg32 = RCBA32(GCS); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 289 | reg32 |= (1 << 6); |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame^] | 290 | RCBA32(GCS) = reg32; |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 291 | reg32 = RCBA32(0x3430); |
| 292 | reg32 &= ~(3 << 0); |
| 293 | reg32 |= (1 << 0); |
| 294 | RCBA32(0x3430) = reg32; |
Arthur Heymans | b451df2 | 2017-08-15 20:59:09 +0200 | [diff] [blame^] | 295 | RCBA32(FD) |= (1 << 0); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 296 | RCBA16(0x0200) = 0x2008; |
| 297 | RCBA8(0x2027) = 0x0d; |
| 298 | RCBA16(0x3e08) |= (1 << 7); |
| 299 | RCBA16(0x3e48) |= (1 << 7); |
| 300 | RCBA32(0x3e0e) |= (1 << 7); |
| 301 | RCBA32(0x3e4e) |= (1 << 7); |
| 302 | |
Elyes HAOUAS | f10b5ff | 2016-10-06 19:49:55 +0200 | [diff] [blame] | 303 | /* next step only on ich7m b0 and later: */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 304 | reg32 = RCBA32(0x2034); |
| 305 | reg32 &= ~(0x0f << 16); |
| 306 | reg32 |= (5 << 16); |
| 307 | RCBA32(0x2034) = reg32; |
| 308 | } |
| 309 | |
Kyösti Mälkki | 15fa992 | 2016-06-17 10:00:28 +0300 | [diff] [blame] | 310 | void mainboard_romstage_entry(unsigned long bist) |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 311 | { |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 312 | int s3resume = 0; |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 313 | |
Paul Menzel | 6c20b65 | 2016-12-29 22:54:02 +0100 | [diff] [blame] | 314 | |
| 315 | timestamp_init(get_initial_timestamp()); |
| 316 | timestamp_add_now(TS_START_ROMSTAGE); |
| 317 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 318 | if (bist == 0) |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 319 | enable_lapic(); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 320 | |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 321 | /* Force PCIRST# */ |
| 322 | pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); |
Stefan Reinauer | bc8613e | 2010-08-25 18:35:42 +0000 | [diff] [blame] | 323 | udelay(200 * 1000); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 324 | pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 325 | |
Stefan Reinauer | bc8613e | 2010-08-25 18:35:42 +0000 | [diff] [blame] | 326 | ich7_enable_lpc(); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 327 | early_superio_config_w83627thg(); |
| 328 | |
| 329 | /* Set up the console */ |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 330 | console_init(); |
| 331 | |
| 332 | /* Halt if there was a built in self test failure */ |
| 333 | report_bist_failure(bist); |
| 334 | |
| 335 | if (MCHBAR16(SSKPD) == 0xCAFE) { |
Stefan Reinauer | bf264e9 | 2010-05-14 19:09:20 +0000 | [diff] [blame] | 336 | printk(BIOS_DEBUG, "soft reset detected, rebooting properly\n"); |
| 337 | outb(0x6, 0xcf9); |
Patrick Georgi | 546953c | 2014-11-29 10:38:17 +0100 | [diff] [blame] | 338 | halt(); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 339 | } |
| 340 | |
| 341 | /* Perform some early chipset initialization required |
| 342 | * before RAM initialization can work |
| 343 | */ |
| 344 | i945_early_initialization(); |
| 345 | |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 346 | s3resume = southbridge_detect_s3_resume(); |
Stefan Reinauer | a5fdadf | 2009-07-21 21:58:20 +0000 | [diff] [blame] | 347 | |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 348 | /* Enable SPD ROMs and DDR-II DRAM */ |
| 349 | enable_smbus(); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 350 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 351 | #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 8 |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 352 | dump_spd_registers(); |
| 353 | #endif |
| 354 | |
Paul Menzel | 6c20b65 | 2016-12-29 22:54:02 +0100 | [diff] [blame] | 355 | timestamp_add_now(TS_BEFORE_INITRAM); |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 356 | sdram_initialize(s3resume ? 2 : 0, NULL); |
Paul Menzel | 6c20b65 | 2016-12-29 22:54:02 +0100 | [diff] [blame] | 357 | timestamp_add_now(TS_AFTER_INITRAM); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 358 | |
| 359 | /* Perform some initialization that must run before stage2 */ |
| 360 | early_ich7_init(); |
| 361 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 362 | /* This should probably go away. Until now it is required |
| 363 | * and mainboard specific |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 364 | */ |
| 365 | rcba_config(); |
| 366 | |
| 367 | /* Chipset Errata! */ |
| 368 | fixup_i945_errata(); |
| 369 | |
| 370 | /* Initialize the internal PCIe links before we go into stage2 */ |
Vladimir Serbinenko | 5560188 | 2014-10-15 20:17:51 +0200 | [diff] [blame] | 371 | i945_late_initialization(s3resume); |
Stefan Reinauer | 36a2268 | 2008-10-29 04:52:57 +0000 | [diff] [blame] | 372 | } |