blob: 082f2d63d98675c546ec2e3d30156c63fa6f502d [file] [log] [blame]
Aaron Durbin76c37002012-10-30 09:03:43 -05001##
2## This file is part of the coreboot project.
3##
4## Copyright (C) 2010 Google Inc.
5##
6## This program is free software; you can redistribute it and/or modify
7## it under the terms of the GNU General Public License as published by
8## the Free Software Foundation; version 2 of the License.
9##
10## This program is distributed in the hope that it will be useful,
11## but WITHOUT ANY WARRANTY; without even the implied warranty of
12## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13## GNU General Public License for more details.
14##
Aaron Durbin76c37002012-10-30 09:03:43 -050015
16config NORTHBRIDGE_INTEL_HASWELL
17 bool
Aaron Durbin76c37002012-10-30 09:03:43 -050018 select CPU_INTEL_HASWELL
Arthur Heymansf300f362018-01-27 13:39:12 +010019 select CACHE_MRC_SETTINGS
Furquan Shaikh77f48cd2013-08-19 10:16:50 -070020 select INTEL_DDI
Vladimir Serbinenkodd2bc3f2014-10-31 09:16:31 +010021 select INTEL_GMA_ACPI
Arthur Heymans410f2562017-01-25 15:27:52 +010022 select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
Arthur Heymans88af0f32018-06-03 12:37:54 +020023 select POSTCAR_STAGE
24 select POSTCAR_CONSOLE
Aaron Durbin76c37002012-10-30 09:03:43 -050025
26if NORTHBRIDGE_INTEL_HASWELL
27
Julius Werner1210b412017-03-27 19:26:32 -070028config VBOOT
Julius Werner9993b6f2019-03-28 18:01:26 -070029 select VBOOT_OPROM_MATTERS
Julius Werner1210b412017-03-27 19:26:32 -070030 select VBOOT_STARTS_IN_ROMSTAGE
31
Aaron Durbin6d04f0f2012-10-31 22:57:16 -050032config BOOTBLOCK_NORTHBRIDGE_INIT
33 string
34 default "northbridge/intel/haswell/bootblock.c"
35
Aaron Durbin76c37002012-10-30 09:03:43 -050036config VGA_BIOS_ID
37 string
38 default "8086,0166"
39
Elyes HAOUASef169d62018-09-14 10:28:52 +020040config MMCONF_BASE_ADDRESS
41 hex
42 default 0xf0000000
43
Aaron Durbin76c37002012-10-30 09:03:43 -050044config CACHE_MRC_SIZE_KB
45 int
46 default 512
47
Aaron Durbin76c37002012-10-30 09:03:43 -050048config DCACHE_RAM_BASE
49 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060050 default 0xff7c0000
Aaron Durbin76c37002012-10-30 09:03:43 -050051
52config DCACHE_RAM_SIZE
53 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060054 default 0x10000
55 help
56 The size of the cache-as-ram region required during bootblock
57 and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
58 must add up to a power of 2.
Aaron Durbin76c37002012-10-30 09:03:43 -050059
60config DCACHE_RAM_MRC_VAR_SIZE
61 hex
Aaron Durbin3d0071b2013-01-18 14:32:50 -060062 default 0x30000
63 help
64 The amount of cache-as-ram region required by the reference code.
65
Aaron Durbin76c37002012-10-30 09:03:43 -050066config HAVE_MRC
67 bool "Add a System Agent binary"
68 help
69 Select this option to add a System Agent binary to
70 the resulting coreboot image.
71
72 Note: Without this binary coreboot will not work
73
74config MRC_FILE
75 string "Intel System Agent path and filename"
76 depends on HAVE_MRC
77 default "mrc.bin"
78 help
79 The path and filename of the file to use as System Agent
80 binary.
81
Stefan Reinauerf1aabec2014-01-22 15:16:30 -080082config PRE_GRAPHICS_DELAY
Stefan Reinauer7034b9e2014-02-11 16:18:07 -080083 int "Graphics initialization delay in ms"
Stefan Reinauerf1aabec2014-01-22 15:16:30 -080084 default 0
85 help
86 On some systems, coreboot boots so fast that connected monitors
87 (mostly TVs) won't be able to wake up fast enough to talk to the
88 VBIOS. On those systems we need to wait for a bit before executing
89 the VBIOS.
90
Aaron Durbin76c37002012-10-30 09:03:43 -050091endif