Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 1 | config SOC_INTEL_TIGERLAKE |
| 2 | bool |
| 3 | help |
| 4 | Intel Tigerlake support |
| 5 | |
Aamir Bohra | a23e0c9 | 2020-03-25 15:31:12 +0530 | [diff] [blame] | 6 | if SOC_INTEL_TIGERLAKE |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
| 10 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Angel Pons | a32df26 | 2020-09-25 10:20:11 +0200 | [diff] [blame] | 11 | select ARCH_ALL_STAGES_X86_32 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 12 | select BOOT_DEVICE_SUPPORTS_WRITES |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 13 | select CACHE_MRC_SETTINGS |
Alex Levin | f3668fc | 2020-06-11 20:09:45 -0700 | [diff] [blame] | 14 | select CPU_INTEL_COMMON |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 15 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Michael Niewöhner | fe6070f | 2020-10-04 15:16:04 +0200 | [diff] [blame] | 16 | select CPU_SUPPORTS_PM_TIMER_EMULATION |
Duncan Laurie | 2e9315c | 2020-10-27 10:29:16 -0700 | [diff] [blame] | 17 | select DRIVERS_USB_ACPI |
Furquan Shaikh | ba75c4c | 2020-11-22 15:45:54 -0800 | [diff] [blame] | 18 | select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW |
Karthikeyan Ramasubramanian | 6abee84 | 2020-06-16 23:29:28 -0600 | [diff] [blame] | 19 | select FSP_COMPRESS_FSP_S_LZ4 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 20 | select FSP_M_XIP |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 21 | select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 22 | select GENERIC_GPIO_LIB |
| 23 | select HAVE_FSP_GOP |
Felix Singer | 3e3c456 | 2020-12-17 18:34:45 +0000 | [diff] [blame] | 24 | select HAVE_INTEL_FSP_REPO |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 25 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
| 26 | select HAVE_SMI_HANDLER |
| 27 | select IDT_IN_EVERY_STAGE |
Shreesh Chhabbi | 87c7ec7 | 2020-12-03 14:07:15 -0800 | [diff] [blame] | 28 | select INTEL_CAR_NEM_ENHANCED if !INTEL_CAR_NEM |
Shreesh Chhabbi | 860c684 | 2020-12-03 15:06:20 -0800 | [diff] [blame] | 29 | select CAR_HAS_SF_MASKS if INTEL_CAR_NEM_ENHANCED |
Shreesh Chhabbi | 42b1d3f | 2020-11-05 12:06:29 -0800 | [diff] [blame] | 30 | select COS_MAPPED_TO_MSB if INTEL_CAR_NEM_ENHANCED |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 31 | select INTEL_GMA_ACPI |
| 32 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
| 33 | select IOAPIC |
Aamir Bohra | 30cca6c | 2021-02-04 20:57:51 +0530 | [diff] [blame] | 34 | select MP_SERVICES_PPI_V1 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 35 | select MRC_SETTINGS_PROTECT |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 36 | select PARALLEL_MP_AP_WORK |
| 37 | select MICROCODE_BLOB_UNDISCLOSED |
Subrata Banik | b622d4b | 2020-05-26 18:33:22 +0530 | [diff] [blame] | 38 | select PLATFORM_USES_FSP2_2 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 39 | select REG_SCRIPT |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 40 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
Subrata Banik | 0359d9d | 2020-09-28 18:43:47 +0530 | [diff] [blame] | 41 | select PMC_LOW_POWER_MODE_PROGRAM |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 42 | select SOC_INTEL_COMMON |
| 43 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
| 44 | select SOC_INTEL_COMMON_BLOCK |
| 45 | select SOC_INTEL_COMMON_BLOCK_ACPI |
Angel Pons | 98f672a | 2021-02-19 19:42:10 +0100 | [diff] [blame] | 46 | select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO |
Michael Niewöhner | 8a6c34e | 2021-01-01 21:26:42 +0100 | [diff] [blame] | 47 | select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT |
Subrata Banik | 21974ab | 2020-10-31 21:40:43 +0530 | [diff] [blame] | 48 | select SOC_INTEL_COMMON_BLOCK_CAR |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 49 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Furquan Shaikh | 23e8813 | 2020-10-08 23:44:20 -0700 | [diff] [blame] | 50 | select SOC_INTEL_COMMON_BLOCK_CNVI |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 51 | select SOC_INTEL_COMMON_BLOCK_CPU |
| 52 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
Angel Pons | a4cd911 | 2021-02-19 19:23:38 +0100 | [diff] [blame] | 53 | select SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE |
Tim Wawrzynczak | c5316ec | 2020-05-29 15:20:56 -0600 | [diff] [blame] | 54 | select SOC_INTEL_COMMON_BLOCK_DTT |
Nick Vaccaro | ef8258a | 2019-12-09 22:11:33 -0800 | [diff] [blame] | 55 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
Duncan Laurie | 7d97136 | 2020-11-05 10:09:58 -0800 | [diff] [blame] | 56 | select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 57 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
| 58 | select SOC_INTEL_COMMON_BLOCK_HDA |
Tim Wawrzynczak | ed042a9 | 2021-02-04 17:07:14 -0700 | [diff] [blame] | 59 | select SOC_INTEL_COMMON_BLOCK_IRQ |
Furquan Shaikh | f06d046 | 2020-12-31 21:15:34 -0800 | [diff] [blame] | 60 | select SOC_INTEL_COMMON_BLOCK_MEMINIT |
Duncan Laurie | e997d85 | 2020-10-10 00:18:08 +0000 | [diff] [blame] | 61 | select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 62 | select SOC_INTEL_COMMON_BLOCK_SA |
| 63 | select SOC_INTEL_COMMON_BLOCK_SMM |
| 64 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
Duncan Laurie | 6f58b99 | 2020-08-28 19:44:42 +0000 | [diff] [blame] | 65 | select SOC_INTEL_COMMON_BLOCK_USB4 |
| 66 | select SOC_INTEL_COMMON_BLOCK_USB4_PCIE |
Duncan Laurie | 2e9315c | 2020-10-27 10:29:16 -0700 | [diff] [blame] | 67 | select SOC_INTEL_COMMON_BLOCK_USB4_XHCI |
Karthikeyan Ramasubramanian | fa9e8f9 | 2020-11-04 22:22:46 -0700 | [diff] [blame] | 68 | select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 69 | select SOC_INTEL_COMMON_FSP_RESET |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 70 | select SOC_INTEL_COMMON_PCH_BASE |
| 71 | select SOC_INTEL_COMMON_RESET |
Sumeet R Pawnikar | d213246 | 2020-05-15 15:55:37 +0530 | [diff] [blame] | 72 | select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 73 | select SSE2 |
| 74 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 75 | select TSC_MONOTONIC_TIMER |
| 76 | select UDELAY_TSC |
| 77 | select UDK_2017_BINDING |
| 78 | select DISPLAY_FSP_VERSION_INFO |
| 79 | select HECI_DISABLE_USING_SMM |
| 80 | |
Andy Pont | d2f52ff | 2021-06-08 10:30:35 +0100 | [diff] [blame] | 81 | config MAX_CPUS |
| 82 | int |
| 83 | default 8 |
| 84 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 85 | config DCACHE_RAM_BASE |
| 86 | default 0xfef00000 |
| 87 | |
| 88 | config DCACHE_RAM_SIZE |
Maulik V Vaghela | e9b1e0f | 2019-12-16 16:39:53 +0530 | [diff] [blame] | 89 | default 0x80000 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 90 | help |
| 91 | The size of the cache-as-ram region required during bootblock |
| 92 | and/or romstage. |
| 93 | |
| 94 | config DCACHE_BSP_STACK_SIZE |
| 95 | hex |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 96 | default 0x40400 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 97 | help |
| 98 | The amount of anticipated stack usage in CAR by bootblock and |
| 99 | other stages. In the case of FSP_USES_CB_STACK default value will be |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 100 | sum of FSP-M stack requirement(256KiB) and CB romstage stack requirement |
| 101 | (~1KiB). |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 102 | |
| 103 | config FSP_TEMP_RAM_SIZE |
| 104 | hex |
Maulik V Vaghela | e9b1e0f | 2019-12-16 16:39:53 +0530 | [diff] [blame] | 105 | default 0x20000 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 106 | help |
| 107 | The amount of anticipated heap usage in CAR by FSP. |
| 108 | Refer to Platform FSP integration guide document to know |
| 109 | the exact FSP requirement for Heap setup. |
| 110 | |
Duncan Laurie | a5bb31f | 2020-07-29 16:31:18 -0700 | [diff] [blame] | 111 | config CHIPSET_DEVICETREE |
| 112 | string |
| 113 | default "soc/intel/tigerlake/chipset.cb" |
| 114 | |
Furquan Shaikh | ba75c4c | 2020-11-22 15:45:54 -0800 | [diff] [blame] | 115 | config EXT_BIOS_WIN_BASE |
| 116 | default 0xf8000000 |
| 117 | |
| 118 | config EXT_BIOS_WIN_SIZE |
| 119 | default 0x2000000 |
| 120 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 121 | config IFD_CHIPSET |
| 122 | string |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 123 | default "tgl" |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 124 | |
| 125 | config IED_REGION_SIZE |
| 126 | hex |
| 127 | default 0x400000 |
| 128 | |
| 129 | config HEAP_SIZE |
| 130 | hex |
Duncan Laurie | aab226c | 2020-06-08 17:36:21 -0700 | [diff] [blame] | 131 | default 0x10000 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 132 | |
| 133 | config MAX_ROOT_PORTS |
| 134 | int |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 135 | default 12 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 136 | |
Rizwan Qureshi | a979460 | 2021-04-08 20:31:47 +0530 | [diff] [blame] | 137 | config MAX_PCIE_CLOCK_SRC |
Ravi Sarawadi | 2fd4972 | 2019-12-16 23:41:36 -0800 | [diff] [blame] | 138 | int |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 139 | default 7 |
Ravi Sarawadi | 2fd4972 | 2019-12-16 23:41:36 -0800 | [diff] [blame] | 140 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 141 | config SMM_TSEG_SIZE |
| 142 | hex |
| 143 | default 0x800000 |
| 144 | |
| 145 | config SMM_RESERVED_SIZE |
| 146 | hex |
| 147 | default 0x200000 |
| 148 | |
| 149 | config PCR_BASE_ADDRESS |
| 150 | hex |
| 151 | default 0xfd000000 |
| 152 | help |
| 153 | This option allows you to select MMIO Base Address of sideband bus. |
| 154 | |
| 155 | config MMCONF_BASE_ADDRESS |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 156 | default 0xc0000000 |
| 157 | |
| 158 | config CPU_BCLK_MHZ |
| 159 | int |
| 160 | default 100 |
| 161 | |
| 162 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
| 163 | int |
| 164 | default 120 |
| 165 | |
Michael Niewöhner | dadcbfb | 2020-10-04 14:48:05 +0200 | [diff] [blame] | 166 | config CPU_XTAL_HZ |
| 167 | default 38400000 |
| 168 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 169 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 170 | int |
| 171 | default 133 |
| 172 | |
| 173 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 174 | int |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 175 | default 4 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 176 | |
| 177 | config SOC_INTEL_I2C_DEV_MAX |
| 178 | int |
| 179 | default 6 |
| 180 | |
| 181 | config SOC_INTEL_UART_DEV_MAX |
| 182 | int |
| 183 | default 3 |
| 184 | |
| 185 | config CONSOLE_UART_BASE_ADDRESS |
| 186 | hex |
Bora Guvendik | c3c3e45 | 2020-11-13 21:35:19 -0800 | [diff] [blame] | 187 | default 0xfe03e000 |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 188 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 189 | |
| 190 | # Clock divider parameters for 115200 baud rate |
Ravi Sarawadi | 3838701 | 2019-12-19 15:04:58 -0800 | [diff] [blame] | 191 | # Baudrate = (UART source clcok * M) /(N *16) |
| 192 | # TGL UART source clock: 120MHz |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 193 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 194 | hex |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 195 | default 0x25a |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 196 | |
| 197 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 198 | hex |
Aamir Bohra | 555c9b6 | 2020-03-23 10:13:10 +0530 | [diff] [blame] | 199 | default 0x7fff |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 200 | |
Jes Klinke | e046b71 | 2020-08-19 14:01:30 -0700 | [diff] [blame] | 201 | # Tiger Lake SoC requires at least 100us interrupt pulses in order to guarantee detection |
| 202 | # in all low power states. Cr50 TPM, if used, needs to be told to generate longer pulses. |
| 203 | config TPM_CR50 |
| 204 | select CR50_USE_LONG_INTERRUPT_PULSES |
| 205 | |
Srinidhi N Kaushik | 74c16d0 | 2020-11-04 11:29:33 -0800 | [diff] [blame] | 206 | config VBT_DATA_SIZE_KB |
| 207 | int |
| 208 | default 9 |
| 209 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 210 | config VBOOT |
| 211 | select VBOOT_SEPARATE_VERSTAGE |
| 212 | select VBOOT_MUST_REQUEST_DISPLAY |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 213 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 214 | select VBOOT_VBNV_CMOS |
| 215 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 216 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 217 | config CBFS_SIZE |
| 218 | hex |
| 219 | default 0x200000 |
| 220 | |
Felix Singer | 3e3c456 | 2020-12-17 18:34:45 +0000 | [diff] [blame] | 221 | config FSP_TYPE_IOT |
| 222 | bool |
| 223 | default n |
| 224 | help |
| 225 | This option allows to select FSP IOT type from 3rdparty/fsp repo |
| 226 | |
| 227 | config FSP_TYPE_CLIENT |
| 228 | bool |
| 229 | default !FSP_TYPE_IOT |
| 230 | help |
| 231 | This option allows to select FSP CLIENT type from 3rdparty/fsp repo |
| 232 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 233 | config FSP_HEADER_PATH |
Felix Singer | 3e3c456 | 2020-12-17 18:34:45 +0000 | [diff] [blame] | 234 | default "3rdparty/fsp/TigerLakeFspBinPkg/TGL_IOT/Include/" if FSP_TYPE_IOT |
| 235 | default "3rdparty/fsp/TigerLakeFspBinPkg/Client/Include/" if FSP_TYPE_CLIENT |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 236 | |
| 237 | config FSP_FD_PATH |
Felix Singer | 3e3c456 | 2020-12-17 18:34:45 +0000 | [diff] [blame] | 238 | default "3rdparty/fsp/TigerLakeFspBinPkg/TGL_IOT/Fsp.fd" if FSP_TYPE_IOT |
| 239 | default "3rdparty/fsp/TigerLakeFspBinPkg/Client/Fsp.fd" if FSP_TYPE_CLIENT |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 240 | |
Subrata Banik | 56626cf | 2020-02-27 19:39:22 +0530 | [diff] [blame] | 241 | config SOC_INTEL_TIGERLAKE_DEBUG_CONSENT |
| 242 | int "Debug Consent for TGL" |
| 243 | # USB DBC is more common for developers so make this default to 3 if |
| 244 | # SOC_INTEL_DEBUG_CONSENT=y |
| 245 | default 3 if SOC_INTEL_DEBUG_CONSENT |
| 246 | default 0 |
| 247 | help |
| 248 | This is to control debug interface on SOC. |
| 249 | Setting non-zero value will allow to use DBC or DCI to debug SOC. |
| 250 | PlatformDebugConsent in FspmUpd.h has the details. |
| 251 | |
| 252 | Desired platform debug type are |
| 253 | 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), |
| 254 | 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), |
| 255 | 6:Enable (2-wire DCI OOB), 7:Manual |
Subrata Banik | ebf1daa | 2020-05-19 12:32:41 +0530 | [diff] [blame] | 256 | |
| 257 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 258 | hex |
Anil Kumar | 033038f | 2020-09-08 16:18:45 -0700 | [diff] [blame] | 259 | default 0x2000 |
Brandon Breitenstein | 99b38a9 | 2019-12-19 23:12:58 -0800 | [diff] [blame] | 260 | |
Furquan Shaikh | f06d046 | 2020-12-31 21:15:34 -0800 | [diff] [blame] | 261 | config DATA_BUS_WIDTH |
| 262 | int |
| 263 | default 128 |
| 264 | |
| 265 | config DIMMS_PER_CHANNEL |
| 266 | int |
| 267 | default 2 |
| 268 | |
| 269 | config MRC_CHANNEL_WIDTH |
| 270 | int |
| 271 | default 16 |
| 272 | |
Francois Toguo | 15cbc3b | 2021-01-26 10:27:49 -0800 | [diff] [blame] | 273 | config SOC_INTEL_CRASHLOG |
| 274 | def_bool n |
| 275 | select SOC_INTEL_COMMON_BLOCK_CRASHLOG |
| 276 | select ACPI_BERT |
| 277 | help |
| 278 | Enables CrashLog. |
| 279 | |
Subrata Banik | 91e89c5 | 2019-11-01 18:30:01 +0530 | [diff] [blame] | 280 | endif |