Angel Pons | f5627e8 | 2020-04-05 15:46:52 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 2 | |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 3 | #include <device/device.h> |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 4 | #include <device/pci.h> |
| 5 | #include <fsp/api.h> |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 6 | #include <fsp/util.h> |
Subrata Banik | 98376b8 | 2018-05-22 16:18:16 +0530 | [diff] [blame] | 7 | #include <intelblocks/acpi.h> |
Kyösti Mälkki | 32d47eb | 2019-09-28 00:00:30 +0300 | [diff] [blame] | 8 | #include <intelblocks/cfg.h> |
Michael Niewöhner | 8913b78 | 2020-12-11 22:13:44 +0100 | [diff] [blame] | 9 | #include <intelblocks/gpio.h> |
Tim Wawrzynczak | f9bb1b4 | 2021-06-25 13:02:16 -0600 | [diff] [blame] | 10 | #include <intelblocks/irq.h> |
Subrata Banik | 819b143 | 2018-09-28 19:56:54 +0530 | [diff] [blame] | 11 | #include <intelblocks/itss.h> |
Nico Huber | 9ea70c0 | 2019-10-12 15:16:33 +0200 | [diff] [blame] | 12 | #include <intelblocks/pcie_rp.h> |
Arthur Heymans | 08769c6 | 2022-05-09 14:33:15 +0200 | [diff] [blame] | 13 | #include <intelblocks/systemagent.h> |
Duncan Laurie | 2410cd9 | 2018-03-26 02:25:07 -0700 | [diff] [blame] | 14 | #include <intelblocks/xdci.h> |
Abhay kumar | fcf8820 | 2017-09-20 15:17:42 -0700 | [diff] [blame] | 15 | #include <soc/intel/common/vbt.h> |
Pratik Prajapati | 9027e1b | 2017-08-23 17:37:43 -0700 | [diff] [blame] | 16 | #include <soc/pci_devs.h> |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 17 | #include <soc/ramstage.h> |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 18 | |
Elyes HAOUAS | c338507 | 2019-03-21 15:38:06 +0100 | [diff] [blame] | 19 | #include "chip.h" |
| 20 | |
Nico Huber | 9ea70c0 | 2019-10-12 15:16:33 +0200 | [diff] [blame] | 21 | static const struct pcie_rp_group pch_lp_rp_groups[] = { |
MAULIK V VAGHELA | d9c5b14 | 2022-02-14 22:04:03 +0530 | [diff] [blame] | 22 | { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, |
| 23 | { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 }, |
Nico Huber | 9ea70c0 | 2019-10-12 15:16:33 +0200 | [diff] [blame] | 24 | { 0 } |
| 25 | }; |
| 26 | |
| 27 | static const struct pcie_rp_group pch_h_rp_groups[] = { |
MAULIK V VAGHELA | d9c5b14 | 2022-02-14 22:04:03 +0530 | [diff] [blame] | 28 | { .slot = PCH_DEV_SLOT_PCIE, .count = 8, .lcap_port_base = 1 }, |
| 29 | { .slot = PCH_DEV_SLOT_PCIE_1, .count = 8, .lcap_port_base = 1 }, |
| 30 | { .slot = PCH_DEV_SLOT_PCIE_2, .count = 8, .lcap_port_base = 1 }, |
Nico Huber | 9ea70c0 | 2019-10-12 15:16:33 +0200 | [diff] [blame] | 31 | { 0 } |
| 32 | }; |
| 33 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 34 | #if CONFIG(HAVE_ACPI_TABLES) |
Subrata Banik | 98376b8 | 2018-05-22 16:18:16 +0530 | [diff] [blame] | 35 | const char *soc_acpi_name(const struct device *dev) |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 36 | { |
| 37 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 38 | return "PCI0"; |
| 39 | |
Duncan Laurie | 1e64d23 | 2018-12-01 17:00:23 -0800 | [diff] [blame] | 40 | if (dev->path.type == DEVICE_PATH_USB) { |
| 41 | switch (dev->path.usb.port_type) { |
| 42 | case 0: |
| 43 | /* Root Hub */ |
| 44 | return "RHUB"; |
| 45 | case 2: |
| 46 | /* USB2 ports */ |
| 47 | switch (dev->path.usb.port_id) { |
| 48 | case 0: return "HS01"; |
| 49 | case 1: return "HS02"; |
| 50 | case 2: return "HS03"; |
| 51 | case 3: return "HS04"; |
| 52 | case 4: return "HS05"; |
| 53 | case 5: return "HS06"; |
| 54 | case 6: return "HS07"; |
| 55 | case 7: return "HS08"; |
| 56 | case 8: return "HS09"; |
| 57 | case 9: return "HS10"; |
| 58 | case 10: return "HS11"; |
| 59 | case 11: return "HS12"; |
| 60 | } |
| 61 | break; |
| 62 | case 3: |
| 63 | /* USB3 ports */ |
| 64 | switch (dev->path.usb.port_id) { |
| 65 | case 0: return "SS01"; |
| 66 | case 1: return "SS02"; |
| 67 | case 2: return "SS03"; |
| 68 | case 3: return "SS04"; |
| 69 | case 4: return "SS05"; |
| 70 | case 5: return "SS06"; |
| 71 | } |
| 72 | break; |
| 73 | } |
| 74 | return NULL; |
| 75 | } |
| 76 | |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 77 | if (dev->path.type != DEVICE_PATH_PCI) |
| 78 | return NULL; |
| 79 | |
| 80 | switch (dev->path.pci.devfn) { |
| 81 | case SA_DEVFN_ROOT: return "MCHC"; |
| 82 | case SA_DEVFN_IGD: return "GFX0"; |
| 83 | case PCH_DEVFN_ISH: return "ISHB"; |
| 84 | case PCH_DEVFN_XHCI: return "XHCI"; |
| 85 | case PCH_DEVFN_USBOTG: return "XDCI"; |
| 86 | case PCH_DEVFN_THERMAL: return "THRM"; |
| 87 | case PCH_DEVFN_I2C0: return "I2C0"; |
| 88 | case PCH_DEVFN_I2C1: return "I2C1"; |
| 89 | case PCH_DEVFN_I2C2: return "I2C2"; |
| 90 | case PCH_DEVFN_I2C3: return "I2C3"; |
| 91 | case PCH_DEVFN_CSE: return "CSE1"; |
| 92 | case PCH_DEVFN_CSE_2: return "CSE2"; |
| 93 | case PCH_DEVFN_CSE_IDER: return "CSED"; |
| 94 | case PCH_DEVFN_CSE_KT: return "CSKT"; |
| 95 | case PCH_DEVFN_CSE_3: return "CSE3"; |
| 96 | case PCH_DEVFN_SATA: return "SATA"; |
| 97 | case PCH_DEVFN_UART2: return "UAR2"; |
| 98 | case PCH_DEVFN_I2C4: return "I2C4"; |
| 99 | case PCH_DEVFN_I2C5: return "I2C5"; |
| 100 | case PCH_DEVFN_PCIE1: return "RP01"; |
| 101 | case PCH_DEVFN_PCIE2: return "RP02"; |
| 102 | case PCH_DEVFN_PCIE3: return "RP03"; |
| 103 | case PCH_DEVFN_PCIE4: return "RP04"; |
| 104 | case PCH_DEVFN_PCIE5: return "RP05"; |
| 105 | case PCH_DEVFN_PCIE6: return "RP06"; |
| 106 | case PCH_DEVFN_PCIE7: return "RP07"; |
| 107 | case PCH_DEVFN_PCIE8: return "RP08"; |
| 108 | case PCH_DEVFN_PCIE9: return "RP09"; |
| 109 | case PCH_DEVFN_PCIE10: return "RP10"; |
| 110 | case PCH_DEVFN_PCIE11: return "RP11"; |
| 111 | case PCH_DEVFN_PCIE12: return "RP12"; |
Lijian Zhao | 580bc41 | 2017-10-04 13:43:47 -0700 | [diff] [blame] | 112 | case PCH_DEVFN_PCIE13: return "RP13"; |
| 113 | case PCH_DEVFN_PCIE14: return "RP14"; |
| 114 | case PCH_DEVFN_PCIE15: return "RP15"; |
| 115 | case PCH_DEVFN_PCIE16: return "RP16"; |
praveen hodagatta pranesh | e26c4a4 | 2018-09-20 03:49:45 +0800 | [diff] [blame] | 116 | case PCH_DEVFN_PCIE17: return "RP17"; |
| 117 | case PCH_DEVFN_PCIE18: return "RP18"; |
| 118 | case PCH_DEVFN_PCIE19: return "RP19"; |
| 119 | case PCH_DEVFN_PCIE20: return "RP20"; |
| 120 | case PCH_DEVFN_PCIE21: return "RP21"; |
| 121 | case PCH_DEVFN_PCIE22: return "RP22"; |
| 122 | case PCH_DEVFN_PCIE23: return "RP23"; |
| 123 | case PCH_DEVFN_PCIE24: return "RP24"; |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 124 | case PCH_DEVFN_UART0: return "UAR0"; |
| 125 | case PCH_DEVFN_UART1: return "UAR1"; |
| 126 | case PCH_DEVFN_GSPI0: return "SPI0"; |
| 127 | case PCH_DEVFN_GSPI1: return "SPI1"; |
| 128 | case PCH_DEVFN_GSPI2: return "SPI2"; |
| 129 | case PCH_DEVFN_EMMC: return "EMMC"; |
| 130 | case PCH_DEVFN_SDCARD: return "SDXC"; |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 131 | case PCH_DEVFN_P2SB: return "P2SB"; |
| 132 | case PCH_DEVFN_PMC: return "PMC_"; |
| 133 | case PCH_DEVFN_HDA: return "HDAS"; |
| 134 | case PCH_DEVFN_SMBUS: return "SBUS"; |
| 135 | case PCH_DEVFN_SPI: return "FSPI"; |
| 136 | case PCH_DEVFN_GBE: return "IGBE"; |
| 137 | case PCH_DEVFN_TRACEHUB:return "THUB"; |
| 138 | } |
| 139 | |
| 140 | return NULL; |
| 141 | } |
| 142 | #endif |
| 143 | |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 144 | void soc_init_pre_device(void *chip_info) |
| 145 | { |
| 146 | /* Perform silicon specific init. */ |
Kyösti Mälkki | cc93c6e | 2021-01-09 22:53:52 +0200 | [diff] [blame] | 147 | fsp_silicon_init(); |
Subrata Banik | a8733e3 | 2018-01-23 16:40:56 +0530 | [diff] [blame] | 148 | |
| 149 | /* Display FIRMWARE_VERSION_INFO_HOB */ |
| 150 | fsp_display_fvi_version_hob(); |
Subrata Banik | 819b143 | 2018-09-28 19:56:54 +0530 | [diff] [blame] | 151 | |
Subrata Banik | 73b1bd7 | 2019-11-28 13:56:24 +0530 | [diff] [blame] | 152 | soc_gpio_pm_configuration(); |
Nico Huber | 9ea70c0 | 2019-10-12 15:16:33 +0200 | [diff] [blame] | 153 | |
| 154 | /* swap enabled PCI ports in device tree if needed */ |
| 155 | if (CONFIG(SOC_INTEL_CANNONLAKE_PCH_H)) |
| 156 | pcie_rp_update_devicetree(pch_h_rp_groups); |
| 157 | else |
| 158 | pcie_rp_update_devicetree(pch_lp_rp_groups); |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 159 | } |
| 160 | |
Tim Wawrzynczak | f9bb1b4 | 2021-06-25 13:02:16 -0600 | [diff] [blame] | 161 | static void cpu_fill_ssdt(const struct device *dev) |
| 162 | { |
| 163 | generate_cpu_entries(dev); |
| 164 | |
| 165 | if (!generate_pin_irq_map()) |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 166 | printk(BIOS_ERR, "Failed to generate ACPI _PRT table!\n"); |
Tim Wawrzynczak | f9bb1b4 | 2021-06-25 13:02:16 -0600 | [diff] [blame] | 167 | } |
| 168 | |
| 169 | static void cpu_set_north_irqs(struct device *dev) |
| 170 | { |
| 171 | irq_program_non_pch(); |
| 172 | } |
| 173 | |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 174 | static struct device_operations pci_domain_ops = { |
| 175 | .read_resources = &pci_domain_read_resources, |
| 176 | .set_resources = &pci_domain_set_resources, |
| 177 | .scan_bus = &pci_domain_scan_bus, |
Tim Wawrzynczak | e281606 | 2021-09-28 14:28:50 -0600 | [diff] [blame] | 178 | #if CONFIG(HAVE_ACPI_TABLES) |
Lijian Zhao | 2b074d9 | 2017-08-17 14:25:24 -0700 | [diff] [blame] | 179 | .acpi_name = &soc_acpi_name, |
Arthur Heymans | 08769c6 | 2022-05-09 14:33:15 +0200 | [diff] [blame] | 180 | .acpi_fill_ssdt = ssdt_set_above_4g_pci, |
Tim Wawrzynczak | e281606 | 2021-09-28 14:28:50 -0600 | [diff] [blame] | 181 | #endif |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 182 | }; |
| 183 | |
| 184 | static struct device_operations cpu_bus_ops = { |
Nico Huber | 2f8ba69 | 2020-04-05 14:05:24 +0200 | [diff] [blame] | 185 | .read_resources = noop_read_resources, |
| 186 | .set_resources = noop_set_resources, |
Tim Wawrzynczak | f9bb1b4 | 2021-06-25 13:02:16 -0600 | [diff] [blame] | 187 | .enable_resources = cpu_set_north_irqs, |
Tim Wawrzynczak | e281606 | 2021-09-28 14:28:50 -0600 | [diff] [blame] | 188 | #if CONFIG(HAVE_ACPI_TABLES) |
Tim Wawrzynczak | f9bb1b4 | 2021-06-25 13:02:16 -0600 | [diff] [blame] | 189 | .acpi_fill_ssdt = cpu_fill_ssdt, |
Tim Wawrzynczak | e281606 | 2021-09-28 14:28:50 -0600 | [diff] [blame] | 190 | #endif |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 191 | }; |
| 192 | |
Elyes HAOUAS | 3c8b5d0 | 2018-05-27 16:57:24 +0200 | [diff] [blame] | 193 | static void soc_enable(struct device *dev) |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 194 | { |
| 195 | /* Set the operations if it is a special bus type */ |
| 196 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 197 | dev->ops = &pci_domain_ops; |
| 198 | else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
| 199 | dev->ops = &cpu_bus_ops; |
Michael Niewöhner | 8913b78 | 2020-12-11 22:13:44 +0100 | [diff] [blame] | 200 | else if (dev->path.type == DEVICE_PATH_GPIO) |
| 201 | block_gpio_enable(dev); |
Tim Wawrzynczak | bd5b4aa | 2021-07-01 08:41:48 -0600 | [diff] [blame] | 202 | else if (dev->path.type == DEVICE_PATH_PCI && |
| 203 | dev->path.pci.devfn == PCH_DEVFN_PMC) |
| 204 | dev->ops = &pmc_ops; |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 205 | } |
| 206 | |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 207 | struct chip_operations soc_intel_cannonlake_ops = { |
| 208 | CHIP_NAME("Intel Cannonlake") |
Pratik Prajapati | 201fa8f | 2017-08-16 11:42:40 -0700 | [diff] [blame] | 209 | .enable_dev = &soc_enable, |
Lijian Zhao | 2f764f7 | 2017-07-14 11:09:10 -0700 | [diff] [blame] | 210 | .init = &soc_init_pre_device, |
| 211 | }; |