soc/intel/cannonlake: Configure GPIO PM configuration in bootblock
This patch performs below operations:
1. Rename soc_fill_gpio_pm_configuration to soc_gpio_pm_configuration
2. Move soc_gpio_pm_configuration() to gpio_common.c
3. Calling from bootblock and after FSP-S to ensure GPIO PM configuration
is updated with devicetree.cb value even with platform reset.
BUG=b:144002424
TEST=coreboot configures all MISCCFG.bit 0-5 local clock gating based on devicetree.cb
Change-Id: I54061d556d62462d9012bc47bb9f3604a3e5a250
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 0ce2f1a..2bb1c92 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -23,6 +23,7 @@
#include <intelblocks/xdci.h>
#include <romstage_handoff.h>
#include <soc/intel/common/vbt.h>
+#include <soc/gpio.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
@@ -166,22 +167,6 @@
gpio_configure_pads(cfg, num_pads);
}
-/* SoC rotine to fill GPIO PM mask and value for GPIO_MISCCFG register */
-static void soc_fill_gpio_pm_configuration(void)
-{
- uint8_t value[TOTAL_GPIO_COMM];
- const config_t *config = config_of_soc();
-
- if (config->gpio_override_pm)
- memcpy(value, config->gpio_pm, sizeof(uint8_t) *
- TOTAL_GPIO_COMM);
- else
- memset(value, MISCCFG_ENABLE_GPIO_PM_CONFIG, sizeof(uint8_t) *
- TOTAL_GPIO_COMM);
-
- gpio_pm_configure(value, TOTAL_GPIO_COMM);
-}
-
void soc_init_pre_device(void *chip_info)
{
/* Perform silicon specific init. */
@@ -193,7 +178,7 @@
/* TODO(furquan): Get rid of this workaround once FSP is fixed. */
cnl_configure_pads(NULL, 0);
- soc_fill_gpio_pm_configuration();
+ soc_gpio_pm_configuration();
}
static void pci_domain_set_resources(struct device *dev)