soc/intel/cannonlake: Ensure FSP don't override ITSS IPCx registers
This patch save and restore ITSS IPCx register before and after
FSP-S call.
Change-Id: Iea9356b4404d2fa49ea62ef7bc2c72f125054ff3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28792
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
diff --git a/src/soc/intel/cannonlake/chip.c b/src/soc/intel/cannonlake/chip.c
index 6a3324b..0529c5c 100644
--- a/src/soc/intel/cannonlake/chip.c
+++ b/src/soc/intel/cannonlake/chip.c
@@ -21,9 +21,11 @@
#include <fsp/util.h>
#include <intelblocks/acpi.h>
#include <intelblocks/chip.h>
+#include <intelblocks/itss.h>
#include <intelblocks/xdci.h>
#include <romstage_handoff.h>
#include <soc/intel/common/vbt.h>
+#include <soc/itss.h>
#include <soc/pci_devs.h>
#include <soc/ramstage.h>
#include <string.h>
@@ -96,11 +98,18 @@
void soc_init_pre_device(void *chip_info)
{
+ /* Snapshot the current GPIO IRQ polarities. FSP is setting a
+ * default policy that doesn't honor boards' requirements. */
+ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
+
/* Perform silicon specific init. */
fsp_silicon_init(romstage_handoff_is_resume());
/* Display FIRMWARE_VERSION_INFO_HOB */
fsp_display_fvi_version_hob();
+
+ /* Restore GPIO IRQ polarities back to previous settings. */
+ itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
}
static void pci_domain_set_resources(struct device *dev)