commit	f9bb1b46a27511e7f2b49d9ab9c1f56335afc1b3	[log] [tgz]
author	Tim Wawrzynczak <twawrzynczak@chromium.org>	Fri Jun 25 13:02:16 2021 -0600
committer	Tim Wawrzynczak <twawrzynczak@chromium.org>	Tue Jun 29 21:53:49 2021 +0000
tree	9859af6dd3599f2ce7ff73b18eaa4c1ef51c135e
parent	664c58ab95ff201bc986f96507de021d772bef74 [diff]

soc/intel/cannonlake: Use new IRQ module

Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch
allows cannonlake boards to dynamically assign PCI IRQs. This means not
relying on FSP defaults, which eliminates the problem of PCI IRQs
interfering with GPIO IRQs routed to the same IRQ, when both have
selected IO-APIC routing.

Also prodrive/hermes (intel/cannonlake) was the only user of
uart_acpi_write_irq(), therefore use the allocated IRQ instead of the
fixed IRQ number in that function to preserve behavior.

BUG=b:130217151
TEST=on dratini, grep 'IO-APIC' /proc/interrupts (compressed to fit)
   0:     11     0    0 0 IO-APIC    2-edge      timer
   1:      0   661    0 0 IO-APIC    1-edge      i8042
   8:      0     0    0 0 IO-APIC    8-edge      rtc0
   9:      0   874    0 0 IO-APIC    9-fasteoi   acpi
  14:      0     0    1 0 IO-APIC   14-fasteoi   INT34BB:00
  17:      0 10633    0 0 IO-APIC   17-fasteoi   mmc1
  19:      0     0    0 0 IO-APIC   19-fasteoi   mmc0
  22:      0     0    0 0 IO-APIC   22-fasteoi   i801_smbus
  26: 153738     0    0 0 IO-APIC   26-fasteoi   idma64.0, i2c_designwar
  27:      0     8    0 0 IO-APIC   27-fasteoi   idma64.1, i2c_designwar
  30:      0     0  227 0 IO-APIC   30-fasteoi   i2c_designware.2
  33:      0     0    0 0 IO-APIC   33-fasteoi   idma64.3
  35:  43107     0    0 0 IO-APIC   35-fasteoi   idma64.4, pxa2xx-spi.4
  36:      0     0 2039 0 IO-APIC   36-fasteoi   idma64.5, pxa2xx-spi.5
  45:      0     0 9451 0 IO-APIC   45-edge      ELAN0000:00
  85:      0     0    0 0 IO-APIC   85-fasteoi   chromeos-ec
  93:      0  7741    0 0 IO-APIC   93-edge      cr50_spi
abbreviated _PRT dump:
If (PICM)
  Package () {0x0001FFFF, 0x00, 0x00, 0x10},
  Package () {0x0001FFFF, 0x01, 0x00, 0x11},
  Package () {0x0001FFFF, 0x02, 0x00, 0x12},
  Package () {0x0002FFFF, 0x00, 0x00, 0x13},
  Package () {0x0004FFFF, 0x00, 0x00, 0x14},
  Package () {0x0005FFFF, 0x00, 0x00, 0x15},
  Package () {0x0008FFFF, 0x00, 0x00, 0x16},
  Package () {0x0012FFFF, 0x01, 0x00, 0x17},
  Package () {0x0012FFFF, 0x02, 0x00, 0x10},
  Package () {0x0012FFFF, 0x00, 0x00, 0x18},
  Package () {0x0013FFFF, 0x00, 0x00, 0x19},
  Package () {0x0014FFFF, 0x00, 0x00, 0x11}
  Package () {0x0014FFFF, 0x01, 0x00, 0x12},
  Package () {0x0014FFFF, 0x02, 0x00, 0x13},
  Package () {0x0014FFFF, 0x03, 0x00, 0x14},
  Package () {0x0015FFFF, 0x00, 0x00, 0x1A},
  Package () {0x0015FFFF, 0x01, 0x00, 0x1B},
  Package () {0x0015FFFF, 0x02, 0x00, 0x1C},
  Package () {0x0015FFFF, 0x03, 0x00, 0x1D},
  Package () {0x0016FFFF, 0x00, 0x00, 0x15},
  Package () {0x0016FFFF, 0x01, 0x00, 0x16},
  Package () {0x0016FFFF, 0x02, 0x00, 0x17},
  Package () {0x0016FFFF, 0x03, 0x00, 0x10},
  Package () {0x0017FFFF, 0x00, 0x00, 0x11},
  Package () {0x0019FFFF, 0x00, 0x00, 0x1E},
  Package () {0x0019FFFF, 0x01, 0x00, 0x1F},
  Package () {0x0019FFFF, 0x02, 0x00, 0x20},
  Package () {0x001AFFFF, 0x00, 0x00, 0x12},
  Package () {0x001CFFFF, 0x00, 0x00, 0x10},
  Package () {0x001CFFFF, 0x01, 0x00, 0x11},
  Package () {0x001CFFFF, 0x02, 0x00, 0x12},
  Package () {0x001CFFFF, 0x03, 0x00, 0x13},
  Package () {0x001DFFFF, 0x00, 0x00, 0x10},
  Package () {0x001DFFFF, 0x01, 0x00, 0x11},
  Package () {0x001DFFFF, 0x02, 0x00, 0x12},
  Package () {0x001DFFFF, 0x03, 0x00, 0x13},
  Package () {0x001EFFFF, 0x00, 0x00, 0x21},
  Package () {0x001EFFFF, 0x01, 0x00, 0x22},
  Package () {0x001EFFFF, 0x02, 0x00, 0x23},
  Package () {0x001EFFFF, 0x03, 0x00, 0x24},
  Package () {0x001FFFFF, 0x01, 0x00, 0x15},
  Package () {0x001FFFFF, 0x02, 0x00, 0x16},
  Package () {0x001FFFFF, 0x03, 0x00, 0x17},
  Package () {0x001FFFFF, 0x00, 0x00, 0x14},
Else
  Package () {0x0001FFFF, 0x00, 0x00, 0x0B},
  Package () {0x0001FFFF, 0x01, 0x00, 0x0A},
  Package () {0x0001FFFF, 0x02, 0x00, 0x0B},
  Package () {0x0002FFFF, 0x00, 0x00, 0x0B},
  Package () {0x0004FFFF, 0x00, 0x00, 0x0B},
  Package () {0x0005FFFF, 0x00, 0x00, 0x0B},
  Package () {0x0008FFFF, 0x00, 0x00, 0x0B},
  Package () {0x0012FFFF, 0x01, 0x00, 0x0B},
  Package () {0x0012FFFF, 0x02, 0x00, 0x0B},
  Package () {0x0014FFFF, 0x00, 0x00, 0x0A},
  Package () {0x0014FFFF, 0x01, 0x00, 0x0B},
  Package () {0x0014FFFF, 0x02, 0x00, 0x0B},
  Package () {0x0014FFFF, 0x03, 0x00, 0x0B},
  Package () {0x0016FFFF, 0x00, 0x00, 0x0B},
  Package () {0x0016FFFF, 0x01, 0x00, 0x0B},
  Package () {0x0016FFFF, 0x02, 0x00, 0x0B},
  Package () {0x0016FFFF, 0x03, 0x00, 0x0B},
  Package () {0x0017FFFF, 0x00, 0x00, 0x0A},
  Package () {0x001AFFFF, 0x00, 0x00, 0x0B},
  Package () {0x001CFFFF, 0x00, 0x00, 0x0B},
  Package () {0x001CFFFF, 0x01, 0x00, 0x0A},
  Package () {0x001CFFFF, 0x02, 0x00, 0x0B},
  Package () {0x001CFFFF, 0x03, 0x00, 0x0B},
  Package () {0x001DFFFF, 0x00, 0x00, 0x0B},
  Package () {0x001DFFFF, 0x01, 0x00, 0x0A},
  Package () {0x001DFFFF, 0x02, 0x00, 0x0B},
  Package () {0x001DFFFF, 0x03, 0x00, 0x0B},
  Package () {0x001FFFFF, 0x01, 0x00, 0x0B},
  Package () {0x001FFFFF, 0x02, 0x00, 0x0B},
  Package () {0x001FFFFF, 0x03, 0x00, 0x0B},
  Package () {0x001FFFFF, 0x00, 0x00, 0x0B},

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I914ac65470635f351d6311dc9b65e8e4d8d8ecfc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55968
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

8 files changed

tree: 9859af6dd3599f2ce7ff73b18eaa4c1ef51c135e

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

https://www.coreboot.org/Supported_Motherboards

Build Requirements

make
gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
iasl (for targets with ACPI support)
pkg-config
libssl-dev (openssl)

Optional:

doxygen (for generating/viewing documentation)
gdb (for better debugging facilities on some targets)
ncurses (for make menuconfig and make nconfig)
flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.