Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 2 | |
Arthur Heymans | fdf6d12 | 2022-05-17 13:07:30 +0200 | [diff] [blame] | 3 | #include <arch/null_breakpoint.h> |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 4 | #include <arch/symbols.h> |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 5 | #include <assert.h> |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 6 | #include <cbfs.h> |
Aaron Durbin | 2792868 | 2016-07-15 22:32:28 -0500 | [diff] [blame] | 7 | #include <cbmem.h> |
Patrick Rudolph | f677d17 | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 8 | #include <cf9_reset.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 9 | #include <console/console.h> |
Furquan Shaikh | 5aea588 | 2016-07-30 18:10:05 -0700 | [diff] [blame] | 10 | #include <elog.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 11 | #include <fsp/api.h> |
| 12 | #include <fsp/util.h> |
| 13 | #include <memrange.h> |
Arthur Heymans | fdf6d12 | 2022-05-17 13:07:30 +0200 | [diff] [blame] | 14 | #include <mode_switch.h> |
Aaron Durbin | decd062 | 2017-12-15 12:26:40 -0700 | [diff] [blame] | 15 | #include <mrc_cache.h> |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 16 | #include <program_loading.h> |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 17 | #include <romstage_handoff.h> |
Arthur Heymans | fdf6d12 | 2022-05-17 13:07:30 +0200 | [diff] [blame] | 18 | #include <security/tpm/tspi.h> |
| 19 | #include <security/vboot/antirollback.h> |
| 20 | #include <security/vboot/vboot_common.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 21 | #include <string.h> |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 22 | #include <symbols.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 23 | #include <timestamp.h> |
Elyes HAOUAS | bd1683d | 2019-05-15 21:05:37 +0200 | [diff] [blame] | 24 | #include <types.h> |
Arthur Heymans | fdf6d12 | 2022-05-17 13:07:30 +0200 | [diff] [blame] | 25 | #include <vb2_api.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 26 | |
Subrata Banik | 30a0114 | 2023-03-22 00:35:42 +0530 | [diff] [blame] | 27 | #if CONFIG(SOC_INTEL_COMMON_BASECODE_RAMTOP) |
| 28 | #include <intelbasecode/ramtop.h> |
Subrata Banik | dbfbfaf | 2023-02-28 07:01:26 +0000 | [diff] [blame] | 29 | #endif |
| 30 | |
Kyösti Mälkki | c987150 | 2019-09-03 07:03:39 +0300 | [diff] [blame] | 31 | static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t)); |
| 32 | |
Subrata Banik | f31ab7a | 2023-06-19 12:07:29 +0000 | [diff] [blame] | 33 | /* |
| 34 | * Helper function to store the MRC cache version into CBMEM |
| 35 | * |
| 36 | * ramstage uses either the MRC version or FSP-M version (depending on the config) |
| 37 | * when updating the MRC cache |
| 38 | */ |
| 39 | static void do_cbmem_version_entry(uint32_t cbmem_id, uint32_t version) |
| 40 | { |
| 41 | uint32_t *cbmem_version_entry = cbmem_add(cbmem_id, sizeof(version)); |
| 42 | if (!cbmem_version_entry) { |
| 43 | printk(BIOS_ERR, "Failed to add %s version to cbmem.\n", |
| 44 | CONFIG(MRC_CACHE_USING_MRC_VERSION) ? "MRC" : "FSP-M"); |
| 45 | return; |
| 46 | } |
| 47 | *cbmem_version_entry = version; |
| 48 | } |
| 49 | |
Subrata Banik | 79274e01 | 2023-06-19 11:32:19 +0000 | [diff] [blame] | 50 | static void do_fsp_post_memory_init(bool s3wake, uint32_t version) |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 51 | { |
| 52 | struct range_entry fsp_mem; |
Subrata Banik | f31ab7a | 2023-06-19 12:07:29 +0000 | [diff] [blame] | 53 | uint32_t cbmem_id = CONFIG(MRC_CACHE_USING_MRC_VERSION) ? CBMEM_ID_MRC_VERSION : |
| 54 | CBMEM_ID_FSPM_VERSION; |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 55 | |
Michael Niewöhner | bc1dbb3 | 2019-10-24 22:58:25 +0200 | [diff] [blame] | 56 | fsp_find_reserved_memory(&fsp_mem); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 57 | |
| 58 | /* initialize cbmem by adding FSP reserved memory first thing */ |
| 59 | if (!s3wake) { |
| 60 | cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, |
| 61 | range_entry_size(&fsp_mem)); |
| 62 | } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, |
| 63 | range_entry_size(&fsp_mem))) { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 64 | if (CONFIG(HAVE_ACPI_RESUME)) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 65 | printk(BIOS_ERR, "Failed to recover CBMEM in S3 resume.\n"); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 66 | /* Failed S3 resume, reset to come up cleanly */ |
Patrick Rudolph | f677d17 | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 67 | /* FIXME: A "system" reset is likely enough: */ |
| 68 | full_reset(); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 69 | } |
| 70 | } |
| 71 | |
| 72 | /* make sure FSP memory is reserved in cbmem */ |
| 73 | if (range_entry_base(&fsp_mem) != |
| 74 | (uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY)) |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 75 | die("Failed to accommodate FSP reserved memory request!\n"); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 76 | |
Subrata Banik | e48f24d | 2023-08-31 14:38:38 +0000 | [diff] [blame] | 77 | if (CONFIG(CACHE_MRC_SETTINGS) && !s3wake) { |
Subrata Banik | f31ab7a | 2023-06-19 12:07:29 +0000 | [diff] [blame] | 78 | do_cbmem_version_entry(cbmem_id, version); |
Subrata Banik | e48f24d | 2023-08-31 14:38:38 +0000 | [diff] [blame] | 79 | if (!CONFIG(FSP_NVS_DATA_POST_SILICON_INIT)) |
| 80 | save_memory_training_data(); |
| 81 | } |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 82 | |
Martin Roth | 74f1877 | 2023-09-03 21:38:29 -0600 | [diff] [blame] | 83 | /* Create romstage handoff information */ |
Aaron Durbin | 77e1399 | 2016-11-29 17:43:04 -0600 | [diff] [blame] | 84 | romstage_handoff_init(s3wake); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 85 | } |
| 86 | |
Subrata Banik | 79274e01 | 2023-06-19 11:32:19 +0000 | [diff] [blame] | 87 | static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t version) |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 88 | { |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 89 | void *data; |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 90 | size_t mrc_size; |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 91 | |
Patrick Rudolph | 31218a4 | 2020-11-30 15:50:06 +0100 | [diff] [blame] | 92 | arch_upd->NvsBufferPtr = 0; |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 93 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 94 | if (!CONFIG(CACHE_MRC_SETTINGS)) |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 95 | return; |
| 96 | |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 97 | /* Assume boot device is memory mapped. */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 98 | assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 99 | |
Subrata Banik | 79274e01 | 2023-06-19 11:32:19 +0000 | [diff] [blame] | 100 | data = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, version, |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 101 | &mrc_size); |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 102 | if (data == NULL) |
| 103 | return; |
| 104 | |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 105 | /* MRC cache found */ |
Patrick Rudolph | 31218a4 | 2020-11-30 15:50:06 +0100 | [diff] [blame] | 106 | arch_upd->NvsBufferPtr = (uintptr_t)data; |
Aamir Bohra | 69cd62c | 2018-01-08 11:01:34 +0530 | [diff] [blame] | 107 | |
Subrata Banik | 0593708 | 2023-03-06 08:18:24 +0000 | [diff] [blame] | 108 | printk(BIOS_SPEW, "MRC cache found, size %zu bytes\n", mrc_size); |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 109 | } |
| 110 | |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 111 | static enum cb_err check_region_overlap(const struct memranges *ranges, |
| 112 | const char *description, |
| 113 | uintptr_t begin, uintptr_t end) |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 114 | { |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 115 | const struct range_entry *r; |
| 116 | |
| 117 | memranges_each_entry(r, ranges) { |
| 118 | if (end <= range_entry_base(r)) |
| 119 | continue; |
| 120 | if (begin >= range_entry_end(r)) |
| 121 | continue; |
Lee Leahy | b20d4ba | 2016-07-31 16:49:28 -0700 | [diff] [blame] | 122 | printk(BIOS_CRIT, "'%s' overlaps currently running program: " |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 123 | "[%p, %p)\n", description, (void *)begin, (void *)end); |
| 124 | return CB_ERR; |
| 125 | } |
| 126 | |
| 127 | return CB_SUCCESS; |
| 128 | } |
Kyösti Mälkki | c987150 | 2019-09-03 07:03:39 +0300 | [diff] [blame] | 129 | |
Aamir Bohra | 6d569e0c | 2018-08-27 13:36:15 +0530 | [diff] [blame] | 130 | static enum cb_err setup_fsp_stack_frame(FSPM_ARCH_UPD *arch_upd, |
| 131 | const struct memranges *memmap) |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 132 | { |
| 133 | uintptr_t stack_begin; |
| 134 | uintptr_t stack_end; |
| 135 | |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 136 | /* |
Aamir Bohra | 6d569e0c | 2018-08-27 13:36:15 +0530 | [diff] [blame] | 137 | * FSPM_UPD passed here is populated with default values |
| 138 | * provided by the blob itself. We let FSPM use top of CAR |
| 139 | * region of the size it requests. |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 140 | */ |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 141 | stack_end = (uintptr_t)_car_region_end; |
| 142 | stack_begin = stack_end - arch_upd->StackSize; |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 143 | if (check_region_overlap(memmap, "FSPM stack", stack_begin, |
| 144 | stack_end) != CB_SUCCESS) |
| 145 | return CB_ERR; |
| 146 | |
Patrick Rudolph | 31218a4 | 2020-11-30 15:50:06 +0100 | [diff] [blame] | 147 | arch_upd->StackBase = stack_begin; |
Aamir Bohra | 6d569e0c | 2018-08-27 13:36:15 +0530 | [diff] [blame] | 148 | return CB_SUCCESS; |
| 149 | } |
| 150 | |
| 151 | static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd, |
Subrata Banik | 79274e01 | 2023-06-19 11:32:19 +0000 | [diff] [blame] | 152 | bool s3wake, uint32_t version, |
Aamir Bohra | 6d569e0c | 2018-08-27 13:36:15 +0530 | [diff] [blame] | 153 | const struct memranges *memmap) |
| 154 | { |
Kyösti Mälkki | c987150 | 2019-09-03 07:03:39 +0300 | [diff] [blame] | 155 | /* |
| 156 | * FSP 2.1 version would use same stack as coreboot instead of |
| 157 | * setting up separate stack frame. FSP 2.1 would not relocate stack |
| 158 | * top and does not reinitialize stack pointer. The parameters passed |
| 159 | * as StackBase and StackSize are actually for temporary RAM and HOBs |
| 160 | * and are not related to FSP stack at all. |
Felix Held | 414d7e4 | 2020-08-11 22:54:06 +0200 | [diff] [blame] | 161 | * Non-CAR FSP 2.0 platforms pass a DRAM location for the FSP stack. |
Kyösti Mälkki | c987150 | 2019-09-03 07:03:39 +0300 | [diff] [blame] | 162 | */ |
Marx Wang | 708a11c | 2023-11-10 17:00:23 +0800 | [diff] [blame^] | 163 | static const char * const fsp_bootmode_strings[] = { |
| 164 | [FSP_BOOT_WITH_FULL_CONFIGURATION] = "boot with full config", |
| 165 | [FSP_BOOT_WITH_MINIMAL_CONFIGURATION] = "boot with minimal config", |
| 166 | [FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES] = "boot assuming no config change", |
| 167 | [FSP_BOOT_ON_S4_RESUME] = "boot on s4 resume", |
| 168 | [FSP_BOOT_ON_S3_RESUME] = "boot on s3 resume", |
| 169 | [FSP_BOOT_ON_FLASH_UPDATE] = "boot on flash update", |
| 170 | [FSP_BOOT_IN_RECOVERY_MODE] = "boot in recovery mode", |
| 171 | }; |
| 172 | |
Felix Held | 414d7e4 | 2020-08-11 22:54:06 +0200 | [diff] [blame] | 173 | if (CONFIG(FSP_USES_CB_STACK) || !ENV_CACHE_AS_RAM) { |
Patrick Rudolph | 31218a4 | 2020-11-30 15:50:06 +0100 | [diff] [blame] | 174 | arch_upd->StackBase = (uintptr_t)temp_ram; |
Kyösti Mälkki | c987150 | 2019-09-03 07:03:39 +0300 | [diff] [blame] | 175 | arch_upd->StackSize = sizeof(temp_ram); |
| 176 | } else if (setup_fsp_stack_frame(arch_upd, memmap)) { |
Aamir Bohra | 6d569e0c | 2018-08-27 13:36:15 +0530 | [diff] [blame] | 177 | return CB_ERR; |
Kyösti Mälkki | c987150 | 2019-09-03 07:03:39 +0300 | [diff] [blame] | 178 | } |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 179 | |
Subrata Banik | 79274e01 | 2023-06-19 11:32:19 +0000 | [diff] [blame] | 180 | fsp_fill_mrc_cache(arch_upd, version); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 181 | |
Aamir Bohra | 69cd62c | 2018-01-08 11:01:34 +0530 | [diff] [blame] | 182 | /* Configure bootmode */ |
| 183 | if (s3wake) { |
Aamir Bohra | 69cd62c | 2018-01-08 11:01:34 +0530 | [diff] [blame] | 184 | arch_upd->BootMode = FSP_BOOT_ON_S3_RESUME; |
| 185 | } else { |
| 186 | if (arch_upd->NvsBufferPtr) |
| 187 | arch_upd->BootMode = |
| 188 | FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; |
| 189 | else |
| 190 | arch_upd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; |
| 191 | } |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 192 | |
Marx Wang | 708a11c | 2023-11-10 17:00:23 +0800 | [diff] [blame^] | 193 | if (arch_upd->BootMode < ARRAY_SIZE(fsp_bootmode_strings) && |
| 194 | fsp_bootmode_strings[arch_upd->BootMode] != NULL) |
| 195 | printk(BIOS_SPEW, "bootmode is set to: %d (%s)\n", arch_upd->BootMode, |
| 196 | fsp_bootmode_strings[arch_upd->BootMode]); |
| 197 | else |
| 198 | printk(BIOS_SPEW, "bootmode is set to: %d (unknown mode)\n", arch_upd->BootMode); |
Aamir Bohra | 276c06a | 2017-12-26 17:54:45 +0530 | [diff] [blame] | 199 | |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 200 | return CB_SUCCESS; |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 201 | } |
| 202 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 203 | __weak |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 204 | uint8_t fsp_memory_mainboard_version(void) |
| 205 | { |
| 206 | return 0; |
| 207 | } |
| 208 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 209 | __weak |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 210 | uint8_t fsp_memory_soc_version(void) |
| 211 | { |
| 212 | return 0; |
| 213 | } |
| 214 | |
| 215 | /* |
| 216 | * Allow SoC and/or mainboard to bump the revision of the FSP setting |
| 217 | * number. The FSP spec uses the low 8 bits as the build number. Take over |
| 218 | * bits 3:0 for the SoC setting and bits 7:4 for the mainboard. That way |
| 219 | * a tweak in the settings will bump the version used to track the cached |
| 220 | * setting which triggers retraining when the FSP version hasn't changed, but |
| 221 | * the SoC or mainboard settings have. |
| 222 | */ |
| 223 | static uint32_t fsp_memory_settings_version(const struct fsp_header *hdr) |
| 224 | { |
| 225 | /* Use the full FSP version by default. */ |
Julian Schroeder | 8a576f6 | 2021-11-02 16:32:28 -0500 | [diff] [blame] | 226 | uint32_t ver = hdr->image_revision; |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 227 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 228 | if (!CONFIG(FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS)) |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 229 | return ver; |
| 230 | |
| 231 | ver &= ~0xff; |
| 232 | ver |= (0xf & fsp_memory_mainboard_version()) << 4; |
| 233 | ver |= (0xf & fsp_memory_soc_version()) << 0; |
| 234 | |
| 235 | return ver; |
| 236 | } |
| 237 | |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 238 | struct fspm_context { |
| 239 | struct fsp_header header; |
| 240 | struct memranges memmap; |
| 241 | }; |
| 242 | |
Subrata Banik | 79274e01 | 2023-06-19 11:32:19 +0000 | [diff] [blame] | 243 | /* |
| 244 | * Helper function to read MRC version |
| 245 | * |
| 246 | * There are multiple ways to read the MRC version using |
| 247 | * Intel FSP. Currently the only supported method to get the |
| 248 | * MRC version is by reading the FSP_PRODUCDER_DATA_TABLES |
| 249 | * from the FSP-M binary (by parsing the FSP header). |
| 250 | */ |
| 251 | static uint32_t fsp_mrc_version(void) |
| 252 | { |
| 253 | uint32_t ver = 0; |
| 254 | #if CONFIG(MRC_CACHE_USING_MRC_VERSION) |
| 255 | size_t fspm_blob_size; |
Jonathon Hall | eb834d9 | 2023-09-27 12:50:59 -0400 | [diff] [blame] | 256 | const char *fspm_cbfs = soc_select_fsp_m_cbfs(); |
| 257 | void *fspm_blob_file = cbfs_map(fspm_cbfs, &fspm_blob_size); |
Subrata Banik | 79274e01 | 2023-06-19 11:32:19 +0000 | [diff] [blame] | 258 | if (!fspm_blob_file) |
| 259 | return 0; |
| 260 | |
| 261 | FSP_PRODUCER_DATA_TABLES *ft = fspm_blob_file + FSP_HDR_OFFSET; |
| 262 | FSP_PRODUCER_DATA_TYPE2 *table2 = &ft->FspProduceDataType2; |
| 263 | size_t mrc_version_size = sizeof(table2->MrcVersion); |
| 264 | for (size_t i = 0; i < mrc_version_size; i++) { |
| 265 | ver |= (table2->MrcVersion[i] << ((mrc_version_size - 1) - i) * 8); |
| 266 | } |
| 267 | cbfs_unmap(fspm_blob_file); |
| 268 | #endif |
| 269 | return ver; |
| 270 | } |
| 271 | |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 272 | static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake) |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 273 | { |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 274 | uint32_t status; |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 275 | fsp_memory_init_fn fsp_raminit; |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 276 | FSPM_UPD fspm_upd, *upd; |
| 277 | FSPM_ARCH_UPD *arch_upd; |
Subrata Banik | 79274e01 | 2023-06-19 11:32:19 +0000 | [diff] [blame] | 278 | uint32_t version; |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 279 | const struct fsp_header *hdr = &context->header; |
| 280 | const struct memranges *memmap = &context->memmap; |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 281 | |
lilacious | 40cb3fe | 2023-06-21 23:24:14 +0200 | [diff] [blame] | 282 | post_code(POSTCODE_MEM_PREINIT_PREP_START); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 283 | |
Subrata Banik | 79274e01 | 2023-06-19 11:32:19 +0000 | [diff] [blame] | 284 | if (CONFIG(MRC_CACHE_USING_MRC_VERSION)) |
| 285 | version = fsp_mrc_version(); |
| 286 | else |
| 287 | version = fsp_memory_settings_version(hdr); |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 288 | |
Patrick Rudolph | 31218a4 | 2020-11-30 15:50:06 +0100 | [diff] [blame] | 289 | upd = (FSPM_UPD *)(uintptr_t)(hdr->cfg_region_offset + hdr->image_base); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 290 | |
Felix Held | a095595 | 2021-02-02 21:30:25 +0100 | [diff] [blame] | 291 | /* |
| 292 | * Verify UPD region size. We don't have malloc before ramstage, so we |
| 293 | * use a static buffer for the FSP-M UPDs which is sizeof(FSPM_UPD) |
| 294 | * bytes long, since that is the value known at compile time. If |
| 295 | * hdr->cfg_region_size is bigger than that, not all UPD defaults will |
| 296 | * be copied, so it'll contain random data at the end, so we just call |
| 297 | * die() in that case. If hdr->cfg_region_size is smaller than that, |
| 298 | * there's a mismatch between the FSP and the header, but since it will |
| 299 | * copy the full UPD defaults to the buffer, we try to continue and |
| 300 | * hope that there was no incompatible change in the UPDs. |
| 301 | */ |
| 302 | if (hdr->cfg_region_size > sizeof(FSPM_UPD)) |
| 303 | die("FSP-M UPD size is larger than FSPM_UPD struct size.\n"); |
| 304 | if (hdr->cfg_region_size < sizeof(FSPM_UPD)) |
| 305 | printk(BIOS_ERR, "FSP-M UPD size is smaller than FSPM_UPD struct size. " |
| 306 | "Check if the FSP binary matches the FSP headers.\n"); |
| 307 | |
Felix Held | 8899598 | 2021-01-28 22:43:52 +0100 | [diff] [blame] | 308 | fsp_verify_upd_header_signature(upd->FspUpdHeader.Signature, FSPM_UPD_SIGNATURE); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 309 | |
| 310 | /* Copy the default values from the UPD area */ |
| 311 | memcpy(&fspm_upd, upd, sizeof(fspm_upd)); |
| 312 | |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 313 | arch_upd = &fspm_upd.FspmArchUpd; |
| 314 | |
Aaron Durbin | 2792868 | 2016-07-15 22:32:28 -0500 | [diff] [blame] | 315 | /* Reserve enough memory under TOLUD to save CBMEM header */ |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 316 | arch_upd->BootLoaderTolumSize = cbmem_overhead_size(); |
Aaron Durbin | 2792868 | 2016-07-15 22:32:28 -0500 | [diff] [blame] | 317 | |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 318 | /* Fill common settings on behalf of chipset. */ |
Subrata Banik | 79274e01 | 2023-06-19 11:32:19 +0000 | [diff] [blame] | 319 | if (fsp_fill_common_arch_params(arch_upd, s3wake, version, |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 320 | memmap) != CB_SUCCESS) |
lilacious | 40cb3fe | 2023-06-21 23:24:14 +0200 | [diff] [blame] | 321 | die_with_post_code(POSTCODE_INVALID_VENDOR_BINARY, |
Keith Short | bb41aba | 2019-05-16 14:07:43 -0600 | [diff] [blame] | 322 | "FSPM_ARCH_UPD not found!\n"); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 323 | |
Subrata Banik | 30a0114 | 2023-03-22 00:35:42 +0530 | [diff] [blame] | 324 | /* Early caching of RAMTOP region if valid mrc cache data is found */ |
| 325 | #if (CONFIG(SOC_INTEL_COMMON_BASECODE_RAMTOP)) |
Subrata Banik | dbfbfaf | 2023-02-28 07:01:26 +0000 | [diff] [blame] | 326 | if (arch_upd->NvsBufferPtr) |
Subrata Banik | 30a0114 | 2023-03-22 00:35:42 +0530 | [diff] [blame] | 327 | early_ramtop_enable_cache_range(); |
Subrata Banik | dbfbfaf | 2023-02-28 07:01:26 +0000 | [diff] [blame] | 328 | #endif |
| 329 | |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 330 | /* Give SoC and mainboard a chance to update the UPD */ |
Subrata Banik | 79274e01 | 2023-06-19 11:32:19 +0000 | [diff] [blame] | 331 | platform_fsp_memory_init_params_cb(&fspm_upd, version); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 332 | |
Furquan Shaikh | dbce8ba | 2020-06-05 19:17:00 -0700 | [diff] [blame] | 333 | /* |
| 334 | * For S3 resume case, if valid mrc cache data is not found or |
| 335 | * RECOVERY_MRC_CACHE hash verification fails, the S3 data |
| 336 | * pointer would be null and S3 resume fails with fsp-m |
| 337 | * returning error. Invoking a reset here saves time. |
| 338 | */ |
| 339 | if (s3wake && !arch_upd->NvsBufferPtr) |
| 340 | /* FIXME: A "system" reset is likely enough: */ |
| 341 | full_reset(); |
| 342 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 343 | if (CONFIG(MMA)) |
Pratik Prajapati | ffc934d | 2016-11-18 14:36:34 -0800 | [diff] [blame] | 344 | setup_mma(&fspm_upd.FspmConfig); |
| 345 | |
lilacious | 40cb3fe | 2023-06-21 23:24:14 +0200 | [diff] [blame] | 346 | post_code(POSTCODE_MEM_PREINIT_PREP_END); |
Furquan Shaikh | 585210a | 2018-10-16 11:54:37 -0700 | [diff] [blame] | 347 | |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 348 | /* Call FspMemoryInit */ |
Julian Schroeder | 8a576f6 | 2021-11-02 16:32:28 -0500 | [diff] [blame] | 349 | fsp_raminit = (void *)(uintptr_t)(hdr->image_base + hdr->fsp_memory_init_entry_offset); |
Lee Leahy | ac3b0a6 | 2016-07-27 07:40:25 -0700 | [diff] [blame] | 350 | fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 351 | |
Arthur Heymans | fdf6d12 | 2022-05-17 13:07:30 +0200 | [diff] [blame] | 352 | /* FSP disables the interrupt handler so remove debug exceptions temporarily */ |
| 353 | null_breakpoint_disable(); |
lilacious | 40cb3fe | 2023-06-21 23:24:14 +0200 | [diff] [blame] | 354 | post_code(POSTCODE_FSP_MEMORY_INIT); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 355 | timestamp_add_now(TS_FSP_MEMORY_INIT_START); |
Patrick Rudolph | 31218a4 | 2020-11-30 15:50:06 +0100 | [diff] [blame] | 356 | if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32)) |
Patrick Rudolph | 40beb36 | 2020-12-01 10:08:38 +0100 | [diff] [blame] | 357 | status = protected_mode_call_2arg(fsp_raminit, |
| 358 | (uintptr_t)&fspm_upd, |
| 359 | (uintptr_t)fsp_get_hob_list_ptr()); |
| 360 | else |
| 361 | status = fsp_raminit(&fspm_upd, fsp_get_hob_list_ptr()); |
Arthur Heymans | fdf6d12 | 2022-05-17 13:07:30 +0200 | [diff] [blame] | 362 | null_breakpoint_init(); |
Patrick Rudolph | 40beb36 | 2020-12-01 10:08:38 +0100 | [diff] [blame] | 363 | |
lilacious | 40cb3fe | 2023-06-21 23:24:14 +0200 | [diff] [blame] | 364 | post_code(POSTCODE_FSP_MEMORY_EXIT); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 365 | timestamp_add_now(TS_FSP_MEMORY_INIT_END); |
| 366 | |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 367 | /* Handle any errors returned by FspMemoryInit */ |
Aaron Durbin | f41f2aa | 2016-07-18 12:03:58 -0500 | [diff] [blame] | 368 | fsp_handle_reset(status); |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 369 | if (status != FSP_SUCCESS) { |
lilacious | 40cb3fe | 2023-06-21 23:24:14 +0200 | [diff] [blame] | 370 | die_with_post_code(POSTCODE_RAM_FAILURE, |
Angel Pons | 2b1f8d4 | 2022-01-01 17:20:00 +0100 | [diff] [blame] | 371 | "FspMemoryInit returned with error 0x%08x!\n", status); |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 372 | } |
Aaron Durbin | f41f2aa | 2016-07-18 12:03:58 -0500 | [diff] [blame] | 373 | |
Subrata Banik | 79274e01 | 2023-06-19 11:32:19 +0000 | [diff] [blame] | 374 | do_fsp_post_memory_init(s3wake, version); |
Matthew Garrett | 78b58a4 | 2018-07-28 16:53:16 -0700 | [diff] [blame] | 375 | |
| 376 | /* |
| 377 | * fsp_debug_after_memory_init() checks whether the end of the tolum |
| 378 | * region is the same as the top of cbmem, so must be called here |
| 379 | * after cbmem has been initialised in do_fsp_post_memory_init(). |
| 380 | */ |
| 381 | fsp_debug_after_memory_init(status); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 382 | } |
| 383 | |
Julius Werner | 8205ce6 | 2021-03-10 17:25:01 -0800 | [diff] [blame] | 384 | static void *fspm_allocator(void *arg, size_t size, const union cbfs_mdata *unused) |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 385 | { |
Julius Werner | 8205ce6 | 2021-03-10 17:25:01 -0800 | [diff] [blame] | 386 | const struct fsp_load_descriptor *fspld = arg; |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 387 | struct fspm_context *context = fspld->arg; |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 388 | struct memranges *memmap = &context->memmap; |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 389 | |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 390 | /* Non XIP FSP-M uses FSP-M address */ |
Julius Werner | 8205ce6 | 2021-03-10 17:25:01 -0800 | [diff] [blame] | 391 | uintptr_t fspm_begin = (uintptr_t)CONFIG_FSP_M_ADDR; |
| 392 | uintptr_t fspm_end = fspm_begin + size; |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 393 | |
| 394 | if (check_region_overlap(memmap, "FSPM", fspm_begin, fspm_end) != CB_SUCCESS) |
Julius Werner | 8205ce6 | 2021-03-10 17:25:01 -0800 | [diff] [blame] | 395 | return NULL; |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 396 | |
Julius Werner | 8205ce6 | 2021-03-10 17:25:01 -0800 | [diff] [blame] | 397 | return (void *)fspm_begin; |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 398 | } |
| 399 | |
Raul E Rangel | 1592846 | 2021-11-05 10:29:24 -0600 | [diff] [blame] | 400 | void preload_fspm(void) |
| 401 | { |
| 402 | if (!CONFIG(CBFS_PRELOAD)) |
| 403 | return; |
| 404 | |
Jonathon Hall | eb834d9 | 2023-09-27 12:50:59 -0400 | [diff] [blame] | 405 | const char *fspm_cbfs = soc_select_fsp_m_cbfs(); |
| 406 | printk(BIOS_DEBUG, "Preloading %s\n", fspm_cbfs); |
| 407 | cbfs_preload(fspm_cbfs); |
Raul E Rangel | 1592846 | 2021-11-05 10:29:24 -0600 | [diff] [blame] | 408 | } |
| 409 | |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 410 | void fsp_memory_init(bool s3wake) |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 411 | { |
Marshall Dawson | e3aa424 | 2019-10-16 21:53:21 -0600 | [diff] [blame] | 412 | struct range_entry prog_ranges[2]; |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 413 | struct fspm_context context; |
Jonathon Hall | eb834d9 | 2023-09-27 12:50:59 -0400 | [diff] [blame] | 414 | const char *fspm_cbfs = soc_select_fsp_m_cbfs(); |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 415 | struct fsp_load_descriptor fspld = { |
Jonathon Hall | eb834d9 | 2023-09-27 12:50:59 -0400 | [diff] [blame] | 416 | .fsp_prog = PROG_INIT(PROG_REFCODE, fspm_cbfs), |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 417 | .arg = &context, |
| 418 | }; |
| 419 | struct fsp_header *hdr = &context.header; |
| 420 | struct memranges *memmap = &context.memmap; |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 421 | |
Julius Werner | 8205ce6 | 2021-03-10 17:25:01 -0800 | [diff] [blame] | 422 | /* For FSP-M XIP we leave alloc NULL to get a direct mapping to flash. */ |
| 423 | if (!CONFIG(FSP_M_XIP)) |
| 424 | fspld.alloc = fspm_allocator; |
| 425 | |
Kyösti Mälkki | 7f50afb | 2019-09-11 17:12:26 +0300 | [diff] [blame] | 426 | elog_boot_notify(s3wake); |
Furquan Shaikh | 5aea588 | 2016-07-30 18:10:05 -0700 | [diff] [blame] | 427 | |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 428 | /* Build up memory map of romstage address space including CAR. */ |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 429 | memranges_init_empty(memmap, &prog_ranges[0], ARRAY_SIZE(prog_ranges)); |
Marshall Dawson | e3aa424 | 2019-10-16 21:53:21 -0600 | [diff] [blame] | 430 | if (ENV_CACHE_AS_RAM) |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 431 | memranges_insert(memmap, (uintptr_t)_car_region_start, |
Marshall Dawson | e3aa424 | 2019-10-16 21:53:21 -0600 | [diff] [blame] | 432 | _car_unallocated_start - _car_region_start, 0); |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 433 | memranges_insert(memmap, (uintptr_t)_program, REGION_SIZE(program), 0); |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 434 | |
Martin Roth | 146508d | 2021-04-30 16:45:08 -0600 | [diff] [blame] | 435 | timestamp_add_now(TS_FSP_MEMORY_INIT_LOAD); |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 436 | if (fsp_load_component(&fspld, hdr) != CB_SUCCESS) |
| 437 | die("FSPM not available or failed to load!\n"); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 438 | |
Julius Werner | 8205ce6 | 2021-03-10 17:25:01 -0800 | [diff] [blame] | 439 | if (CONFIG(FSP_M_XIP) && (uintptr_t)prog_start(&fspld.fsp_prog) != hdr->image_base) |
| 440 | die("FSPM XIP base does not match: %p vs %p\n", |
| 441 | (void *)(uintptr_t)hdr->image_base, prog_start(&fspld.fsp_prog)); |
| 442 | |
Jakub Czapiga | ad6157e | 2022-02-15 11:50:31 +0100 | [diff] [blame] | 443 | timestamp_add_now(TS_INITRAM_START); |
Kyösti Mälkki | 216db61 | 2019-09-11 09:57:14 +0300 | [diff] [blame] | 444 | |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 445 | do_fsp_memory_init(&context, s3wake); |
Kyösti Mälkki | 0889e93 | 2019-08-18 07:40:43 +0300 | [diff] [blame] | 446 | |
Jakub Czapiga | ad6157e | 2022-02-15 11:50:31 +0100 | [diff] [blame] | 447 | timestamp_add_now(TS_INITRAM_END); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 448 | } |