Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Lee Leahy | 47bd2d9 | 2016-07-24 18:12:16 -0700 | [diff] [blame] | 4 | * Copyright (C) 2015-2016 Intel Corp. |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 5 | * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) |
| 6 | * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | */ |
| 13 | |
| 14 | #include <arch/io.h> |
| 15 | #include <arch/cpu.h> |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 16 | #include <arch/symbols.h> |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 17 | #include <cbfs.h> |
Aaron Durbin | 2792868 | 2016-07-15 22:32:28 -0500 | [diff] [blame] | 18 | #include <cbmem.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 19 | #include <console/console.h> |
Furquan Shaikh | 5aea588 | 2016-07-30 18:10:05 -0700 | [diff] [blame^] | 20 | #include <elog.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 21 | #include <fsp/api.h> |
| 22 | #include <fsp/util.h> |
| 23 | #include <memrange.h> |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 24 | #include <program_loading.h> |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 25 | #include <reset.h> |
| 26 | #include <romstage_handoff.h> |
| 27 | #include <soc/intel/common/mrc_cache.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 28 | #include <string.h> |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 29 | #include <symbols.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 30 | #include <timestamp.h> |
Furquan Shaikh | 0325dc6 | 2016-07-25 13:02:36 -0700 | [diff] [blame] | 31 | #include <vboot/vboot_common.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 32 | |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 33 | static void save_memory_training_data(bool s3wake, uint32_t fsp_version) |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 34 | { |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 35 | size_t mrc_data_size; |
| 36 | const void *mrc_data; |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 37 | |
| 38 | if (!IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS) || s3wake) |
| 39 | return; |
| 40 | |
| 41 | mrc_data = fsp_find_nv_storage_data(&mrc_data_size); |
| 42 | if (!mrc_data) { |
| 43 | printk(BIOS_ERR, "Couldn't find memory training data HOB.\n"); |
| 44 | return; |
| 45 | } |
| 46 | |
| 47 | /* |
| 48 | * Save MRC Data to CBMEM. By always saving the data this forces |
| 49 | * a retrain after a trip through Chrome OS recovery path. The |
| 50 | * code which saves the data to flash doesn't write if the latest |
| 51 | * training data matches this one. |
| 52 | */ |
| 53 | if (mrc_cache_stash_data_with_version(mrc_data, mrc_data_size, |
| 54 | fsp_version) < 0) |
| 55 | printk(BIOS_ERR, "Failed to stash MRC data\n"); |
| 56 | } |
| 57 | |
Furquan Shaikh | af8ef2a | 2016-07-24 08:48:34 -0700 | [diff] [blame] | 58 | /* |
| 59 | * On every trip to recovery, newly generated MRC data is stored with this |
| 60 | * version since it is not expected to be a legit version. This ensures that on |
| 61 | * next normal boot, memory re-training occurs and new MRC data is stored. |
| 62 | */ |
| 63 | #define MRC_DEAD_VERSION (0xdeaddead) |
| 64 | |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 65 | static enum fsp_status do_fsp_post_memory_init(void *hob_list_ptr, bool s3wake, |
| 66 | uint32_t fsp_version) |
| 67 | { |
| 68 | struct range_entry fsp_mem; |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 69 | struct romstage_handoff *handoff; |
| 70 | |
| 71 | fsp_find_reserved_memory(&fsp_mem, hob_list_ptr); |
| 72 | |
| 73 | /* initialize cbmem by adding FSP reserved memory first thing */ |
| 74 | if (!s3wake) { |
| 75 | cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, |
| 76 | range_entry_size(&fsp_mem)); |
| 77 | } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, |
| 78 | range_entry_size(&fsp_mem))) { |
| 79 | if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { |
| 80 | printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); |
| 81 | /* Failed S3 resume, reset to come up cleanly */ |
| 82 | hard_reset(); |
| 83 | } |
| 84 | } |
| 85 | |
| 86 | /* make sure FSP memory is reserved in cbmem */ |
| 87 | if (range_entry_base(&fsp_mem) != |
| 88 | (uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY)) |
| 89 | die("Failed to accommodate FSP reserved memory request"); |
| 90 | |
| 91 | /* Now that CBMEM is up, save the list so ramstage can use it */ |
| 92 | fsp_save_hob_list(hob_list_ptr); |
| 93 | |
Furquan Shaikh | 0325dc6 | 2016-07-25 13:02:36 -0700 | [diff] [blame] | 94 | if (vboot_recovery_mode_enabled()) |
Furquan Shaikh | af8ef2a | 2016-07-24 08:48:34 -0700 | [diff] [blame] | 95 | fsp_version = MRC_DEAD_VERSION; |
| 96 | |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 97 | save_memory_training_data(s3wake, fsp_version); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 98 | |
| 99 | /* Create romstage handof information */ |
| 100 | handoff = romstage_handoff_find_or_add(); |
| 101 | if (handoff != NULL) |
| 102 | handoff->s3_resume = s3wake; |
| 103 | else |
| 104 | printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); |
| 105 | |
| 106 | return FSP_SUCCESS; |
| 107 | } |
| 108 | |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 109 | static void fsp_fill_mrc_cache(struct FSPM_ARCH_UPD *arch_upd, bool s3wake, |
| 110 | uint32_t fsp_version) |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 111 | { |
| 112 | const struct mrc_saved_data *mrc_cache; |
| 113 | |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 114 | arch_upd->NvsBufferPtr = NULL; |
| 115 | |
| 116 | if (!IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) |
| 117 | return; |
| 118 | |
Aaron Durbin | 98ea636 | 2016-07-18 11:31:53 -0500 | [diff] [blame] | 119 | /* Don't use saved training data when recovery mode is enabled. */ |
Furquan Shaikh | 0325dc6 | 2016-07-25 13:02:36 -0700 | [diff] [blame] | 120 | if (vboot_recovery_mode_enabled()) { |
Aaron Durbin | 98ea636 | 2016-07-18 11:31:53 -0500 | [diff] [blame] | 121 | printk(BIOS_DEBUG, "Recovery mode. Not using MRC cache.\n"); |
| 122 | return; |
| 123 | } |
| 124 | |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 125 | if (mrc_cache_get_current_with_version(&mrc_cache, fsp_version)) { |
| 126 | printk(BIOS_DEBUG, "MRC cache was not found\n"); |
| 127 | return; |
| 128 | } |
| 129 | |
| 130 | /* MRC cache found */ |
| 131 | arch_upd->NvsBufferPtr = (void *)mrc_cache->data; |
| 132 | arch_upd->BootMode = s3wake ? |
| 133 | FSP_BOOT_ON_S3_RESUME: |
| 134 | FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; |
| 135 | printk(BIOS_DEBUG, "MRC cache found, size %x bootmode:%d\n", |
| 136 | mrc_cache->size, arch_upd->BootMode); |
| 137 | } |
| 138 | |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 139 | static enum cb_err check_region_overlap(const struct memranges *ranges, |
| 140 | const char *description, |
| 141 | uintptr_t begin, uintptr_t end) |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 142 | { |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 143 | const struct range_entry *r; |
| 144 | |
| 145 | memranges_each_entry(r, ranges) { |
| 146 | if (end <= range_entry_base(r)) |
| 147 | continue; |
| 148 | if (begin >= range_entry_end(r)) |
| 149 | continue; |
| 150 | printk(BIOS_ERR, "'%s' overlaps currently running program: " |
| 151 | "[%p, %p)\n", description, (void *)begin, (void *)end); |
| 152 | return CB_ERR; |
| 153 | } |
| 154 | |
| 155 | return CB_SUCCESS; |
| 156 | } |
| 157 | |
| 158 | static enum cb_err fsp_fill_common_arch_params(struct FSPM_ARCH_UPD *arch_upd, |
| 159 | bool s3wake, uint32_t fsp_version, |
| 160 | const struct memranges *memmap) |
| 161 | { |
| 162 | uintptr_t stack_begin; |
| 163 | uintptr_t stack_end; |
| 164 | |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 165 | /* |
| 166 | * FSPM_UPD passed here is populated with default values provided by |
| 167 | * the blob itself. We let FSPM use top of CAR region of the size it |
| 168 | * requests. |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 169 | */ |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 170 | stack_end = (uintptr_t)_car_region_end; |
| 171 | stack_begin = stack_end - arch_upd->StackSize; |
| 172 | |
| 173 | if (check_region_overlap(memmap, "FSPM stack", stack_begin, |
| 174 | stack_end) != CB_SUCCESS) |
| 175 | return CB_ERR; |
| 176 | |
| 177 | arch_upd->StackBase = (void *)stack_begin; |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 178 | |
| 179 | arch_upd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; |
| 180 | |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 181 | fsp_fill_mrc_cache(arch_upd, s3wake, fsp_version); |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 182 | |
| 183 | return CB_SUCCESS; |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 184 | } |
| 185 | |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 186 | static enum fsp_status do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, |
| 187 | const struct memranges *memmap) |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 188 | { |
| 189 | enum fsp_status status; |
| 190 | fsp_memory_init_fn fsp_raminit; |
| 191 | struct FSPM_UPD fspm_upd, *upd; |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 192 | void *hob_list_ptr; |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 193 | struct FSPM_ARCH_UPD *arch_upd; |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 194 | |
| 195 | post_code(0x34); |
| 196 | |
| 197 | upd = (struct FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base); |
| 198 | |
| 199 | if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE) { |
| 200 | printk(BIOS_ERR, "Invalid FSPM signature\n"); |
| 201 | return FSP_INCOMPATIBLE_VERSION; |
| 202 | } |
| 203 | |
| 204 | /* Copy the default values from the UPD area */ |
| 205 | memcpy(&fspm_upd, upd, sizeof(fspm_upd)); |
| 206 | |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 207 | arch_upd = &fspm_upd.FspmArchUpd; |
| 208 | |
Aaron Durbin | 2792868 | 2016-07-15 22:32:28 -0500 | [diff] [blame] | 209 | /* Reserve enough memory under TOLUD to save CBMEM header */ |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 210 | arch_upd->BootLoaderTolumSize = cbmem_overhead_size(); |
Aaron Durbin | 2792868 | 2016-07-15 22:32:28 -0500 | [diff] [blame] | 211 | |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 212 | /* Fill common settings on behalf of chipset. */ |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 213 | if (fsp_fill_common_arch_params(arch_upd, s3wake, hdr->fsp_revision, |
| 214 | memmap) != CB_SUCCESS) |
| 215 | return FSP_NOT_FOUND; |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 216 | |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 217 | /* Give SoC and mainboard a chance to update the UPD */ |
| 218 | platform_fsp_memory_init_params_cb(&fspm_upd); |
| 219 | |
| 220 | /* Call FspMemoryInit */ |
| 221 | fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset); |
Lee Leahy | 672df16 | 2016-07-24 18:21:13 -0700 | [diff] [blame] | 222 | fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd, |
| 223 | &hob_list_ptr); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 224 | |
Alexandru Gagniuc | c4ea8f7 | 2016-05-23 12:16:58 -0700 | [diff] [blame] | 225 | post_code(POST_FSP_MEMORY_INIT); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 226 | timestamp_add_now(TS_FSP_MEMORY_INIT_START); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 227 | status = fsp_raminit(&fspm_upd, &hob_list_ptr); |
Alexandru Gagniuc | c4ea8f7 | 2016-05-23 12:16:58 -0700 | [diff] [blame] | 228 | post_code(POST_FSP_MEMORY_INIT); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 229 | timestamp_add_now(TS_FSP_MEMORY_INIT_END); |
| 230 | |
Lee Leahy | 672df16 | 2016-07-24 18:21:13 -0700 | [diff] [blame] | 231 | fsp_debug_after_memory_init(status, hob_list_ptr); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 232 | |
Aaron Durbin | f41f2aa | 2016-07-18 12:03:58 -0500 | [diff] [blame] | 233 | /* Handle any resets requested by FSPM. */ |
| 234 | fsp_handle_reset(status); |
| 235 | |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 236 | if (status != FSP_SUCCESS) |
| 237 | return status; |
| 238 | |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 239 | return do_fsp_post_memory_init(hob_list_ptr, s3wake, hdr->fsp_revision); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 240 | } |
| 241 | |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 242 | /* Load the binary into the memory specified by the info header. */ |
| 243 | static enum cb_err load_fspm_mem(struct fsp_header *hdr, |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 244 | const struct region_device *rdev, |
| 245 | const struct memranges *memmap) |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 246 | { |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 247 | uintptr_t fspm_begin; |
| 248 | uintptr_t fspm_end; |
| 249 | |
| 250 | if (fsp_validate_component(hdr, rdev) != CB_SUCCESS) |
| 251 | return CB_ERR; |
| 252 | |
| 253 | fspm_begin = hdr->image_base; |
| 254 | fspm_end = fspm_begin + hdr->image_size; |
| 255 | |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 256 | if (check_region_overlap(memmap, "FSPM", fspm_begin, fspm_end) != |
| 257 | CB_SUCCESS) |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 258 | return CB_ERR; |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 259 | |
| 260 | /* Load binary into memory at provided address. */ |
| 261 | if (rdev_readat(rdev, (void *)fspm_begin, 0, fspm_end - fspm_begin) < 0) |
| 262 | return CB_ERR; |
| 263 | |
| 264 | return CB_SUCCESS; |
| 265 | } |
| 266 | |
| 267 | /* Handle the case when FSPM is running XIP. */ |
| 268 | static enum cb_err load_fspm_xip(struct fsp_header *hdr, |
| 269 | const struct region_device *rdev) |
| 270 | { |
| 271 | void *base; |
| 272 | |
| 273 | if (fsp_validate_component(hdr, rdev) != CB_SUCCESS) |
| 274 | return CB_ERR; |
| 275 | |
| 276 | base = rdev_mmap_full(rdev); |
| 277 | if ((uintptr_t)base != hdr->image_base) { |
| 278 | printk(BIOS_ERR, "FSPM XIP base does not match: %p vs %p\n", |
| 279 | (void *)(uintptr_t)hdr->image_base, base); |
| 280 | return CB_ERR; |
| 281 | } |
| 282 | |
| 283 | /* |
| 284 | * Since the component is XIP it's already in the address space. Thus, |
| 285 | * there's no need to rdev_munmap(). |
| 286 | */ |
| 287 | return CB_SUCCESS; |
| 288 | } |
| 289 | |
| 290 | enum fsp_status fsp_memory_init(bool s3wake) |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 291 | { |
| 292 | struct fsp_header hdr; |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 293 | enum cb_err status; |
| 294 | struct cbfsf file_desc; |
| 295 | struct region_device file_data; |
| 296 | const char *name = CONFIG_FSP_M_CBFS; |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 297 | struct memranges memmap; |
| 298 | struct range_entry freeranges[2]; |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 299 | |
Furquan Shaikh | 5aea588 | 2016-07-30 18:10:05 -0700 | [diff] [blame^] | 300 | if (IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) && !s3wake) |
| 301 | boot_count_increment(); |
| 302 | |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 303 | if (cbfs_boot_locate(&file_desc, name, NULL)) { |
| 304 | printk(BIOS_ERR, "Could not locate %s in CBFS\n", name); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 305 | return FSP_NOT_FOUND; |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 306 | } |
| 307 | |
| 308 | cbfs_file_data(&file_data, &file_desc); |
| 309 | |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 310 | /* Build up memory map of romstage address space including CAR. */ |
| 311 | memranges_init_empty(&memmap, &freeranges[0], ARRAY_SIZE(freeranges)); |
| 312 | memranges_insert(&memmap, (uintptr_t)_car_region_start, |
| 313 | _car_relocatable_data_end - _car_region_start, 0); |
| 314 | memranges_insert(&memmap, (uintptr_t)_program, _program_size, 0); |
| 315 | |
Lee Leahy | 27cd96a | 2016-07-21 11:16:39 -0700 | [diff] [blame] | 316 | if (!IS_ENABLED(CONFIG_FSP_M_XIP)) |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 317 | status = load_fspm_mem(&hdr, &file_data, &memmap); |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 318 | else |
| 319 | status = load_fspm_xip(&hdr, &file_data); |
| 320 | |
| 321 | if (status != CB_SUCCESS) { |
| 322 | printk(BIOS_ERR, "Loading FSPM failed.\n"); |
| 323 | return FSP_NOT_FOUND; |
| 324 | } |
| 325 | |
| 326 | /* Signal that FSP component has been loaded. */ |
| 327 | prog_segment_loaded(hdr.image_base, hdr.image_size, SEG_FINAL); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 328 | |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 329 | return do_fsp_memory_init(&hdr, s3wake, &memmap); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 330 | } |