Patrick Georgi | ac95903 | 2020-05-05 22:49:26 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 2 | |
Arthur Heymans | fdf6d12 | 2022-05-17 13:07:30 +0200 | [diff] [blame] | 3 | #include <arch/null_breakpoint.h> |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 4 | #include <arch/symbols.h> |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 5 | #include <assert.h> |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 6 | #include <cbfs.h> |
Aaron Durbin | 2792868 | 2016-07-15 22:32:28 -0500 | [diff] [blame] | 7 | #include <cbmem.h> |
Patrick Rudolph | f677d17 | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 8 | #include <cf9_reset.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 9 | #include <console/console.h> |
Furquan Shaikh | 5aea588 | 2016-07-30 18:10:05 -0700 | [diff] [blame] | 10 | #include <elog.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 11 | #include <fsp/api.h> |
| 12 | #include <fsp/util.h> |
| 13 | #include <memrange.h> |
Arthur Heymans | fdf6d12 | 2022-05-17 13:07:30 +0200 | [diff] [blame] | 14 | #include <mode_switch.h> |
Aaron Durbin | decd062 | 2017-12-15 12:26:40 -0700 | [diff] [blame] | 15 | #include <mrc_cache.h> |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 16 | #include <program_loading.h> |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 17 | #include <romstage_handoff.h> |
Arthur Heymans | fdf6d12 | 2022-05-17 13:07:30 +0200 | [diff] [blame] | 18 | #include <security/tpm/tspi.h> |
| 19 | #include <security/vboot/antirollback.h> |
| 20 | #include <security/vboot/vboot_common.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 21 | #include <string.h> |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 22 | #include <symbols.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 23 | #include <timestamp.h> |
Elyes HAOUAS | bd1683d | 2019-05-15 21:05:37 +0200 | [diff] [blame] | 24 | #include <types.h> |
Arthur Heymans | fdf6d12 | 2022-05-17 13:07:30 +0200 | [diff] [blame] | 25 | #include <vb2_api.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 26 | |
Kyösti Mälkki | c987150 | 2019-09-03 07:03:39 +0300 | [diff] [blame] | 27 | static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t)); |
| 28 | |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 29 | static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 30 | { |
| 31 | struct range_entry fsp_mem; |
Reka Norman | 7b5a931 | 2022-09-13 14:06:52 +1000 | [diff] [blame] | 32 | uint32_t *fsp_version_cbmem; |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 33 | |
Michael Niewöhner | bc1dbb3 | 2019-10-24 22:58:25 +0200 | [diff] [blame] | 34 | fsp_find_reserved_memory(&fsp_mem); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 35 | |
| 36 | /* initialize cbmem by adding FSP reserved memory first thing */ |
| 37 | if (!s3wake) { |
| 38 | cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, |
| 39 | range_entry_size(&fsp_mem)); |
| 40 | } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, |
| 41 | range_entry_size(&fsp_mem))) { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 42 | if (CONFIG(HAVE_ACPI_RESUME)) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 43 | printk(BIOS_ERR, "Failed to recover CBMEM in S3 resume.\n"); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 44 | /* Failed S3 resume, reset to come up cleanly */ |
Patrick Rudolph | f677d17 | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 45 | /* FIXME: A "system" reset is likely enough: */ |
| 46 | full_reset(); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 47 | } |
| 48 | } |
| 49 | |
| 50 | /* make sure FSP memory is reserved in cbmem */ |
| 51 | if (range_entry_base(&fsp_mem) != |
| 52 | (uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY)) |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 53 | die("Failed to accommodate FSP reserved memory request!\n"); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 54 | |
Reka Norman | 7b5a931 | 2022-09-13 14:06:52 +1000 | [diff] [blame] | 55 | /* ramstage uses the FSP-M version when updating the MRC cache */ |
| 56 | if (CONFIG(CACHE_MRC_SETTINGS) && !s3wake) { |
| 57 | fsp_version_cbmem = cbmem_add(CBMEM_ID_FSPM_VERSION, |
| 58 | sizeof(fsp_version)); |
| 59 | if (!fsp_version_cbmem) |
| 60 | printk(BIOS_ERR, "Failed to add FSP-M version to cbmem.\n"); |
| 61 | *fsp_version_cbmem = fsp_version; |
| 62 | } |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 63 | |
| 64 | /* Create romstage handof information */ |
Aaron Durbin | 77e1399 | 2016-11-29 17:43:04 -0600 | [diff] [blame] | 65 | romstage_handoff_init(s3wake); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 66 | } |
| 67 | |
Aamir Bohra | 69cd62c | 2018-01-08 11:01:34 +0530 | [diff] [blame] | 68 | static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version) |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 69 | { |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 70 | void *data; |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 71 | size_t mrc_size; |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 72 | |
Patrick Rudolph | 31218a4 | 2020-11-30 15:50:06 +0100 | [diff] [blame] | 73 | arch_upd->NvsBufferPtr = 0; |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 74 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 75 | if (!CONFIG(CACHE_MRC_SETTINGS)) |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 76 | return; |
| 77 | |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 78 | /* Assume boot device is memory mapped. */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 79 | assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 80 | |
Shelley Chen | ad9cd68 | 2020-07-23 16:10:52 -0700 | [diff] [blame] | 81 | data = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA, fsp_version, |
| 82 | &mrc_size); |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 83 | if (data == NULL) |
| 84 | return; |
| 85 | |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 86 | /* MRC cache found */ |
Patrick Rudolph | 31218a4 | 2020-11-30 15:50:06 +0100 | [diff] [blame] | 87 | arch_upd->NvsBufferPtr = (uintptr_t)data; |
Aamir Bohra | 69cd62c | 2018-01-08 11:01:34 +0530 | [diff] [blame] | 88 | |
Subrata Banik | 0593708 | 2023-03-06 08:18:24 +0000 | [diff] [blame^] | 89 | printk(BIOS_SPEW, "MRC cache found, size %zu bytes\n", mrc_size); |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 90 | } |
| 91 | |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 92 | static enum cb_err check_region_overlap(const struct memranges *ranges, |
| 93 | const char *description, |
| 94 | uintptr_t begin, uintptr_t end) |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 95 | { |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 96 | const struct range_entry *r; |
| 97 | |
| 98 | memranges_each_entry(r, ranges) { |
| 99 | if (end <= range_entry_base(r)) |
| 100 | continue; |
| 101 | if (begin >= range_entry_end(r)) |
| 102 | continue; |
Lee Leahy | b20d4ba | 2016-07-31 16:49:28 -0700 | [diff] [blame] | 103 | printk(BIOS_CRIT, "'%s' overlaps currently running program: " |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 104 | "[%p, %p)\n", description, (void *)begin, (void *)end); |
| 105 | return CB_ERR; |
| 106 | } |
| 107 | |
| 108 | return CB_SUCCESS; |
| 109 | } |
Kyösti Mälkki | c987150 | 2019-09-03 07:03:39 +0300 | [diff] [blame] | 110 | |
Aamir Bohra | 6d569e0c | 2018-08-27 13:36:15 +0530 | [diff] [blame] | 111 | static enum cb_err setup_fsp_stack_frame(FSPM_ARCH_UPD *arch_upd, |
| 112 | const struct memranges *memmap) |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 113 | { |
| 114 | uintptr_t stack_begin; |
| 115 | uintptr_t stack_end; |
| 116 | |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 117 | /* |
Aamir Bohra | 6d569e0c | 2018-08-27 13:36:15 +0530 | [diff] [blame] | 118 | * FSPM_UPD passed here is populated with default values |
| 119 | * provided by the blob itself. We let FSPM use top of CAR |
| 120 | * region of the size it requests. |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 121 | */ |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 122 | stack_end = (uintptr_t)_car_region_end; |
| 123 | stack_begin = stack_end - arch_upd->StackSize; |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 124 | if (check_region_overlap(memmap, "FSPM stack", stack_begin, |
| 125 | stack_end) != CB_SUCCESS) |
| 126 | return CB_ERR; |
| 127 | |
Patrick Rudolph | 31218a4 | 2020-11-30 15:50:06 +0100 | [diff] [blame] | 128 | arch_upd->StackBase = stack_begin; |
Aamir Bohra | 6d569e0c | 2018-08-27 13:36:15 +0530 | [diff] [blame] | 129 | return CB_SUCCESS; |
| 130 | } |
| 131 | |
| 132 | static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd, |
| 133 | bool s3wake, uint32_t fsp_version, |
| 134 | const struct memranges *memmap) |
| 135 | { |
Kyösti Mälkki | c987150 | 2019-09-03 07:03:39 +0300 | [diff] [blame] | 136 | /* |
| 137 | * FSP 2.1 version would use same stack as coreboot instead of |
| 138 | * setting up separate stack frame. FSP 2.1 would not relocate stack |
| 139 | * top and does not reinitialize stack pointer. The parameters passed |
| 140 | * as StackBase and StackSize are actually for temporary RAM and HOBs |
| 141 | * and are not related to FSP stack at all. |
Felix Held | 414d7e4 | 2020-08-11 22:54:06 +0200 | [diff] [blame] | 142 | * Non-CAR FSP 2.0 platforms pass a DRAM location for the FSP stack. |
Kyösti Mälkki | c987150 | 2019-09-03 07:03:39 +0300 | [diff] [blame] | 143 | */ |
Felix Held | 414d7e4 | 2020-08-11 22:54:06 +0200 | [diff] [blame] | 144 | if (CONFIG(FSP_USES_CB_STACK) || !ENV_CACHE_AS_RAM) { |
Patrick Rudolph | 31218a4 | 2020-11-30 15:50:06 +0100 | [diff] [blame] | 145 | arch_upd->StackBase = (uintptr_t)temp_ram; |
Kyösti Mälkki | c987150 | 2019-09-03 07:03:39 +0300 | [diff] [blame] | 146 | arch_upd->StackSize = sizeof(temp_ram); |
| 147 | } else if (setup_fsp_stack_frame(arch_upd, memmap)) { |
Aamir Bohra | 6d569e0c | 2018-08-27 13:36:15 +0530 | [diff] [blame] | 148 | return CB_ERR; |
Kyösti Mälkki | c987150 | 2019-09-03 07:03:39 +0300 | [diff] [blame] | 149 | } |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 150 | |
Aamir Bohra | 69cd62c | 2018-01-08 11:01:34 +0530 | [diff] [blame] | 151 | fsp_fill_mrc_cache(arch_upd, fsp_version); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 152 | |
Aamir Bohra | 69cd62c | 2018-01-08 11:01:34 +0530 | [diff] [blame] | 153 | /* Configure bootmode */ |
| 154 | if (s3wake) { |
Aamir Bohra | 69cd62c | 2018-01-08 11:01:34 +0530 | [diff] [blame] | 155 | arch_upd->BootMode = FSP_BOOT_ON_S3_RESUME; |
| 156 | } else { |
| 157 | if (arch_upd->NvsBufferPtr) |
| 158 | arch_upd->BootMode = |
| 159 | FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; |
| 160 | else |
| 161 | arch_upd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; |
| 162 | } |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 163 | |
Marshall Dawson | 22d66ef | 2019-08-30 14:52:37 -0600 | [diff] [blame] | 164 | printk(BIOS_SPEW, "bootmode is set to: %d\n", arch_upd->BootMode); |
Aamir Bohra | 276c06a | 2017-12-26 17:54:45 +0530 | [diff] [blame] | 165 | |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 166 | return CB_SUCCESS; |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 167 | } |
| 168 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 169 | __weak |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 170 | uint8_t fsp_memory_mainboard_version(void) |
| 171 | { |
| 172 | return 0; |
| 173 | } |
| 174 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 175 | __weak |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 176 | uint8_t fsp_memory_soc_version(void) |
| 177 | { |
| 178 | return 0; |
| 179 | } |
| 180 | |
| 181 | /* |
| 182 | * Allow SoC and/or mainboard to bump the revision of the FSP setting |
| 183 | * number. The FSP spec uses the low 8 bits as the build number. Take over |
| 184 | * bits 3:0 for the SoC setting and bits 7:4 for the mainboard. That way |
| 185 | * a tweak in the settings will bump the version used to track the cached |
| 186 | * setting which triggers retraining when the FSP version hasn't changed, but |
| 187 | * the SoC or mainboard settings have. |
| 188 | */ |
| 189 | static uint32_t fsp_memory_settings_version(const struct fsp_header *hdr) |
| 190 | { |
| 191 | /* Use the full FSP version by default. */ |
Julian Schroeder | 8a576f6 | 2021-11-02 16:32:28 -0500 | [diff] [blame] | 192 | uint32_t ver = hdr->image_revision; |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 193 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 194 | if (!CONFIG(FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS)) |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 195 | return ver; |
| 196 | |
| 197 | ver &= ~0xff; |
| 198 | ver |= (0xf & fsp_memory_mainboard_version()) << 4; |
| 199 | ver |= (0xf & fsp_memory_soc_version()) << 0; |
| 200 | |
| 201 | return ver; |
| 202 | } |
| 203 | |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 204 | struct fspm_context { |
| 205 | struct fsp_header header; |
| 206 | struct memranges memmap; |
| 207 | }; |
| 208 | |
| 209 | static void do_fsp_memory_init(const struct fspm_context *context, bool s3wake) |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 210 | { |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 211 | uint32_t status; |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 212 | fsp_memory_init_fn fsp_raminit; |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 213 | FSPM_UPD fspm_upd, *upd; |
| 214 | FSPM_ARCH_UPD *arch_upd; |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 215 | uint32_t fsp_version; |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 216 | const struct fsp_header *hdr = &context->header; |
| 217 | const struct memranges *memmap = &context->memmap; |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 218 | |
Furquan Shaikh | 585210a | 2018-10-16 11:54:37 -0700 | [diff] [blame] | 219 | post_code(POST_MEM_PREINIT_PREP_START); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 220 | |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 221 | fsp_version = fsp_memory_settings_version(hdr); |
| 222 | |
Patrick Rudolph | 31218a4 | 2020-11-30 15:50:06 +0100 | [diff] [blame] | 223 | upd = (FSPM_UPD *)(uintptr_t)(hdr->cfg_region_offset + hdr->image_base); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 224 | |
Felix Held | a095595 | 2021-02-02 21:30:25 +0100 | [diff] [blame] | 225 | /* |
| 226 | * Verify UPD region size. We don't have malloc before ramstage, so we |
| 227 | * use a static buffer for the FSP-M UPDs which is sizeof(FSPM_UPD) |
| 228 | * bytes long, since that is the value known at compile time. If |
| 229 | * hdr->cfg_region_size is bigger than that, not all UPD defaults will |
| 230 | * be copied, so it'll contain random data at the end, so we just call |
| 231 | * die() in that case. If hdr->cfg_region_size is smaller than that, |
| 232 | * there's a mismatch between the FSP and the header, but since it will |
| 233 | * copy the full UPD defaults to the buffer, we try to continue and |
| 234 | * hope that there was no incompatible change in the UPDs. |
| 235 | */ |
| 236 | if (hdr->cfg_region_size > sizeof(FSPM_UPD)) |
| 237 | die("FSP-M UPD size is larger than FSPM_UPD struct size.\n"); |
| 238 | if (hdr->cfg_region_size < sizeof(FSPM_UPD)) |
| 239 | printk(BIOS_ERR, "FSP-M UPD size is smaller than FSPM_UPD struct size. " |
| 240 | "Check if the FSP binary matches the FSP headers.\n"); |
| 241 | |
Felix Held | 8899598 | 2021-01-28 22:43:52 +0100 | [diff] [blame] | 242 | fsp_verify_upd_header_signature(upd->FspUpdHeader.Signature, FSPM_UPD_SIGNATURE); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 243 | |
| 244 | /* Copy the default values from the UPD area */ |
| 245 | memcpy(&fspm_upd, upd, sizeof(fspm_upd)); |
| 246 | |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 247 | arch_upd = &fspm_upd.FspmArchUpd; |
| 248 | |
Aaron Durbin | 2792868 | 2016-07-15 22:32:28 -0500 | [diff] [blame] | 249 | /* Reserve enough memory under TOLUD to save CBMEM header */ |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 250 | arch_upd->BootLoaderTolumSize = cbmem_overhead_size(); |
Aaron Durbin | 2792868 | 2016-07-15 22:32:28 -0500 | [diff] [blame] | 251 | |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 252 | /* Fill common settings on behalf of chipset. */ |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 253 | if (fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version, |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 254 | memmap) != CB_SUCCESS) |
Keith Short | bb41aba | 2019-05-16 14:07:43 -0600 | [diff] [blame] | 255 | die_with_post_code(POST_INVALID_VENDOR_BINARY, |
| 256 | "FSPM_ARCH_UPD not found!\n"); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 257 | |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 258 | /* Give SoC and mainboard a chance to update the UPD */ |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 259 | platform_fsp_memory_init_params_cb(&fspm_upd, fsp_version); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 260 | |
Furquan Shaikh | dbce8ba | 2020-06-05 19:17:00 -0700 | [diff] [blame] | 261 | /* |
| 262 | * For S3 resume case, if valid mrc cache data is not found or |
| 263 | * RECOVERY_MRC_CACHE hash verification fails, the S3 data |
| 264 | * pointer would be null and S3 resume fails with fsp-m |
| 265 | * returning error. Invoking a reset here saves time. |
| 266 | */ |
| 267 | if (s3wake && !arch_upd->NvsBufferPtr) |
| 268 | /* FIXME: A "system" reset is likely enough: */ |
| 269 | full_reset(); |
| 270 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 271 | if (CONFIG(MMA)) |
Pratik Prajapati | ffc934d | 2016-11-18 14:36:34 -0800 | [diff] [blame] | 272 | setup_mma(&fspm_upd.FspmConfig); |
| 273 | |
Furquan Shaikh | 585210a | 2018-10-16 11:54:37 -0700 | [diff] [blame] | 274 | post_code(POST_MEM_PREINIT_PREP_END); |
| 275 | |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 276 | /* Call FspMemoryInit */ |
Julian Schroeder | 8a576f6 | 2021-11-02 16:32:28 -0500 | [diff] [blame] | 277 | fsp_raminit = (void *)(uintptr_t)(hdr->image_base + hdr->fsp_memory_init_entry_offset); |
Lee Leahy | ac3b0a6 | 2016-07-27 07:40:25 -0700 | [diff] [blame] | 278 | fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 279 | |
Arthur Heymans | fdf6d12 | 2022-05-17 13:07:30 +0200 | [diff] [blame] | 280 | /* FSP disables the interrupt handler so remove debug exceptions temporarily */ |
| 281 | null_breakpoint_disable(); |
Alexandru Gagniuc | c4ea8f7 | 2016-05-23 12:16:58 -0700 | [diff] [blame] | 282 | post_code(POST_FSP_MEMORY_INIT); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 283 | timestamp_add_now(TS_FSP_MEMORY_INIT_START); |
Patrick Rudolph | 31218a4 | 2020-11-30 15:50:06 +0100 | [diff] [blame] | 284 | if (ENV_X86_64 && CONFIG(PLATFORM_USES_FSP2_X86_32)) |
Patrick Rudolph | 40beb36 | 2020-12-01 10:08:38 +0100 | [diff] [blame] | 285 | status = protected_mode_call_2arg(fsp_raminit, |
| 286 | (uintptr_t)&fspm_upd, |
| 287 | (uintptr_t)fsp_get_hob_list_ptr()); |
| 288 | else |
| 289 | status = fsp_raminit(&fspm_upd, fsp_get_hob_list_ptr()); |
Arthur Heymans | fdf6d12 | 2022-05-17 13:07:30 +0200 | [diff] [blame] | 290 | null_breakpoint_init(); |
Patrick Rudolph | 40beb36 | 2020-12-01 10:08:38 +0100 | [diff] [blame] | 291 | |
Subrata Banik | 0755ab9 | 2017-07-12 15:31:06 +0530 | [diff] [blame] | 292 | post_code(POST_FSP_MEMORY_EXIT); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 293 | timestamp_add_now(TS_FSP_MEMORY_INIT_END); |
| 294 | |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 295 | /* Handle any errors returned by FspMemoryInit */ |
Aaron Durbin | f41f2aa | 2016-07-18 12:03:58 -0500 | [diff] [blame] | 296 | fsp_handle_reset(status); |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 297 | if (status != FSP_SUCCESS) { |
Keith Short | 2430263 | 2019-05-16 14:08:31 -0600 | [diff] [blame] | 298 | die_with_post_code(POST_RAM_FAILURE, |
Angel Pons | 2b1f8d4 | 2022-01-01 17:20:00 +0100 | [diff] [blame] | 299 | "FspMemoryInit returned with error 0x%08x!\n", status); |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 300 | } |
Aaron Durbin | f41f2aa | 2016-07-18 12:03:58 -0500 | [diff] [blame] | 301 | |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 302 | do_fsp_post_memory_init(s3wake, fsp_version); |
Matthew Garrett | 78b58a4 | 2018-07-28 16:53:16 -0700 | [diff] [blame] | 303 | |
| 304 | /* |
| 305 | * fsp_debug_after_memory_init() checks whether the end of the tolum |
| 306 | * region is the same as the top of cbmem, so must be called here |
| 307 | * after cbmem has been initialised in do_fsp_post_memory_init(). |
| 308 | */ |
| 309 | fsp_debug_after_memory_init(status); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 310 | } |
| 311 | |
Julius Werner | 8205ce6 | 2021-03-10 17:25:01 -0800 | [diff] [blame] | 312 | static void *fspm_allocator(void *arg, size_t size, const union cbfs_mdata *unused) |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 313 | { |
Julius Werner | 8205ce6 | 2021-03-10 17:25:01 -0800 | [diff] [blame] | 314 | const struct fsp_load_descriptor *fspld = arg; |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 315 | struct fspm_context *context = fspld->arg; |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 316 | struct memranges *memmap = &context->memmap; |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 317 | |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 318 | /* Non XIP FSP-M uses FSP-M address */ |
Julius Werner | 8205ce6 | 2021-03-10 17:25:01 -0800 | [diff] [blame] | 319 | uintptr_t fspm_begin = (uintptr_t)CONFIG_FSP_M_ADDR; |
| 320 | uintptr_t fspm_end = fspm_begin + size; |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 321 | |
| 322 | if (check_region_overlap(memmap, "FSPM", fspm_begin, fspm_end) != CB_SUCCESS) |
Julius Werner | 8205ce6 | 2021-03-10 17:25:01 -0800 | [diff] [blame] | 323 | return NULL; |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 324 | |
Julius Werner | 8205ce6 | 2021-03-10 17:25:01 -0800 | [diff] [blame] | 325 | return (void *)fspm_begin; |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 326 | } |
| 327 | |
Raul E Rangel | 1592846 | 2021-11-05 10:29:24 -0600 | [diff] [blame] | 328 | void preload_fspm(void) |
| 329 | { |
| 330 | if (!CONFIG(CBFS_PRELOAD)) |
| 331 | return; |
| 332 | |
| 333 | printk(BIOS_DEBUG, "Preloading %s\n", CONFIG_FSP_M_CBFS); |
| 334 | cbfs_preload(CONFIG_FSP_M_CBFS); |
| 335 | } |
| 336 | |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 337 | void fsp_memory_init(bool s3wake) |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 338 | { |
Marshall Dawson | e3aa424 | 2019-10-16 21:53:21 -0600 | [diff] [blame] | 339 | struct range_entry prog_ranges[2]; |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 340 | struct fspm_context context; |
| 341 | struct fsp_load_descriptor fspld = { |
| 342 | .fsp_prog = PROG_INIT(PROG_REFCODE, CONFIG_FSP_M_CBFS), |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 343 | .arg = &context, |
| 344 | }; |
| 345 | struct fsp_header *hdr = &context.header; |
| 346 | struct memranges *memmap = &context.memmap; |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 347 | |
Julius Werner | 8205ce6 | 2021-03-10 17:25:01 -0800 | [diff] [blame] | 348 | /* For FSP-M XIP we leave alloc NULL to get a direct mapping to flash. */ |
| 349 | if (!CONFIG(FSP_M_XIP)) |
| 350 | fspld.alloc = fspm_allocator; |
| 351 | |
Kyösti Mälkki | 7f50afb | 2019-09-11 17:12:26 +0300 | [diff] [blame] | 352 | elog_boot_notify(s3wake); |
Furquan Shaikh | 5aea588 | 2016-07-30 18:10:05 -0700 | [diff] [blame] | 353 | |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 354 | /* Build up memory map of romstage address space including CAR. */ |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 355 | memranges_init_empty(memmap, &prog_ranges[0], ARRAY_SIZE(prog_ranges)); |
Marshall Dawson | e3aa424 | 2019-10-16 21:53:21 -0600 | [diff] [blame] | 356 | if (ENV_CACHE_AS_RAM) |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 357 | memranges_insert(memmap, (uintptr_t)_car_region_start, |
Marshall Dawson | e3aa424 | 2019-10-16 21:53:21 -0600 | [diff] [blame] | 358 | _car_unallocated_start - _car_region_start, 0); |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 359 | memranges_insert(memmap, (uintptr_t)_program, REGION_SIZE(program), 0); |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 360 | |
Martin Roth | 146508d | 2021-04-30 16:45:08 -0600 | [diff] [blame] | 361 | timestamp_add_now(TS_FSP_MEMORY_INIT_LOAD); |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 362 | if (fsp_load_component(&fspld, hdr) != CB_SUCCESS) |
| 363 | die("FSPM not available or failed to load!\n"); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 364 | |
Julius Werner | 8205ce6 | 2021-03-10 17:25:01 -0800 | [diff] [blame] | 365 | if (CONFIG(FSP_M_XIP) && (uintptr_t)prog_start(&fspld.fsp_prog) != hdr->image_base) |
| 366 | die("FSPM XIP base does not match: %p vs %p\n", |
| 367 | (void *)(uintptr_t)hdr->image_base, prog_start(&fspld.fsp_prog)); |
| 368 | |
Jakub Czapiga | ad6157e | 2022-02-15 11:50:31 +0100 | [diff] [blame] | 369 | timestamp_add_now(TS_INITRAM_START); |
Kyösti Mälkki | 216db61 | 2019-09-11 09:57:14 +0300 | [diff] [blame] | 370 | |
Aaron Durbin | ecbfa99 | 2020-05-15 17:01:58 -0600 | [diff] [blame] | 371 | do_fsp_memory_init(&context, s3wake); |
Kyösti Mälkki | 0889e93 | 2019-08-18 07:40:43 +0300 | [diff] [blame] | 372 | |
Jakub Czapiga | ad6157e | 2022-02-15 11:50:31 +0100 | [diff] [blame] | 373 | timestamp_add_now(TS_INITRAM_END); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 374 | } |