Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Lee Leahy | 47bd2d9 | 2016-07-24 18:12:16 -0700 | [diff] [blame] | 4 | * Copyright (C) 2015-2016 Intel Corp. |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 5 | * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) |
| 6 | * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | */ |
| 13 | |
Philipp Deppenwiese | c07f8fb | 2018-02-27 19:40:52 +0100 | [diff] [blame] | 14 | #include <security/vboot/antirollback.h> |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 15 | #include <arch/symbols.h> |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 16 | #include <assert.h> |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 17 | #include <cbfs.h> |
Aaron Durbin | 2792868 | 2016-07-15 22:32:28 -0500 | [diff] [blame] | 18 | #include <cbmem.h> |
Patrick Rudolph | f677d17 | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 19 | #include <cf9_reset.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 20 | #include <console/console.h> |
Furquan Shaikh | 5aea588 | 2016-07-30 18:10:05 -0700 | [diff] [blame] | 21 | #include <elog.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 22 | #include <fsp/api.h> |
| 23 | #include <fsp/util.h> |
| 24 | #include <memrange.h> |
Aaron Durbin | decd062 | 2017-12-15 12:26:40 -0700 | [diff] [blame] | 25 | #include <mrc_cache.h> |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 26 | #include <program_loading.h> |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 27 | #include <romstage_handoff.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 28 | #include <string.h> |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 29 | #include <symbols.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 30 | #include <timestamp.h> |
Philipp Deppenwiese | fea2429 | 2017-10-17 17:02:29 +0200 | [diff] [blame] | 31 | #include <security/vboot/vboot_common.h> |
Philipp Deppenwiese | 80961af | 2018-02-27 22:14:34 +0100 | [diff] [blame] | 32 | #include <security/tpm/tspi.h> |
Furquan Shaikh | 2db5bac | 2016-11-07 23:57:48 -0800 | [diff] [blame] | 33 | #include <vb2_api.h> |
Philipp Deppenwiese | 80961af | 2018-02-27 22:14:34 +0100 | [diff] [blame] | 34 | #include <fsp/memory_init.h> |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 35 | |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 36 | static void save_memory_training_data(bool s3wake, uint32_t fsp_version) |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 37 | { |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 38 | size_t mrc_data_size; |
| 39 | const void *mrc_data; |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 40 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 41 | if (!CONFIG(CACHE_MRC_SETTINGS) || s3wake) |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 42 | return; |
| 43 | |
| 44 | mrc_data = fsp_find_nv_storage_data(&mrc_data_size); |
| 45 | if (!mrc_data) { |
| 46 | printk(BIOS_ERR, "Couldn't find memory training data HOB.\n"); |
| 47 | return; |
| 48 | } |
| 49 | |
| 50 | /* |
| 51 | * Save MRC Data to CBMEM. By always saving the data this forces |
| 52 | * a retrain after a trip through Chrome OS recovery path. The |
| 53 | * code which saves the data to flash doesn't write if the latest |
| 54 | * training data matches this one. |
| 55 | */ |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 56 | if (mrc_cache_stash_data(MRC_TRAINING_DATA, fsp_version, mrc_data, |
| 57 | mrc_data_size) < 0) |
| 58 | printk(BIOS_ERR, "Failed to stash MRC data\n"); |
Furquan Shaikh | 2db5bac | 2016-11-07 23:57:48 -0800 | [diff] [blame] | 59 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 60 | if (CONFIG(FSP2_0_USES_TPM_MRC_HASH)) |
Philipp Deppenwiese | 80961af | 2018-02-27 22:14:34 +0100 | [diff] [blame] | 61 | mrc_cache_update_hash(mrc_data, mrc_data_size); |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 62 | } |
| 63 | |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 64 | static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version) |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 65 | { |
| 66 | struct range_entry fsp_mem; |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 67 | |
Lee Leahy | 52d0c68 | 2016-08-01 15:47:42 -0700 | [diff] [blame] | 68 | if (fsp_find_reserved_memory(&fsp_mem)) |
| 69 | die("Failed to find FSP_RESERVED_MEMORY_RESOURCE_HOB!\n"); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 70 | |
| 71 | /* initialize cbmem by adding FSP reserved memory first thing */ |
| 72 | if (!s3wake) { |
| 73 | cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, |
| 74 | range_entry_size(&fsp_mem)); |
| 75 | } else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, |
| 76 | range_entry_size(&fsp_mem))) { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 77 | if (CONFIG(HAVE_ACPI_RESUME)) { |
Lee Leahy | b20d4ba | 2016-07-31 16:49:28 -0700 | [diff] [blame] | 78 | printk(BIOS_ERR, |
Lee Leahy | ac3b0a6 | 2016-07-27 07:40:25 -0700 | [diff] [blame] | 79 | "Failed to recover CBMEM in S3 resume.\n"); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 80 | /* Failed S3 resume, reset to come up cleanly */ |
Patrick Rudolph | f677d17 | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 81 | /* FIXME: A "system" reset is likely enough: */ |
| 82 | full_reset(); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 83 | } |
| 84 | } |
| 85 | |
| 86 | /* make sure FSP memory is reserved in cbmem */ |
| 87 | if (range_entry_base(&fsp_mem) != |
| 88 | (uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY)) |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 89 | die("Failed to accommodate FSP reserved memory request!\n"); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 90 | |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 91 | save_memory_training_data(s3wake, fsp_version); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 92 | |
| 93 | /* Create romstage handof information */ |
Aaron Durbin | 77e1399 | 2016-11-29 17:43:04 -0600 | [diff] [blame] | 94 | romstage_handoff_init(s3wake); |
Youness Alaoui | 676887d | 2018-02-07 11:49:35 -0500 | [diff] [blame] | 95 | |
| 96 | /* |
| 97 | * Initialize the TPM, unless the TPM was already initialized |
| 98 | * in verstage and used to verify romstage. |
| 99 | */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 100 | if ((CONFIG(TPM1) || CONFIG(TPM2)) && |
| 101 | !CONFIG(VBOOT_STARTS_IN_BOOTBLOCK)) |
Philipp Deppenwiese | c07f8fb | 2018-02-27 19:40:52 +0100 | [diff] [blame] | 102 | tpm_setup(s3wake); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 103 | } |
| 104 | |
Aamir Bohra | 69cd62c | 2018-01-08 11:01:34 +0530 | [diff] [blame] | 105 | static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version) |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 106 | { |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 107 | struct region_device rdev; |
| 108 | void *data; |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 109 | |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 110 | arch_upd->NvsBufferPtr = NULL; |
| 111 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 112 | if (!CONFIG(CACHE_MRC_SETTINGS)) |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 113 | return; |
| 114 | |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 115 | /* |
| 116 | * In recovery mode, force retraining: |
| 117 | * 1. Recovery cache is not supported, or |
| 118 | * 2. Memory retrain switch is set. |
| 119 | */ |
| 120 | if (vboot_recovery_mode_enabled()) { |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 121 | if (!CONFIG(HAS_RECOVERY_MRC_CACHE)) |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 122 | return; |
| 123 | if (vboot_recovery_mode_memory_retrain()) |
| 124 | return; |
| 125 | } |
Aaron Durbin | 98ea636 | 2016-07-18 11:31:53 -0500 | [diff] [blame] | 126 | |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 127 | if (mrc_cache_get_current(MRC_TRAINING_DATA, fsp_version, &rdev) < 0) |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 128 | return; |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 129 | |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 130 | /* Assume boot device is memory mapped. */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 131 | assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED)); |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 132 | data = rdev_mmap_full(&rdev); |
| 133 | |
| 134 | if (data == NULL) |
| 135 | return; |
| 136 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 137 | if (CONFIG(FSP2_0_USES_TPM_MRC_HASH) && |
Philipp Deppenwiese | 80961af | 2018-02-27 22:14:34 +0100 | [diff] [blame] | 138 | !mrc_cache_verify_hash(data, region_device_sz(&rdev))) |
Furquan Shaikh | 2db5bac | 2016-11-07 23:57:48 -0800 | [diff] [blame] | 139 | return; |
| 140 | |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 141 | /* MRC cache found */ |
Aaron Durbin | 31be2c9 | 2016-12-03 22:08:20 -0600 | [diff] [blame] | 142 | arch_upd->NvsBufferPtr = data; |
Aamir Bohra | 69cd62c | 2018-01-08 11:01:34 +0530 | [diff] [blame] | 143 | |
| 144 | printk(BIOS_SPEW, "MRC cache found, size %zx\n", |
| 145 | region_device_sz(&rdev)); |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 146 | } |
| 147 | |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 148 | static enum cb_err check_region_overlap(const struct memranges *ranges, |
| 149 | const char *description, |
| 150 | uintptr_t begin, uintptr_t end) |
Aaron Durbin | f0ec824 | 2016-07-18 11:24:36 -0500 | [diff] [blame] | 151 | { |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 152 | const struct range_entry *r; |
| 153 | |
| 154 | memranges_each_entry(r, ranges) { |
| 155 | if (end <= range_entry_base(r)) |
| 156 | continue; |
| 157 | if (begin >= range_entry_end(r)) |
| 158 | continue; |
Lee Leahy | b20d4ba | 2016-07-31 16:49:28 -0700 | [diff] [blame] | 159 | printk(BIOS_CRIT, "'%s' overlaps currently running program: " |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 160 | "[%p, %p)\n", description, (void *)begin, (void *)end); |
| 161 | return CB_ERR; |
| 162 | } |
| 163 | |
| 164 | return CB_SUCCESS; |
| 165 | } |
Aamir Bohra | 6d569e0c | 2018-08-27 13:36:15 +0530 | [diff] [blame] | 166 | static enum cb_err setup_fsp_stack_frame(FSPM_ARCH_UPD *arch_upd, |
| 167 | const struct memranges *memmap) |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 168 | { |
| 169 | uintptr_t stack_begin; |
| 170 | uintptr_t stack_end; |
| 171 | |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 172 | /* |
Aamir Bohra | 6d569e0c | 2018-08-27 13:36:15 +0530 | [diff] [blame] | 173 | * FSP 2.1 version would use same stack as coreboot instead of |
| 174 | * setting up seprate stack frame. FSP 2.1 would not relocate stack |
| 175 | * top and does not reinitialize stack pointer. |
| 176 | */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 177 | if (CONFIG(FSP_USES_CB_STACK)) { |
Aamir Bohra | 6d569e0c | 2018-08-27 13:36:15 +0530 | [diff] [blame] | 178 | arch_upd->StackBase = (void *)_car_stack_end; |
| 179 | arch_upd->StackSize = CONFIG_DCACHE_BSP_STACK_SIZE; |
| 180 | return CB_SUCCESS; |
| 181 | } |
| 182 | |
| 183 | /* |
| 184 | * FSPM_UPD passed here is populated with default values |
| 185 | * provided by the blob itself. We let FSPM use top of CAR |
| 186 | * region of the size it requests. |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 187 | */ |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 188 | stack_end = (uintptr_t)_car_region_end; |
| 189 | stack_begin = stack_end - arch_upd->StackSize; |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 190 | if (check_region_overlap(memmap, "FSPM stack", stack_begin, |
| 191 | stack_end) != CB_SUCCESS) |
| 192 | return CB_ERR; |
| 193 | |
| 194 | arch_upd->StackBase = (void *)stack_begin; |
Aamir Bohra | 6d569e0c | 2018-08-27 13:36:15 +0530 | [diff] [blame] | 195 | return CB_SUCCESS; |
| 196 | } |
| 197 | |
| 198 | static enum cb_err fsp_fill_common_arch_params(FSPM_ARCH_UPD *arch_upd, |
| 199 | bool s3wake, uint32_t fsp_version, |
| 200 | const struct memranges *memmap) |
| 201 | { |
| 202 | if (setup_fsp_stack_frame(arch_upd, memmap)) |
| 203 | return CB_ERR; |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 204 | |
Aamir Bohra | 69cd62c | 2018-01-08 11:01:34 +0530 | [diff] [blame] | 205 | fsp_fill_mrc_cache(arch_upd, fsp_version); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 206 | |
Aamir Bohra | 69cd62c | 2018-01-08 11:01:34 +0530 | [diff] [blame] | 207 | /* Configure bootmode */ |
| 208 | if (s3wake) { |
| 209 | /* |
| 210 | * For S3 resume case, if valid mrc cache data is not found or |
| 211 | * RECOVERY_MRC_CACHE hash verification fails, the S3 data |
| 212 | * pointer would be null and S3 resume fails with fsp-m |
| 213 | * returning error. Invoking a reset here saves time. |
| 214 | */ |
| 215 | if (!arch_upd->NvsBufferPtr) |
Patrick Rudolph | f677d17 | 2018-10-01 19:17:11 +0200 | [diff] [blame] | 216 | /* FIXME: A "system" reset is likely enough: */ |
| 217 | full_reset(); |
Aamir Bohra | 69cd62c | 2018-01-08 11:01:34 +0530 | [diff] [blame] | 218 | arch_upd->BootMode = FSP_BOOT_ON_S3_RESUME; |
| 219 | } else { |
| 220 | if (arch_upd->NvsBufferPtr) |
| 221 | arch_upd->BootMode = |
| 222 | FSP_BOOT_ASSUMING_NO_CONFIGURATION_CHANGES; |
| 223 | else |
| 224 | arch_upd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; |
| 225 | } |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 226 | |
Aamir Bohra | 69cd62c | 2018-01-08 11:01:34 +0530 | [diff] [blame] | 227 | printk(BIOS_SPEW, "bootmode is set to :%d\n", arch_upd->BootMode); |
Aamir Bohra | 276c06a | 2017-12-26 17:54:45 +0530 | [diff] [blame] | 228 | |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 229 | return CB_SUCCESS; |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 230 | } |
| 231 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 232 | __weak |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 233 | uint8_t fsp_memory_mainboard_version(void) |
| 234 | { |
| 235 | return 0; |
| 236 | } |
| 237 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 238 | __weak |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 239 | uint8_t fsp_memory_soc_version(void) |
| 240 | { |
| 241 | return 0; |
| 242 | } |
| 243 | |
| 244 | /* |
| 245 | * Allow SoC and/or mainboard to bump the revision of the FSP setting |
| 246 | * number. The FSP spec uses the low 8 bits as the build number. Take over |
| 247 | * bits 3:0 for the SoC setting and bits 7:4 for the mainboard. That way |
| 248 | * a tweak in the settings will bump the version used to track the cached |
| 249 | * setting which triggers retraining when the FSP version hasn't changed, but |
| 250 | * the SoC or mainboard settings have. |
| 251 | */ |
| 252 | static uint32_t fsp_memory_settings_version(const struct fsp_header *hdr) |
| 253 | { |
| 254 | /* Use the full FSP version by default. */ |
| 255 | uint32_t ver = hdr->fsp_revision; |
| 256 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 257 | if (!CONFIG(FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS)) |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 258 | return ver; |
| 259 | |
| 260 | ver &= ~0xff; |
| 261 | ver |= (0xf & fsp_memory_mainboard_version()) << 4; |
| 262 | ver |= (0xf & fsp_memory_soc_version()) << 0; |
| 263 | |
| 264 | return ver; |
| 265 | } |
| 266 | |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 267 | static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 268 | const struct memranges *memmap) |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 269 | { |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 270 | uint32_t status; |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 271 | fsp_memory_init_fn fsp_raminit; |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 272 | FSPM_UPD fspm_upd, *upd; |
| 273 | FSPM_ARCH_UPD *arch_upd; |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 274 | uint32_t fsp_version; |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 275 | |
Furquan Shaikh | 585210a | 2018-10-16 11:54:37 -0700 | [diff] [blame] | 276 | post_code(POST_MEM_PREINIT_PREP_START); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 277 | |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 278 | fsp_version = fsp_memory_settings_version(hdr); |
| 279 | |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 280 | upd = (FSPM_UPD *)(hdr->cfg_region_offset + hdr->image_base); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 281 | |
Lee Leahy | e686ee8 | 2017-03-10 08:45:30 -0800 | [diff] [blame] | 282 | if (upd->FspUpdHeader.Signature != FSPM_UPD_SIGNATURE) |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 283 | die("Invalid FSPM signature!\n"); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 284 | |
| 285 | /* Copy the default values from the UPD area */ |
| 286 | memcpy(&fspm_upd, upd, sizeof(fspm_upd)); |
| 287 | |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 288 | arch_upd = &fspm_upd.FspmArchUpd; |
| 289 | |
Aaron Durbin | 2792868 | 2016-07-15 22:32:28 -0500 | [diff] [blame] | 290 | /* Reserve enough memory under TOLUD to save CBMEM header */ |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 291 | arch_upd->BootLoaderTolumSize = cbmem_overhead_size(); |
Aaron Durbin | 2792868 | 2016-07-15 22:32:28 -0500 | [diff] [blame] | 292 | |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 293 | /* Fill common settings on behalf of chipset. */ |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 294 | if (fsp_fill_common_arch_params(arch_upd, s3wake, fsp_version, |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 295 | memmap) != CB_SUCCESS) |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 296 | die("FSPM_ARCH_UPD not found!\n"); |
Aaron Durbin | b430250 | 2016-07-17 17:04:37 -0500 | [diff] [blame] | 297 | |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 298 | /* Give SoC and mainboard a chance to update the UPD */ |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 299 | platform_fsp_memory_init_params_cb(&fspm_upd, fsp_version); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 300 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 301 | if (CONFIG(MMA)) |
Pratik Prajapati | ffc934d | 2016-11-18 14:36:34 -0800 | [diff] [blame] | 302 | setup_mma(&fspm_upd.FspmConfig); |
| 303 | |
Furquan Shaikh | 585210a | 2018-10-16 11:54:37 -0700 | [diff] [blame] | 304 | post_code(POST_MEM_PREINIT_PREP_END); |
| 305 | |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 306 | /* Call FspMemoryInit */ |
| 307 | fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset); |
Lee Leahy | ac3b0a6 | 2016-07-27 07:40:25 -0700 | [diff] [blame] | 308 | fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 309 | |
Alexandru Gagniuc | c4ea8f7 | 2016-05-23 12:16:58 -0700 | [diff] [blame] | 310 | post_code(POST_FSP_MEMORY_INIT); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 311 | timestamp_add_now(TS_FSP_MEMORY_INIT_START); |
Lee Leahy | ac3b0a6 | 2016-07-27 07:40:25 -0700 | [diff] [blame] | 312 | status = fsp_raminit(&fspm_upd, fsp_get_hob_list_ptr()); |
Subrata Banik | 0755ab9 | 2017-07-12 15:31:06 +0530 | [diff] [blame] | 313 | post_code(POST_FSP_MEMORY_EXIT); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 314 | timestamp_add_now(TS_FSP_MEMORY_INIT_END); |
| 315 | |
Lee Leahy | ac3b0a6 | 2016-07-27 07:40:25 -0700 | [diff] [blame] | 316 | fsp_debug_after_memory_init(status); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 317 | |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 318 | /* Handle any errors returned by FspMemoryInit */ |
Aaron Durbin | f41f2aa | 2016-07-18 12:03:58 -0500 | [diff] [blame] | 319 | fsp_handle_reset(status); |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 320 | if (status != FSP_SUCCESS) { |
Lee Leahy | b20d4ba | 2016-07-31 16:49:28 -0700 | [diff] [blame] | 321 | printk(BIOS_CRIT, "FspMemoryInit returned 0x%08x\n", status); |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 322 | die("FspMemoryInit returned an error!\n"); |
| 323 | } |
Aaron Durbin | f41f2aa | 2016-07-18 12:03:58 -0500 | [diff] [blame] | 324 | |
Aaron Durbin | a3cecb2 | 2017-04-25 21:58:10 -0500 | [diff] [blame] | 325 | do_fsp_post_memory_init(s3wake, fsp_version); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 326 | } |
| 327 | |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 328 | /* Load the binary into the memory specified by the info header. */ |
| 329 | static enum cb_err load_fspm_mem(struct fsp_header *hdr, |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 330 | const struct region_device *rdev, |
| 331 | const struct memranges *memmap) |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 332 | { |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 333 | uintptr_t fspm_begin; |
| 334 | uintptr_t fspm_end; |
| 335 | |
| 336 | if (fsp_validate_component(hdr, rdev) != CB_SUCCESS) |
| 337 | return CB_ERR; |
| 338 | |
| 339 | fspm_begin = hdr->image_base; |
| 340 | fspm_end = fspm_begin + hdr->image_size; |
| 341 | |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 342 | if (check_region_overlap(memmap, "FSPM", fspm_begin, fspm_end) != |
| 343 | CB_SUCCESS) |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 344 | return CB_ERR; |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 345 | |
| 346 | /* Load binary into memory at provided address. */ |
| 347 | if (rdev_readat(rdev, (void *)fspm_begin, 0, fspm_end - fspm_begin) < 0) |
| 348 | return CB_ERR; |
| 349 | |
| 350 | return CB_SUCCESS; |
| 351 | } |
| 352 | |
| 353 | /* Handle the case when FSPM is running XIP. */ |
| 354 | static enum cb_err load_fspm_xip(struct fsp_header *hdr, |
| 355 | const struct region_device *rdev) |
| 356 | { |
| 357 | void *base; |
| 358 | |
| 359 | if (fsp_validate_component(hdr, rdev) != CB_SUCCESS) |
| 360 | return CB_ERR; |
| 361 | |
| 362 | base = rdev_mmap_full(rdev); |
| 363 | if ((uintptr_t)base != hdr->image_base) { |
Lee Leahy | b20d4ba | 2016-07-31 16:49:28 -0700 | [diff] [blame] | 364 | printk(BIOS_CRIT, "FSPM XIP base does not match: %p vs %p\n", |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 365 | (void *)(uintptr_t)hdr->image_base, base); |
| 366 | return CB_ERR; |
| 367 | } |
| 368 | |
| 369 | /* |
| 370 | * Since the component is XIP it's already in the address space. Thus, |
| 371 | * there's no need to rdev_munmap(). |
| 372 | */ |
| 373 | return CB_SUCCESS; |
| 374 | } |
| 375 | |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 376 | void fsp_memory_init(bool s3wake) |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 377 | { |
| 378 | struct fsp_header hdr; |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 379 | enum cb_err status; |
| 380 | struct cbfsf file_desc; |
| 381 | struct region_device file_data; |
| 382 | const char *name = CONFIG_FSP_M_CBFS; |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 383 | struct memranges memmap; |
| 384 | struct range_entry freeranges[2]; |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 385 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 386 | if (CONFIG(ELOG_BOOT_COUNT) && !s3wake) |
Furquan Shaikh | 5aea588 | 2016-07-30 18:10:05 -0700 | [diff] [blame] | 387 | boot_count_increment(); |
| 388 | |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 389 | if (cbfs_boot_locate(&file_desc, name, NULL)) { |
Lee Leahy | b20d4ba | 2016-07-31 16:49:28 -0700 | [diff] [blame] | 390 | printk(BIOS_CRIT, "Could not locate %s in CBFS\n", name); |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 391 | die("FSPM not available!\n"); |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 392 | } |
| 393 | |
| 394 | cbfs_file_data(&file_data, &file_desc); |
| 395 | |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 396 | /* Build up memory map of romstage address space including CAR. */ |
| 397 | memranges_init_empty(&memmap, &freeranges[0], ARRAY_SIZE(freeranges)); |
| 398 | memranges_insert(&memmap, (uintptr_t)_car_region_start, |
| 399 | _car_relocatable_data_end - _car_region_start, 0); |
Julius Werner | 7e0dea6 | 2019-02-20 18:39:22 -0800 | [diff] [blame] | 400 | memranges_insert(&memmap, (uintptr_t)_program, REGION_SIZE(program), 0); |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 401 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame^] | 402 | if (!CONFIG(FSP_M_XIP)) |
Aaron Durbin | 02e504c | 2016-07-18 11:53:10 -0500 | [diff] [blame] | 403 | status = load_fspm_mem(&hdr, &file_data, &memmap); |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 404 | else |
| 405 | status = load_fspm_xip(&hdr, &file_data); |
| 406 | |
Lee Leahy | e686ee8 | 2017-03-10 08:45:30 -0800 | [diff] [blame] | 407 | if (status != CB_SUCCESS) |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 408 | die("Loading FSPM failed!\n"); |
Aaron Durbin | d04639b | 2016-07-17 23:23:59 -0500 | [diff] [blame] | 409 | |
| 410 | /* Signal that FSP component has been loaded. */ |
| 411 | prog_segment_loaded(hdr.image_base, hdr.image_size, SEG_FINAL); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 412 | |
Lee Leahy | 9671faa | 2016-07-24 18:18:52 -0700 | [diff] [blame] | 413 | do_fsp_memory_init(&hdr, s3wake, &memmap); |
Andrey Petrov | 465fc13 | 2016-02-25 14:16:33 -0800 | [diff] [blame] | 414 | } |