Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 4 | * Copyright (C) 2015 - 2017 Intel Corp. |
Mario Scheithauer | a39aede | 2017-11-06 16:47:27 +0100 | [diff] [blame] | 5 | * Copyright (C) 2017 Siemens AG |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 6 | * (Written by Alexandru Gagniuc <alexandrux.gagniuc@intel.com> for Intel Corp.) |
| 7 | * (Written by Andrey Petrov <andrey.petrov@intel.com> for Intel Corp.) |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
Martin Roth | ebabfad | 2016-04-10 11:09:16 -0600 | [diff] [blame] | 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 18 | */ |
| 19 | |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 20 | #include <arch/acpi.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 21 | #include <bootstate.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 22 | #include <cbmem.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 23 | #include <console/console.h> |
| 24 | #include <cpu/cpu.h> |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 25 | #include <cpu/x86/mp.h> |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame] | 26 | #include <cpu/x86/msr.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 27 | #include <device/device.h> |
| 28 | #include <device/pci.h> |
Mario Scheithauer | 841416f | 2017-09-18 17:08:48 +0200 | [diff] [blame] | 29 | #include <intelblocks/acpi.h> |
Barnali Sarkar | e70142c | 2017-03-28 16:32:33 +0530 | [diff] [blame] | 30 | #include <intelblocks/fast_spi.h> |
Lijian Zhao | 8aba24d | 2017-10-26 12:16:53 -0700 | [diff] [blame] | 31 | #include <intelblocks/p2sb.h> |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame] | 32 | #include <intelblocks/msr.h> |
Duncan Laurie | 4c8fbc0 | 2018-03-26 02:19:58 -0700 | [diff] [blame] | 33 | #include <intelblocks/xdci.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 34 | #include <fsp/api.h> |
| 35 | #include <fsp/util.h> |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame] | 36 | #include <intelblocks/cpulib.h> |
Bora Guvendik | 33117ec | 2017-04-10 15:49:02 -0700 | [diff] [blame] | 37 | #include <intelblocks/itss.h> |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 38 | #include <intelblocks/pmclib.h> |
Brandon Breitenstein | c6ec8dd | 2016-11-17 12:23:04 -0800 | [diff] [blame] | 39 | #include <romstage_handoff.h> |
Andrey Petrov | e07e13d | 2016-03-18 14:43:00 -0700 | [diff] [blame] | 40 | #include <soc/iomap.h> |
Bora Guvendik | 33117ec | 2017-04-10 15:49:02 -0700 | [diff] [blame] | 41 | #include <soc/itss.h> |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 42 | #include <soc/intel/common/vbt.h> |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 43 | #include <soc/nvs.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 44 | #include <soc/pci_devs.h> |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 45 | #include <spi-generic.h> |
Aaron Durbin | ac3e482 | 2017-06-14 13:21:00 -0500 | [diff] [blame] | 46 | #include <soc/cpu.h> |
Andrey Petrov | 3dbea29 | 2016-06-14 22:20:28 -0700 | [diff] [blame] | 47 | #include <soc/pm.h> |
Subrata Banik | 7952e28 | 2017-03-14 18:26:27 +0530 | [diff] [blame] | 48 | #include <soc/systemagent.h> |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 49 | |
| 50 | #include "chip.h" |
| 51 | |
Aaron Durbin | aa090cb | 2017-09-13 16:01:52 -0600 | [diff] [blame] | 52 | static const char *soc_acpi_name(const struct device *dev) |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 53 | { |
| 54 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
| 55 | return "PCI0"; |
| 56 | |
| 57 | if (dev->path.type != DEVICE_PATH_PCI) |
| 58 | return NULL; |
| 59 | |
| 60 | switch (dev->path.pci.devfn) { |
| 61 | /* DSDT: acpi/northbridge.asl */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 62 | case SA_DEVFN_ROOT: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 63 | return "MCHC"; |
| 64 | /* DSDT: acpi/lpc.asl */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 65 | case PCH_DEVFN_LPC: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 66 | return "LPCB"; |
| 67 | /* DSDT: acpi/xhci.asl */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 68 | case PCH_DEVFN_XHCI: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 69 | return "XHCI"; |
| 70 | /* DSDT: acpi/pch_hda.asl */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 71 | case PCH_DEVFN_HDA: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 72 | return "HDAS"; |
| 73 | /* DSDT: acpi/lpss.asl */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 74 | case PCH_DEVFN_UART0: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 75 | return "URT1"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 76 | case PCH_DEVFN_UART1: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 77 | return "URT2"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 78 | case PCH_DEVFN_UART2: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 79 | return "URT3"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 80 | case PCH_DEVFN_UART3: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 81 | return "URT4"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 82 | case PCH_DEVFN_SPI0: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 83 | return "SPI1"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 84 | case PCH_DEVFN_SPI1: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 85 | return "SPI2"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 86 | case PCH_DEVFN_SPI2: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 87 | return "SPI3"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 88 | case PCH_DEVFN_PWM: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 89 | return "PWM"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 90 | case PCH_DEVFN_I2C0: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 91 | return "I2C0"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 92 | case PCH_DEVFN_I2C1: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 93 | return "I2C1"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 94 | case PCH_DEVFN_I2C2: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 95 | return "I2C2"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 96 | case PCH_DEVFN_I2C3: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 97 | return "I2C3"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 98 | case PCH_DEVFN_I2C4: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 99 | return "I2C4"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 100 | case PCH_DEVFN_I2C5: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 101 | return "I2C5"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 102 | case PCH_DEVFN_I2C6: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 103 | return "I2C6"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 104 | case PCH_DEVFN_I2C7: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 105 | return "I2C7"; |
| 106 | /* Storage */ |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 107 | case PCH_DEVFN_SDCARD: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 108 | return "SDCD"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 109 | case PCH_DEVFN_EMMC: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 110 | return "EMMC"; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 111 | case PCH_DEVFN_SDIO: |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 112 | return "SDIO"; |
Vaibhav Shankar | ec9168f | 2016-09-16 14:20:53 -0700 | [diff] [blame] | 113 | /* PCIe */ |
Venkateswarlu Vinjamuri | f03c63e | 2018-04-12 10:13:43 -0700 | [diff] [blame] | 114 | case PCH_DEVFN_PCIE1: |
| 115 | return "RP03"; |
Venkateswarlu Vinjamuri | efeb690 | 2018-04-09 11:14:42 -0700 | [diff] [blame] | 116 | case PCH_DEVFN_PCIE5: |
Vaibhav Shankar | ec9168f | 2016-09-16 14:20:53 -0700 | [diff] [blame] | 117 | return "RP01"; |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 118 | } |
| 119 | |
| 120 | return NULL; |
| 121 | } |
| 122 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 123 | static void pci_domain_set_resources(device_t dev) |
| 124 | { |
Lee Leahy | 1d20fe7 | 2017-03-09 09:50:28 -0800 | [diff] [blame] | 125 | assign_resources(dev->link_list); |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 126 | } |
| 127 | |
| 128 | static struct device_operations pci_domain_ops = { |
| 129 | .read_resources = pci_domain_read_resources, |
| 130 | .set_resources = pci_domain_set_resources, |
| 131 | .enable_resources = NULL, |
| 132 | .init = NULL, |
| 133 | .scan_bus = pci_domain_scan_bus, |
| 134 | .ops_pci_bus = pci_bus_default_ops, |
Duncan Laurie | 02fcc88 | 2016-06-27 10:51:17 -0700 | [diff] [blame] | 135 | .acpi_name = &soc_acpi_name, |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 136 | }; |
| 137 | |
| 138 | static struct device_operations cpu_bus_ops = { |
| 139 | .read_resources = DEVICE_NOOP, |
| 140 | .set_resources = DEVICE_NOOP, |
| 141 | .enable_resources = DEVICE_NOOP, |
Aaron Durbin | ac3e482 | 2017-06-14 13:21:00 -0500 | [diff] [blame] | 142 | .init = apollolake_init_cpus, |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 143 | .scan_bus = NULL, |
Hannah Williams | 0f61da8 | 2016-04-18 13:47:08 -0700 | [diff] [blame] | 144 | .acpi_fill_ssdt_generator = generate_cpu_entries, |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 145 | }; |
| 146 | |
| 147 | static void enable_dev(device_t dev) |
| 148 | { |
| 149 | /* Set the operations if it is a special bus type */ |
Lee Leahy | 4430f9f | 2017-03-09 10:00:30 -0800 | [diff] [blame] | 150 | if (dev->path.type == DEVICE_PATH_DOMAIN) |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 151 | dev->ops = &pci_domain_ops; |
Lee Leahy | 4430f9f | 2017-03-09 10:00:30 -0800 | [diff] [blame] | 152 | else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 153 | dev->ops = &cpu_bus_ops; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 154 | } |
| 155 | |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 156 | /* |
| 157 | * If the PCIe root port at function 0 is disabled, |
| 158 | * the PCIe root ports might be coalesced after FSP silicon init. |
| 159 | * The below function will swap the devfn of the first enabled device |
| 160 | * in devicetree and function 0 resides a pci device |
| 161 | * so that it won't confuse coreboot. |
| 162 | */ |
| 163 | static void pcie_update_device_tree(unsigned int devfn0, int num_funcs) |
| 164 | { |
| 165 | device_t func0; |
| 166 | unsigned int devfn; |
| 167 | int i; |
| 168 | unsigned int inc = PCI_DEVFN(0, 1); |
| 169 | |
| 170 | func0 = dev_find_slot(0, devfn0); |
| 171 | if (func0 == NULL) |
| 172 | return; |
| 173 | |
| 174 | /* No more functions if function 0 is disabled. */ |
| 175 | if (pci_read_config32(func0, PCI_VENDOR_ID) == 0xffffffff) |
| 176 | return; |
| 177 | |
| 178 | devfn = devfn0 + inc; |
| 179 | |
| 180 | /* |
| 181 | * Increase funtion by 1. |
| 182 | * Then find first enabled device to replace func0 |
| 183 | * as that port was move to func0. |
| 184 | */ |
| 185 | for (i = 1; i < num_funcs; i++, devfn += inc) { |
| 186 | device_t dev = dev_find_slot(0, devfn); |
| 187 | if (dev == NULL) |
| 188 | continue; |
| 189 | |
| 190 | if (!dev->enabled) |
| 191 | continue; |
| 192 | /* Found the first enabled device in given dev number */ |
| 193 | func0->path.pci.devfn = dev->path.pci.devfn; |
| 194 | dev->path.pci.devfn = devfn0; |
| 195 | break; |
| 196 | } |
| 197 | } |
| 198 | |
| 199 | static void pcie_override_devicetree_after_silicon_init(void) |
| 200 | { |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 201 | pcie_update_device_tree(PCH_DEVFN_PCIE1, 4); |
| 202 | pcie_update_device_tree(PCH_DEVFN_PCIE5, 2); |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 203 | } |
| 204 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 205 | /* Configure package power limits */ |
| 206 | static void set_power_limits(void) |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 207 | { |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 208 | static struct soc_intel_apollolake_config *cfg; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 209 | struct device *dev = SA_DEV_ROOT; |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 210 | msr_t rapl_msr_reg, limit; |
| 211 | uint32_t power_unit; |
| 212 | uint32_t tdp, min_power, max_power; |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 213 | uint32_t pl2_val; |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 214 | |
Mario Scheithauer | 38b6100 | 2017-07-25 10:52:41 +0200 | [diff] [blame] | 215 | if (IS_ENABLED(CONFIG_APL_SKIP_SET_POWER_LIMITS)) { |
| 216 | printk(BIOS_INFO, "Skip the RAPL settings.\n"); |
| 217 | return; |
| 218 | } |
| 219 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 220 | if (!dev || !dev->chip_info) { |
| 221 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
| 222 | return; |
| 223 | } |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 224 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 225 | cfg = dev->chip_info; |
| 226 | |
| 227 | /* Get units */ |
| 228 | rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU_UNIT); |
| 229 | power_unit = 1 << (rapl_msr_reg.lo & 0xf); |
| 230 | |
| 231 | /* Get power defaults for this SKU */ |
| 232 | rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU); |
| 233 | tdp = rapl_msr_reg.lo & PKG_POWER_LIMIT_MASK; |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 234 | pl2_val = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK; |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 235 | min_power = (rapl_msr_reg.lo >> 16) & PKG_POWER_LIMIT_MASK; |
| 236 | max_power = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK; |
| 237 | |
| 238 | if (min_power > 0 && tdp < min_power) |
| 239 | tdp = min_power; |
| 240 | |
| 241 | if (max_power > 0 && tdp > max_power) |
| 242 | tdp = max_power; |
| 243 | |
| 244 | /* Set PL1 override value */ |
| 245 | tdp = (cfg->tdp_pl1_override_mw == 0) ? |
| 246 | tdp : (cfg->tdp_pl1_override_mw * power_unit) / 1000; |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 247 | /* Set PL2 override value */ |
| 248 | pl2_val = (cfg->tdp_pl2_override_mw == 0) ? |
| 249 | pl2_val : (cfg->tdp_pl2_override_mw * power_unit) / 1000; |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 250 | |
| 251 | /* Set long term power limit to TDP */ |
| 252 | limit.lo = tdp & PKG_POWER_LIMIT_MASK; |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 253 | /* Set PL1 Pkg Power clamp bit */ |
| 254 | limit.lo |= PKG_POWER_LIMIT_CLAMP; |
| 255 | |
| 256 | limit.lo |= PKG_POWER_LIMIT_EN; |
| 257 | limit.lo |= (MB_POWER_LIMIT1_TIME_DEFAULT & |
| 258 | PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT; |
| 259 | |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 260 | /* Set short term power limit PL2 */ |
| 261 | limit.hi = pl2_val & PKG_POWER_LIMIT_MASK; |
| 262 | limit.hi |= PKG_POWER_LIMIT_EN; |
| 263 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 264 | /* Program package power limits in RAPL MSR */ |
| 265 | wrmsr(MSR_PKG_POWER_LIMIT, limit); |
| 266 | printk(BIOS_INFO, "RAPL PL1 %d.%dW\n", tdp / power_unit, |
| 267 | 100 * (tdp % power_unit) / power_unit); |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 268 | printk(BIOS_INFO, "RAPL PL2 %d.%dW\n", pl2_val / power_unit, |
| 269 | 100 * (pl2_val % power_unit) / power_unit); |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 270 | |
Sumeet Pawnikar | 428f90a | 2016-12-02 18:14:19 +0530 | [diff] [blame] | 271 | /* Setting RAPL MMIO register for Power limits. |
| 272 | * RAPL driver is using MSR instead of MMIO. |
| 273 | * So, disabled LIMIT_EN bit for MMIO. */ |
Subrata Banik | 208587e | 2017-05-19 18:38:24 +0530 | [diff] [blame] | 274 | MCHBAR32(MCHBAR_RAPL_PPL) = limit.lo & ~PKG_POWER_LIMIT_EN; |
| 275 | MCHBAR32(MCHBAR_RAPL_PPL + 4) = limit.hi & ~PKG_POWER_LIMIT_EN; |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 276 | } |
| 277 | |
Mario Scheithauer | 841416f | 2017-09-18 17:08:48 +0200 | [diff] [blame] | 278 | /* Overwrites the SCI IRQ if another IRQ number is given by device tree. */ |
| 279 | static void set_sci_irq(void) |
| 280 | { |
| 281 | static struct soc_intel_apollolake_config *cfg; |
| 282 | struct device *dev = SA_DEV_ROOT; |
| 283 | uint32_t scis; |
| 284 | |
| 285 | if (!dev || !dev->chip_info) { |
| 286 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
| 287 | return; |
| 288 | } |
| 289 | |
| 290 | cfg = dev->chip_info; |
| 291 | |
| 292 | /* Change only if a device tree entry exists. */ |
| 293 | if (cfg->sci_irq) { |
| 294 | scis = soc_read_sci_irq_select(); |
| 295 | scis &= ~SCI_IRQ_SEL; |
| 296 | scis |= (cfg->sci_irq << SCI_IRQ_ADJUST) & SCI_IRQ_SEL; |
| 297 | soc_write_sci_irq_select(scis); |
| 298 | } |
| 299 | } |
| 300 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 301 | static void soc_init(void *data) |
| 302 | { |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 303 | struct global_nvs_t *gnvs; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 304 | |
Aaron Durbin | 81d1e09 | 2016-07-13 01:49:10 -0500 | [diff] [blame] | 305 | /* Snapshot the current GPIO IRQ polarities. FSP is setting a |
| 306 | * default policy that doesn't honor boards' requirements. */ |
| 307 | itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); |
| 308 | |
Aaron Durbin | 6c191d8 | 2016-11-29 21:22:42 -0600 | [diff] [blame] | 309 | fsp_silicon_init(romstage_handoff_is_resume()); |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 310 | |
Aaron Durbin | 81d1e09 | 2016-07-13 01:49:10 -0500 | [diff] [blame] | 311 | /* Restore GPIO IRQ polarities back to previous settings. */ |
| 312 | itss_restore_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); |
| 313 | |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 314 | /* override 'enabled' setting in device tree if needed */ |
| 315 | pcie_override_devicetree_after_silicon_init(); |
| 316 | |
Aaron Durbin | fadfc2e | 2016-07-01 16:36:03 -0500 | [diff] [blame] | 317 | /* |
| 318 | * Keep the P2SB device visible so it and the other devices are |
| 319 | * visible in coreboot for driver support and PCI resource allocation. |
| 320 | * There is a UPD setting for this, but it's more consistent to use |
| 321 | * hide and unhide symmetrically. |
| 322 | */ |
| 323 | p2sb_unhide(); |
| 324 | |
Lance Zhao | 1bd0c0c | 2016-04-19 18:04:21 -0700 | [diff] [blame] | 325 | /* Allocate ACPI NVS in CBMEM */ |
| 326 | gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); |
Sumeet Pawnikar | 35240eb | 2016-08-23 11:20:20 +0530 | [diff] [blame] | 327 | |
Sumeet Pawnikar | a247d8e | 2016-09-27 23:18:35 +0530 | [diff] [blame] | 328 | /* Set RAPL MSR for Package power limits*/ |
| 329 | set_power_limits(); |
Mario Scheithauer | 841416f | 2017-09-18 17:08:48 +0200 | [diff] [blame] | 330 | |
| 331 | /* |
| 332 | * FSP-S routes SCI to IRQ 9. With the help of this function you can |
| 333 | * select another IRQ for SCI. |
| 334 | */ |
| 335 | set_sci_irq(); |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 336 | } |
| 337 | |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 338 | static void soc_final(void *data) |
| 339 | { |
Andrey Petrov | 3dbea29 | 2016-06-14 22:20:28 -0700 | [diff] [blame] | 340 | /* Disable global reset, just in case */ |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 341 | pmc_global_reset_enable(0); |
Andrey Petrov | 3dbea29 | 2016-06-14 22:20:28 -0700 | [diff] [blame] | 342 | /* Make sure payload/OS can't trigger global reset */ |
Shaunak Saha | 93cdc8b | 2017-04-18 15:42:09 -0700 | [diff] [blame] | 343 | pmc_global_reset_lock(); |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 344 | } |
| 345 | |
Lee Leahy | bab8be2 | 2017-03-09 09:53:58 -0800 | [diff] [blame] | 346 | static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig) |
| 347 | { |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 348 | switch (dev->path.pci.devfn) { |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 349 | case PCH_DEVFN_ISH: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 350 | silconfig->IshEnable = 0; |
| 351 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 352 | case PCH_DEVFN_SATA: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 353 | silconfig->EnableSata = 0; |
| 354 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 355 | case PCH_DEVFN_PCIE5: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 356 | silconfig->PcieRootPortEn[0] = 0; |
| 357 | silconfig->PcieRpHotPlug[0] = 0; |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 358 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 359 | case PCH_DEVFN_PCIE6: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 360 | silconfig->PcieRootPortEn[1] = 0; |
| 361 | silconfig->PcieRpHotPlug[1] = 0; |
| 362 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 363 | case PCH_DEVFN_PCIE1: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 364 | silconfig->PcieRootPortEn[2] = 0; |
| 365 | silconfig->PcieRpHotPlug[2] = 0; |
| 366 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 367 | case PCH_DEVFN_PCIE2: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 368 | silconfig->PcieRootPortEn[3] = 0; |
| 369 | silconfig->PcieRpHotPlug[3] = 0; |
| 370 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 371 | case PCH_DEVFN_PCIE3: |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 372 | silconfig->PcieRootPortEn[4] = 0; |
| 373 | silconfig->PcieRpHotPlug[4] = 0; |
| 374 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 375 | case PCH_DEVFN_PCIE4: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 376 | silconfig->PcieRootPortEn[5] = 0; |
Kane Chen | d779605 | 2016-07-11 12:17:13 +0800 | [diff] [blame] | 377 | silconfig->PcieRpHotPlug[5] = 0; |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 378 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 379 | case PCH_DEVFN_XHCI: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 380 | silconfig->Usb30Mode = 0; |
| 381 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 382 | case PCH_DEVFN_XDCI: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 383 | silconfig->UsbOtg = 0; |
| 384 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 385 | case PCH_DEVFN_I2C0: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 386 | silconfig->I2c0Enable = 0; |
| 387 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 388 | case PCH_DEVFN_I2C1: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 389 | silconfig->I2c1Enable = 0; |
| 390 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 391 | case PCH_DEVFN_I2C2: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 392 | silconfig->I2c2Enable = 0; |
| 393 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 394 | case PCH_DEVFN_I2C3: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 395 | silconfig->I2c3Enable = 0; |
| 396 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 397 | case PCH_DEVFN_I2C4: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 398 | silconfig->I2c4Enable = 0; |
| 399 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 400 | case PCH_DEVFN_I2C5: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 401 | silconfig->I2c5Enable = 0; |
| 402 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 403 | case PCH_DEVFN_I2C6: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 404 | silconfig->I2c6Enable = 0; |
| 405 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 406 | case PCH_DEVFN_I2C7: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 407 | silconfig->I2c7Enable = 0; |
| 408 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 409 | case PCH_DEVFN_UART0: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 410 | silconfig->Hsuart0Enable = 0; |
| 411 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 412 | case PCH_DEVFN_UART1: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 413 | silconfig->Hsuart1Enable = 0; |
| 414 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 415 | case PCH_DEVFN_UART2: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 416 | silconfig->Hsuart2Enable = 0; |
| 417 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 418 | case PCH_DEVFN_UART3: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 419 | silconfig->Hsuart3Enable = 0; |
| 420 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 421 | case PCH_DEVFN_SPI0: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 422 | silconfig->Spi0Enable = 0; |
| 423 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 424 | case PCH_DEVFN_SPI1: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 425 | silconfig->Spi1Enable = 0; |
| 426 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 427 | case PCH_DEVFN_SPI2: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 428 | silconfig->Spi2Enable = 0; |
| 429 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 430 | case PCH_DEVFN_SDCARD: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 431 | silconfig->SdcardEnabled = 0; |
| 432 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 433 | case PCH_DEVFN_EMMC: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 434 | silconfig->eMMCEnabled = 0; |
| 435 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 436 | case PCH_DEVFN_SDIO: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 437 | silconfig->SdioEnabled = 0; |
| 438 | break; |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 439 | case PCH_DEVFN_SMBUS: |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 440 | silconfig->SmbusEnable = 0; |
| 441 | break; |
| 442 | default: |
| 443 | printk(BIOS_WARNING, "PCI:%02x.%01x: Could not disable the device\n", |
| 444 | PCI_SLOT(dev->path.pci.devfn), |
| 445 | PCI_FUNC(dev->path.pci.devfn)); |
| 446 | break; |
| 447 | } |
| 448 | } |
| 449 | |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 450 | static void parse_devicetree(FSP_S_CONFIG *silconfig) |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 451 | { |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 452 | struct device *dev = SA_DEV_ROOT; |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 453 | |
| 454 | if (!dev) { |
| 455 | printk(BIOS_ERR, "Could not find root device\n"); |
| 456 | return; |
| 457 | } |
| 458 | /* Only disable bus 0 devices. */ |
| 459 | for (dev = dev->bus->children; dev; dev = dev->sibling) { |
| 460 | if (!dev->enabled) |
| 461 | disable_dev(dev, silconfig); |
| 462 | } |
| 463 | } |
| 464 | |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 465 | static void apl_fsp_silicon_init_params_cb(struct soc_intel_apollolake_config |
| 466 | *cfg, FSP_S_CONFIG *silconfig) |
| 467 | { |
| 468 | #if !IS_ENABLED(CONFIG_SOC_INTEL_GLK) /* GLK FSP does not have these |
| 469 | fields in FspsUpd.h yet */ |
| 470 | uint8_t port; |
| 471 | |
| 472 | for (port = 0; port < APOLLOLAKE_USB2_PORT_MAX; port++) { |
| 473 | if (cfg->usb2eye[port].Usb20PerPortTxPeHalf != 0) |
| 474 | silconfig->PortUsb20PerPortTxPeHalf[port] = |
| 475 | cfg->usb2eye[port].Usb20PerPortTxPeHalf; |
| 476 | |
| 477 | if (cfg->usb2eye[port].Usb20PerPortPeTxiSet != 0) |
| 478 | silconfig->PortUsb20PerPortPeTxiSet[port] = |
| 479 | cfg->usb2eye[port].Usb20PerPortPeTxiSet; |
| 480 | |
| 481 | if (cfg->usb2eye[port].Usb20PerPortTxiSet != 0) |
| 482 | silconfig->PortUsb20PerPortTxiSet[port] = |
| 483 | cfg->usb2eye[port].Usb20PerPortTxiSet; |
| 484 | |
| 485 | if (cfg->usb2eye[port].Usb20HsSkewSel != 0) |
| 486 | silconfig->PortUsb20HsSkewSel[port] = |
| 487 | cfg->usb2eye[port].Usb20HsSkewSel; |
| 488 | |
| 489 | if (cfg->usb2eye[port].Usb20IUsbTxEmphasisEn != 0) |
| 490 | silconfig->PortUsb20IUsbTxEmphasisEn[port] = |
| 491 | cfg->usb2eye[port].Usb20IUsbTxEmphasisEn; |
| 492 | |
| 493 | if (cfg->usb2eye[port].Usb20PerPortRXISet != 0) |
| 494 | silconfig->PortUsb20PerPortRXISet[port] = |
| 495 | cfg->usb2eye[port].Usb20PerPortRXISet; |
| 496 | |
| 497 | if (cfg->usb2eye[port].Usb20HsNpreDrvSel != 0) |
| 498 | silconfig->PortUsb20HsNpreDrvSel[port] = |
| 499 | cfg->usb2eye[port].Usb20HsNpreDrvSel; |
| 500 | } |
| 501 | #endif |
| 502 | } |
| 503 | |
| 504 | static void glk_fsp_silicon_init_params_cb( |
| 505 | struct soc_intel_apollolake_config *cfg, FSP_S_CONFIG *silconfig) |
| 506 | { |
| 507 | silconfig->Gmm = 0; |
Shamile Khan | c4276a3 | 2018-03-14 18:09:19 -0700 | [diff] [blame] | 508 | |
| 509 | /* On Geminilake, we need to override the default FSP PCIe de-emphasis |
| 510 | * settings using the device tree settings. This is because PCIe |
| 511 | * de-emphasis is enabled by default and Thunderpeak PCIe WiFi detection |
| 512 | * requires de-emphasis disabled. If we make this change common to both |
| 513 | * Apollolake and Geminilake, then we need to add mainboard device tree |
| 514 | * de-emphasis settings of 1 to Apollolake systems. |
| 515 | */ |
| 516 | memcpy(silconfig->PcieRpSelectableDeemphasis, |
| 517 | cfg->pcie_rp_deemphasis_enable, |
| 518 | sizeof(silconfig->PcieRpSelectableDeemphasis)); |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 519 | } |
| 520 | |
Kane Chen | 5bddcc4 | 2017-08-22 11:37:18 +0800 | [diff] [blame] | 521 | void __attribute__((weak)) mainboard_devtree_update(struct device *dev) |
| 522 | { |
| 523 | /* Override dev tree settings per board */ |
| 524 | } |
| 525 | |
Brandon Breitenstein | c31ba0e | 2016-07-27 17:34:45 -0700 | [diff] [blame] | 526 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 527 | { |
Lee Leahy | 1d20fe7 | 2017-03-09 09:50:28 -0800 | [diff] [blame] | 528 | FSP_S_CONFIG *silconfig = &silupd->FspsConfig; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 529 | static struct soc_intel_apollolake_config *cfg; |
| 530 | |
| 531 | /* Load VBT before devicetree-specific config. */ |
Patrick Georgi | 2257959 | 2017-10-06 17:36:09 +0200 | [diff] [blame] | 532 | silconfig->GraphicsConfigPtr = (uintptr_t)vbt_get(); |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 533 | |
Subrata Banik | 2ee54db | 2017-03-05 12:37:00 +0530 | [diff] [blame] | 534 | struct device *dev = SA_DEV_ROOT; |
Andrey Petrov | 78461a9 | 2016-06-28 12:14:33 -0700 | [diff] [blame] | 535 | |
Patrick Georgi | 831d65d | 2016-04-14 11:53:48 +0200 | [diff] [blame] | 536 | if (!dev || !dev->chip_info) { |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 537 | printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); |
| 538 | return; |
| 539 | } |
| 540 | |
Kane Chen | 5bddcc4 | 2017-08-22 11:37:18 +0800 | [diff] [blame] | 541 | mainboard_devtree_update(dev); |
| 542 | |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 543 | cfg = dev->chip_info; |
| 544 | |
Jagadish Krishnamoorthy | b023e5e | 2016-06-22 18:32:17 -0700 | [diff] [blame] | 545 | /* Parse device tree and disable unused device*/ |
| 546 | parse_devicetree(silconfig); |
| 547 | |
Furquan Shaikh | 6d5e10c | 2018-03-14 19:57:16 -0700 | [diff] [blame] | 548 | memcpy(silconfig->PcieRpClkReqNumber, cfg->pcie_rp_clkreq_pin, |
| 549 | sizeof(silconfig->PcieRpClkReqNumber)); |
Andrey Petrov | e07e13d | 2016-03-18 14:43:00 -0700 | [diff] [blame] | 550 | |
Furquan Shaikh | 2cfc862 | 2018-03-14 21:43:04 -0700 | [diff] [blame] | 551 | memcpy(silconfig->PcieRpHotPlug, cfg->pcie_rp_hotplug_enable, |
| 552 | sizeof(silconfig->PcieRpHotPlug)); |
| 553 | |
Zhao, Lijian | 1b8ee0b | 2016-05-17 19:01:34 -0700 | [diff] [blame] | 554 | if (cfg->emmc_tx_cmd_cntl != 0) |
| 555 | silconfig->EmmcTxCmdCntl = cfg->emmc_tx_cmd_cntl; |
| 556 | if (cfg->emmc_tx_data_cntl1 != 0) |
| 557 | silconfig->EmmcTxDataCntl1 = cfg->emmc_tx_data_cntl1; |
| 558 | if (cfg->emmc_tx_data_cntl2 != 0) |
| 559 | silconfig->EmmcTxDataCntl2 = cfg->emmc_tx_data_cntl2; |
| 560 | if (cfg->emmc_rx_cmd_data_cntl1 != 0) |
| 561 | silconfig->EmmcRxCmdDataCntl1 = cfg->emmc_rx_cmd_data_cntl1; |
| 562 | if (cfg->emmc_rx_strobe_cntl != 0) |
| 563 | silconfig->EmmcRxStrobeCntl = cfg->emmc_rx_strobe_cntl; |
| 564 | if (cfg->emmc_rx_cmd_data_cntl2 != 0) |
| 565 | silconfig->EmmcRxCmdDataCntl2 = cfg->emmc_rx_cmd_data_cntl2; |
| 566 | |
Saurabh Satija | e46dbcc | 2016-05-03 15:15:31 -0700 | [diff] [blame] | 567 | silconfig->LPSS_S0ixEnable = cfg->lpss_s0ix_enable; |
| 568 | |
Lee Leahy | 07441b5 | 2017-03-09 10:59:25 -0800 | [diff] [blame] | 569 | /* Disable monitor mwait since it is broken due to a hardware bug |
Cole Nelson | f357c25 | 2017-05-16 11:38:59 -0700 | [diff] [blame] | 570 | * without a fix. Specific to Apollolake. |
Lee Leahy | 07441b5 | 2017-03-09 10:59:25 -0800 | [diff] [blame] | 571 | */ |
Cole Nelson | f357c25 | 2017-05-16 11:38:59 -0700 | [diff] [blame] | 572 | if (!IS_ENABLED(CONFIG_SOC_INTEL_GLK)) |
| 573 | silconfig->MonitorMwaitEnable = 0; |
Bora Guvendik | 60cc75d | 2016-07-25 14:44:51 -0700 | [diff] [blame] | 574 | |
Venkateswarlu Vinjamuri | 1a5e32c | 2016-10-31 17:15:30 -0700 | [diff] [blame] | 575 | silconfig->SkipMpInit = 1; |
| 576 | |
Furquan Shaikh | cad9b63 | 2016-06-20 16:08:42 -0700 | [diff] [blame] | 577 | /* Disable setting of EISS bit in FSP. */ |
| 578 | silconfig->SpiEiss = 0; |
Ravi Sarawadi | 3a21d0f | 2016-08-10 11:33:56 -0700 | [diff] [blame] | 579 | |
| 580 | /* Disable FSP from locking access to the RTC NVRAM */ |
| 581 | silconfig->RtcLock = 0; |
Venkateswarlu Vinjamuri | 88df48c | 2016-09-02 16:04:27 -0700 | [diff] [blame] | 582 | |
| 583 | /* Enable Audio clk gate and power gate */ |
| 584 | silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; |
| 585 | silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; |
| 586 | /* Bios config lockdown Audio clk and power gate */ |
| 587 | silconfig->BiosCfgLockDown = cfg->hdaudio_bios_config_lockdown; |
Hannah Williams | 3ff14a0 | 2017-05-05 16:30:22 -0700 | [diff] [blame] | 588 | if (IS_ENABLED(CONFIG_SOC_INTEL_GLK)) |
| 589 | glk_fsp_silicon_init_params_cb(cfg, silconfig); |
| 590 | else |
| 591 | apl_fsp_silicon_init_params_cb(cfg, silconfig); |
Duncan Laurie | 4c8fbc0 | 2018-03-26 02:19:58 -0700 | [diff] [blame] | 592 | |
| 593 | /* Enable xDCI controller if enabled in devicetree and allowed */ |
| 594 | dev = dev_find_slot(0, PCH_DEVFN_XDCI); |
| 595 | if (!xdci_can_enable()) |
| 596 | dev->enabled = 0; |
| 597 | silconfig->UsbOtg = dev->enabled; |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 598 | } |
| 599 | |
| 600 | struct chip_operations soc_intel_apollolake_ops = { |
| 601 | CHIP_NAME("Intel Apollolake SOC") |
| 602 | .enable_dev = &enable_dev, |
Andrey Petrov | 868679f | 2016-05-12 19:11:48 -0700 | [diff] [blame] | 603 | .init = &soc_init, |
| 604 | .final = &soc_final |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 605 | }; |
| 606 | |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 607 | static void drop_privilege_all(void) |
| 608 | { |
| 609 | /* Drop privilege level on all the CPUs */ |
Barnali Sarkar | 66fe0c4 | 2017-05-23 18:17:14 +0530 | [diff] [blame] | 610 | if (mp_run_on_all_cpus(&cpu_enable_untrusted_mode, 1000) < 0) |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 611 | printk(BIOS_ERR, "failed to enable untrusted mode\n"); |
| 612 | } |
| 613 | |
Lee Leahy | 806fa24 | 2016-08-01 13:55:02 -0700 | [diff] [blame] | 614 | void platform_fsp_notify_status(enum fsp_notify_phase phase) |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 615 | { |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 616 | if (phase == END_OF_FIRMWARE) { |
| 617 | /* Hide the P2SB device to align with previous behavior. */ |
Aaron Durbin | fadfc2e | 2016-07-01 16:36:03 -0500 | [diff] [blame] | 618 | p2sb_hide(); |
Andrey Petrov | a697c19 | 2016-12-07 10:47:46 -0800 | [diff] [blame] | 619 | /* |
| 620 | * As per guidelines BIOS is recommended to drop CPU privilege |
| 621 | * level to IA_UNTRUSTED. After that certain device registers |
| 622 | * and MSRs become inaccessible supposedly increasing system |
| 623 | * security. |
| 624 | */ |
| 625 | drop_privilege_all(); |
| 626 | } |
Andrey Petrov | 70efecd | 2016-03-04 21:41:13 -0800 | [diff] [blame] | 627 | } |
| 628 | |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 629 | /* |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 630 | * spi_flash init() needs to run unconditionally on every boot (including |
| 631 | * resume) to allow write protect to be disabled for eventlog and nvram |
| 632 | * updates. This needs to be done as early as possible in ramstage. Thus, add a |
| 633 | * callback for entry into BS_PRE_DEVICE. |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 634 | */ |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 635 | static void spi_flash_init_cb(void *unused) |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 636 | { |
Barnali Sarkar | e70142c | 2017-03-28 16:32:33 +0530 | [diff] [blame] | 637 | fast_spi_init(); |
Furquan Shaikh | 6ac226d | 2016-06-15 17:13:20 -0700 | [diff] [blame] | 638 | } |
| 639 | |
Furquan Shaikh | d6c5559 | 2016-11-21 12:41:20 -0800 | [diff] [blame] | 640 | BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL); |