Noah Glovsky | abe40e0 | 2016-04-19 14:55:38 -0600 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License as published by |
| 6 | * the Free Software Foundation; version 2 of the License. |
| 7 | * |
| 8 | * This program is distributed in the hope that it will be useful, |
| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 11 | * GNU General Public License for more details. |
| 12 | */ |
| 13 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 14 | #include <stdint.h> |
Patrick Georgi | 12aba82 | 2009-04-30 07:07:22 +0000 | [diff] [blame] | 15 | #include <string.h> |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 16 | #include <device/pci_def.h> |
| 17 | #include <device/pci_ids.h> |
| 18 | #include <arch/io.h> |
| 19 | #include <device/pnp_def.h> |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 20 | #include <pc80/mc146818rtc.h> |
Patrick Georgi | 12584e2 | 2010-05-08 09:14:51 +0000 | [diff] [blame] | 21 | #include <console/console.h> |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 22 | #include <cpu/amd/model_fxx_rev.h> |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 23 | #include "southbridge/amd/amd8111/early_smbus.c" |
Stefan Reinauer | 8f2c616 | 2010-04-06 21:50:21 +0000 | [diff] [blame] | 24 | #include <reset.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 25 | #include <northbridge/amd/amdk8/raminit.h> |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 26 | #include "northbridge/amd/amdk8/reset_test.c" |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 27 | #include <cpu/x86/bist.h> |
Edward O'Callaghan | ebe3a7a | 2015-01-05 00:27:54 +1100 | [diff] [blame] | 28 | #include <delay.h> |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 29 | #include "northbridge/amd/amdk8/debug.c" |
Stefan Reinauer | 8f2c616 | 2010-04-06 21:50:21 +0000 | [diff] [blame] | 30 | #include <cpu/amd/mtrr.h> |
Edward O'Callaghan | 8199809 | 2014-04-28 18:07:33 +1000 | [diff] [blame] | 31 | #include <superio/winbond/common/winbond.h> |
| 32 | #include <superio/winbond/w83627hf/w83627hf.h> |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 33 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 34 | #include "southbridge/amd/amd8111/early_ctrl.c" |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 35 | |
| 36 | #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) |
| 37 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 38 | static void memreset_setup(void) |
| 39 | { |
| 40 | //GPIO on amd8111 to enable MEMRST ???? |
Elyes HAOUAS | 6350a2e | 2016-09-16 20:49:38 +0200 | [diff] [blame^] | 41 | outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN = 1 |
| 42 | outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 43 | } |
| 44 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 45 | static void memreset(int controllers, const struct mem_controller *ctrl) { } |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 46 | |
| 47 | static inline void activate_spd_rom(const struct mem_controller *ctrl) |
| 48 | { |
| 49 | #define SMBUS_HUB 0x18 |
| 50 | int ret,i; |
| 51 | unsigned device=(ctrl->channel0[0])>>8; |
Elyes HAOUAS | 6350a2e | 2016-09-16 20:49:38 +0200 | [diff] [blame^] | 52 | /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/ |
| 53 | i = 2; |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 54 | do { |
| 55 | ret = smbus_write_byte(SMBUS_HUB, 0x01, device); |
Elyes HAOUAS | 6350a2e | 2016-09-16 20:49:38 +0200 | [diff] [blame^] | 56 | } while ((ret != 0) && (i-->0)); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 57 | |
| 58 | smbus_write_byte(SMBUS_HUB, 0x03, 0); |
| 59 | } |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 60 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 61 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 62 | { |
| 63 | return smbus_read_byte(device, address); |
| 64 | } |
| 65 | |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 66 | #include <northbridge/amd/amdk8/amdk8.h> |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 67 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
Stefan Reinauer | 23836e2 | 2010-04-15 12:39:29 +0000 | [diff] [blame] | 68 | #include "northbridge/amd/amdk8/coherent_ht.c" |
Myles Watson | 1725703 | 2009-06-04 20:18:42 +0000 | [diff] [blame] | 69 | #include "northbridge/amd/amdk8/raminit_f.c" |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 70 | #include "lib/generic_sdram.c" |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 71 | #include "resourcemap.c" |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 72 | #include "cpu/amd/dualcore/dualcore.c" |
Patrick Georgi | 9bd9a90 | 2010-11-20 10:31:00 +0000 | [diff] [blame] | 73 | #include <spd.h> |
Uwe Hermann | 57b2ff8 | 2010-11-21 17:29:59 +0000 | [diff] [blame] | 74 | #include "cpu/amd/model_fxx/init_cpus.c" |
| 75 | #include "cpu/amd/model_fxx/fidvid.c" |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 76 | |
Elyes HAOUAS | 6350a2e | 2016-09-16 20:49:38 +0200 | [diff] [blame^] | 77 | #define RC0 ((1 << 0)<<8) |
| 78 | #define RC1 ((1 << 1)<<8) |
| 79 | #define RC2 ((1 << 2)<<8) |
| 80 | #define RC3 ((1 << 3)<<8) |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 81 | |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 82 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 83 | { |
| 84 | static const uint16_t spd_addr[] = { |
| 85 | //first node |
| 86 | RC0|DIMM0, RC0|DIMM2, 0, 0, |
| 87 | RC0|DIMM1, RC0|DIMM3, 0, 0, |
| 88 | #if CONFIG_MAX_PHYSICAL_CPUS > 1 |
| 89 | //second node |
| 90 | RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, |
| 91 | RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, |
| 92 | #endif |
| 93 | #if CONFIG_MAX_PHYSICAL_CPUS > 2 |
| 94 | // third node |
| 95 | RC2|DIMM0, RC2|DIMM2, 0, 0, |
| 96 | RC2|DIMM1, RC2|DIMM3, 0, 0, |
| 97 | // four node |
| 98 | RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6, |
| 99 | RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7, |
| 100 | #endif |
| 101 | |
| 102 | }; |
| 103 | |
Patrick Georgi | bbc880e | 2012-11-20 18:20:56 +0100 | [diff] [blame] | 104 | struct sys_info *sysinfo = &sysinfo_car; |
Myles Watson | 6e23576 | 2009-09-29 14:56:15 +0000 | [diff] [blame] | 105 | int needs_reset; |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 106 | unsigned bsp_apicid = 0; |
Patrick Georgi | 76e8152 | 2010-11-16 21:25:29 +0000 | [diff] [blame] | 107 | #if CONFIG_SET_FIDVID |
Dan Lykowski | 6ef8e0f | 2009-01-12 16:16:08 +0000 | [diff] [blame] | 108 | struct cpuid_result cpuid1; |
Myles Watson | 6e23576 | 2009-09-29 14:56:15 +0000 | [diff] [blame] | 109 | #endif |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 110 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 111 | if (bist == 0) |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 112 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 113 | |
Edward O'Callaghan | 8199809 | 2014-04-28 18:07:33 +1000 | [diff] [blame] | 114 | winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
| 115 | console_init(); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 116 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 117 | // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 118 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 119 | /* Halt if there was a built in self test failure */ |
| 120 | report_bist_failure(bist); |
| 121 | |
Myles Watson | 08e0fb8 | 2010-03-22 16:33:25 +0000 | [diff] [blame] | 122 | printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 123 | |
Yinghai Lu | 5f9624d | 2006-10-04 22:56:21 +0000 | [diff] [blame] | 124 | setup_mb_resource_map(); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 125 | #if 0 |
| 126 | dump_pci_device(PCI_DEV(0, 0x18, 0)); |
| 127 | dump_pci_device(PCI_DEV(0, 0x19, 0)); |
| 128 | #endif |
| 129 | |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 130 | printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 131 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 132 | set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 133 | setup_coherent_ht_domain(); // routing table and start other core0 |
| 134 | |
| 135 | wait_all_core0_started(); |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 136 | #if CONFIG_LOGICAL_CPUS |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 137 | // It is said that we should start core1 after all core0 launched |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 138 | /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 139 | * So here need to make sure last core0 is started, esp for two way system, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 140 | * (there may be apic id conflicts in that case) |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 141 | */ |
| 142 | start_other_cores(); |
| 143 | wait_all_other_cores_started(bsp_apicid); |
| 144 | #endif |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 145 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 146 | /* it will set up chains and store link pair for optimization later */ |
| 147 | ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn |
| 148 | |
| 149 | #if 0 |
| 150 | //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. |
| 151 | needs_reset = optimize_link_coherent_ht(); |
| 152 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 153 | #endif |
| 154 | |
Patrick Georgi | 76e8152 | 2010-11-16 21:25:29 +0000 | [diff] [blame] | 155 | #if CONFIG_SET_FIDVID |
Dan Lykowski | 6ef8e0f | 2009-01-12 16:16:08 +0000 | [diff] [blame] | 156 | /* Check to see if processor is capable of changing FIDVID */ |
| 157 | /* otherwise it will throw a GP# when reading FIDVID_STATUS */ |
| 158 | cpuid1 = cpuid(0x80000007); |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 159 | if ((cpuid1.edx & 0x6) == 0x6) { |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 160 | |
| 161 | { |
Dan Lykowski | 6ef8e0f | 2009-01-12 16:16:08 +0000 | [diff] [blame] | 162 | /* Read FIDVID_STATUS */ |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 163 | msr_t msr; |
Elyes HAOUAS | 6350a2e | 2016-09-16 20:49:38 +0200 | [diff] [blame^] | 164 | msr = rdmsr(0xc0010042); |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 165 | printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 166 | } |
| 167 | |
| 168 | enable_fid_change(); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 169 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 170 | init_fidvid_bsp(bsp_apicid); |
| 171 | |
| 172 | // show final fid and vid |
| 173 | { |
| 174 | msr_t msr; |
Elyes HAOUAS | 6350a2e | 2016-09-16 20:49:38 +0200 | [diff] [blame^] | 175 | msr = rdmsr(0xc0010042); |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 176 | printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 177 | } |
Dan Lykowski | 6ef8e0f | 2009-01-12 16:16:08 +0000 | [diff] [blame] | 178 | |
| 179 | } else { |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 180 | printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); |
Dan Lykowski | 6ef8e0f | 2009-01-12 16:16:08 +0000 | [diff] [blame] | 181 | } |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 182 | #endif |
| 183 | |
| 184 | #if 1 |
| 185 | needs_reset = optimize_link_coherent_ht(); |
| 186 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 187 | |
| 188 | // fidvid change will issue one LDTSTOP and the HT change will be effective too |
| 189 | if (needs_reset) { |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame] | 190 | printk(BIOS_INFO, "ht reset -\n"); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 191 | soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); |
| 192 | } |
| 193 | #endif |
| 194 | allow_all_aps_stop(bsp_apicid); |
| 195 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 196 | //It's the time to set ctrl in sysinfo now; |
| 197 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 198 | |
| 199 | enable_smbus(); |
| 200 | |
| 201 | #if 0 |
Myles Watson | 6e23576 | 2009-09-29 14:56:15 +0000 | [diff] [blame] | 202 | int i; |
Elyes HAOUAS | 6350a2e | 2016-09-16 20:49:38 +0200 | [diff] [blame^] | 203 | for(i = 0; i < 4; i++) { |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 204 | activate_spd_rom(&cpu[i]); |
| 205 | dump_smbus_registers(); |
| 206 | } |
| 207 | #endif |
| 208 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 209 | memreset_setup(); |
| 210 | |
| 211 | //do we need apci timer, tsc...., only debug need it for better output |
| 212 | /* all ap stopped? */ |
Paul Menzel | 4549e5a | 2014-02-02 22:05:48 +0100 | [diff] [blame] | 213 | // init_timer(); // Need to use TMICT to synchronize FID/VID |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 214 | |
| 215 | sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); |
| 216 | |
| 217 | #if 0 |
| 218 | print_pci_devices(); |
| 219 | #endif |
| 220 | |
| 221 | #if 0 |
| 222 | // dump_pci_devices(); |
| 223 | dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); |
| 224 | dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); |
| 225 | #endif |
| 226 | |
Elyes HAOUAS | 8ab989e | 2016-07-30 17:46:17 +0200 | [diff] [blame] | 227 | post_cache_as_ram(); // bsp swtich stack to RAM and copy sysinfo RAM now |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 228 | } |