Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 1 | #include <stdint.h> |
Patrick Georgi | 12aba82 | 2009-04-30 07:07:22 +0000 | [diff] [blame] | 2 | #include <string.h> |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 3 | #include <device/pci_def.h> |
| 4 | #include <device/pci_ids.h> |
| 5 | #include <arch/io.h> |
| 6 | #include <device/pnp_def.h> |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 7 | #include <pc80/mc146818rtc.h> |
Patrick Georgi | 12584e2 | 2010-05-08 09:14:51 +0000 | [diff] [blame] | 8 | #include <console/console.h> |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 9 | #include <cpu/amd/model_fxx_rev.h> |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 10 | #include "southbridge/amd/amd8111/early_smbus.c" |
Stefan Reinauer | 8f2c616 | 2010-04-06 21:50:21 +0000 | [diff] [blame] | 11 | #include <reset.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 12 | #include <northbridge/amd/amdk8/raminit.h> |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 13 | #include "northbridge/amd/amdk8/reset_test.c" |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 14 | #include <cpu/x86/bist.h> |
Edward O'Callaghan | ebe3a7a | 2015-01-05 00:27:54 +1100 | [diff] [blame] | 15 | #include <delay.h> |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 16 | #include "northbridge/amd/amdk8/debug.c" |
Stefan Reinauer | 8f2c616 | 2010-04-06 21:50:21 +0000 | [diff] [blame] | 17 | #include <cpu/amd/mtrr.h> |
Edward O'Callaghan | 8199809 | 2014-04-28 18:07:33 +1000 | [diff] [blame] | 18 | #include <superio/winbond/common/winbond.h> |
| 19 | #include <superio/winbond/w83627hf/w83627hf.h> |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 20 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
stepan | 836ae29 | 2010-12-08 05:42:47 +0000 | [diff] [blame] | 21 | #include "southbridge/amd/amd8111/early_ctrl.c" |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 22 | |
| 23 | #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) |
| 24 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 25 | static void memreset_setup(void) |
| 26 | { |
| 27 | //GPIO on amd8111 to enable MEMRST ???? |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 28 | outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 |
| 29 | outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 30 | } |
| 31 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 32 | static void memreset(int controllers, const struct mem_controller *ctrl) { } |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 33 | |
| 34 | static inline void activate_spd_rom(const struct mem_controller *ctrl) |
| 35 | { |
| 36 | #define SMBUS_HUB 0x18 |
| 37 | int ret,i; |
| 38 | unsigned device=(ctrl->channel0[0])>>8; |
| 39 | /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ |
| 40 | i=2; |
| 41 | do { |
| 42 | ret = smbus_write_byte(SMBUS_HUB, 0x01, device); |
| 43 | } while ((ret!=0) && (i-->0)); |
| 44 | |
| 45 | smbus_write_byte(SMBUS_HUB, 0x03, 0); |
| 46 | } |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 47 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 48 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 49 | { |
| 50 | return smbus_read_byte(device, address); |
| 51 | } |
| 52 | |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 53 | #include <northbridge/amd/amdk8/amdk8.h> |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 54 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
Stefan Reinauer | 23836e2 | 2010-04-15 12:39:29 +0000 | [diff] [blame] | 55 | #include "northbridge/amd/amdk8/coherent_ht.c" |
Myles Watson | 1725703 | 2009-06-04 20:18:42 +0000 | [diff] [blame] | 56 | #include "northbridge/amd/amdk8/raminit_f.c" |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 57 | #include "lib/generic_sdram.c" |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 58 | #include "resourcemap.c" |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 59 | #include "cpu/amd/dualcore/dualcore.c" |
Patrick Georgi | 9bd9a90 | 2010-11-20 10:31:00 +0000 | [diff] [blame] | 60 | #include <spd.h> |
Uwe Hermann | 57b2ff8 | 2010-11-21 17:29:59 +0000 | [diff] [blame] | 61 | #include "cpu/amd/model_fxx/init_cpus.c" |
| 62 | #include "cpu/amd/model_fxx/fidvid.c" |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 63 | |
| 64 | #define RC0 ((1<<0)<<8) |
| 65 | #define RC1 ((1<<1)<<8) |
| 66 | #define RC2 ((1<<2)<<8) |
| 67 | #define RC3 ((1<<3)<<8) |
| 68 | |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 69 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 70 | { |
| 71 | static const uint16_t spd_addr[] = { |
| 72 | //first node |
| 73 | RC0|DIMM0, RC0|DIMM2, 0, 0, |
| 74 | RC0|DIMM1, RC0|DIMM3, 0, 0, |
| 75 | #if CONFIG_MAX_PHYSICAL_CPUS > 1 |
| 76 | //second node |
| 77 | RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, |
| 78 | RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, |
| 79 | #endif |
| 80 | #if CONFIG_MAX_PHYSICAL_CPUS > 2 |
| 81 | // third node |
| 82 | RC2|DIMM0, RC2|DIMM2, 0, 0, |
| 83 | RC2|DIMM1, RC2|DIMM3, 0, 0, |
| 84 | // four node |
| 85 | RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6, |
| 86 | RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7, |
| 87 | #endif |
| 88 | |
| 89 | }; |
| 90 | |
Patrick Georgi | bbc880e | 2012-11-20 18:20:56 +0100 | [diff] [blame] | 91 | struct sys_info *sysinfo = &sysinfo_car; |
Myles Watson | 6e23576 | 2009-09-29 14:56:15 +0000 | [diff] [blame] | 92 | int needs_reset; |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 93 | unsigned bsp_apicid = 0; |
Patrick Georgi | 76e8152 | 2010-11-16 21:25:29 +0000 | [diff] [blame] | 94 | #if CONFIG_SET_FIDVID |
Dan Lykowski | 6ef8e0f | 2009-01-12 16:16:08 +0000 | [diff] [blame] | 95 | struct cpuid_result cpuid1; |
Myles Watson | 6e23576 | 2009-09-29 14:56:15 +0000 | [diff] [blame] | 96 | #endif |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 97 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 98 | if (bist == 0) |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 99 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 100 | |
Edward O'Callaghan | 8199809 | 2014-04-28 18:07:33 +1000 | [diff] [blame] | 101 | winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
| 102 | console_init(); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 103 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 104 | // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 105 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 106 | /* Halt if there was a built in self test failure */ |
| 107 | report_bist_failure(bist); |
| 108 | |
Myles Watson | 08e0fb8 | 2010-03-22 16:33:25 +0000 | [diff] [blame] | 109 | printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 110 | |
Yinghai Lu | 5f9624d | 2006-10-04 22:56:21 +0000 | [diff] [blame] | 111 | setup_mb_resource_map(); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 112 | #if 0 |
| 113 | dump_pci_device(PCI_DEV(0, 0x18, 0)); |
| 114 | dump_pci_device(PCI_DEV(0, 0x19, 0)); |
| 115 | #endif |
| 116 | |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame^] | 117 | printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 118 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 119 | set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 120 | setup_coherent_ht_domain(); // routing table and start other core0 |
| 121 | |
| 122 | wait_all_core0_started(); |
Patrick Georgi | e166782 | 2012-05-05 15:29:32 +0200 | [diff] [blame] | 123 | #if CONFIG_LOGICAL_CPUS |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 124 | // It is said that we should start core1 after all core0 launched |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 125 | /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 126 | * So here need to make sure last core0 is started, esp for two way system, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 127 | * (there may be apic id conflicts in that case) |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 128 | */ |
| 129 | start_other_cores(); |
| 130 | wait_all_other_cores_started(bsp_apicid); |
| 131 | #endif |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 132 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 133 | /* it will set up chains and store link pair for optimization later */ |
| 134 | ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn |
| 135 | |
| 136 | #if 0 |
| 137 | //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. |
| 138 | needs_reset = optimize_link_coherent_ht(); |
| 139 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 140 | #endif |
| 141 | |
Patrick Georgi | 76e8152 | 2010-11-16 21:25:29 +0000 | [diff] [blame] | 142 | #if CONFIG_SET_FIDVID |
Dan Lykowski | 6ef8e0f | 2009-01-12 16:16:08 +0000 | [diff] [blame] | 143 | /* Check to see if processor is capable of changing FIDVID */ |
| 144 | /* otherwise it will throw a GP# when reading FIDVID_STATUS */ |
| 145 | cpuid1 = cpuid(0x80000007); |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame] | 146 | if ((cpuid1.edx & 0x6) == 0x6) { |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 147 | |
| 148 | { |
Dan Lykowski | 6ef8e0f | 2009-01-12 16:16:08 +0000 | [diff] [blame] | 149 | /* Read FIDVID_STATUS */ |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 150 | msr_t msr; |
| 151 | msr=rdmsr(0xc0010042); |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame^] | 152 | printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 153 | } |
| 154 | |
| 155 | enable_fid_change(); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 156 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 157 | init_fidvid_bsp(bsp_apicid); |
| 158 | |
| 159 | // show final fid and vid |
| 160 | { |
| 161 | msr_t msr; |
| 162 | msr=rdmsr(0xc0010042); |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame^] | 163 | printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 164 | } |
Dan Lykowski | 6ef8e0f | 2009-01-12 16:16:08 +0000 | [diff] [blame] | 165 | |
| 166 | } else { |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame^] | 167 | printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); |
Dan Lykowski | 6ef8e0f | 2009-01-12 16:16:08 +0000 | [diff] [blame] | 168 | } |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 169 | #endif |
| 170 | |
| 171 | #if 1 |
| 172 | needs_reset = optimize_link_coherent_ht(); |
| 173 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 174 | |
| 175 | // fidvid change will issue one LDTSTOP and the HT change will be effective too |
| 176 | if (needs_reset) { |
Stefan Reinauer | 069f476 | 2015-01-05 13:02:32 -0800 | [diff] [blame^] | 177 | printk(BIOS_INFO, "ht reset -\n"); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 178 | soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); |
| 179 | } |
| 180 | #endif |
| 181 | allow_all_aps_stop(bsp_apicid); |
| 182 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 183 | //It's the time to set ctrl in sysinfo now; |
| 184 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 185 | |
| 186 | enable_smbus(); |
| 187 | |
| 188 | #if 0 |
Myles Watson | 6e23576 | 2009-09-29 14:56:15 +0000 | [diff] [blame] | 189 | int i; |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 190 | for(i=0;i<4;i++) { |
| 191 | activate_spd_rom(&cpu[i]); |
| 192 | dump_smbus_registers(); |
| 193 | } |
| 194 | #endif |
| 195 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 196 | memreset_setup(); |
| 197 | |
| 198 | //do we need apci timer, tsc...., only debug need it for better output |
| 199 | /* all ap stopped? */ |
| 200 | // init_timer(); // Need to use TMICT to synconize FID/VID |
| 201 | |
| 202 | sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); |
| 203 | |
| 204 | #if 0 |
| 205 | print_pci_devices(); |
| 206 | #endif |
| 207 | |
| 208 | #if 0 |
| 209 | // dump_pci_devices(); |
| 210 | dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); |
| 211 | dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); |
| 212 | #endif |
| 213 | |
| 214 | post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 215 | } |