Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 1 | #define RAMINIT_SYSINFO 1 |
| 2 | #define CACHE_AS_RAM_ADDRESS_DEBUG 0 |
| 3 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 4 | #define SET_NB_CFG_54 1 |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 5 | |
| 6 | //used by raminit |
| 7 | #define QRANK_DIMM_SUPPORT 1 |
| 8 | |
| 9 | //used by incoherent_ht |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 10 | //#define K8_ALLOCATE_IO_RANGE 1 |
| 11 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 12 | //used by init_cpus and fidvid |
Myles Watson | 9b43afd | 2010-04-08 15:09:53 +0000 | [diff] [blame] | 13 | #define SET_FIDVID 0 |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 14 | //if we want to wait for core1 done before DQS training, set it to 0 |
Myles Watson | 9b43afd | 2010-04-08 15:09:53 +0000 | [diff] [blame] | 15 | #define SET_FIDVID_CORE0_ONLY 1 |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 16 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 17 | #if CONFIG_K8_REV_F_SUPPORT == 1 |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 18 | #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 |
Yinghai Lu | 5f9624d | 2006-10-04 22:56:21 +0000 | [diff] [blame] | 19 | #endif |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 20 | |
| 21 | #include <stdint.h> |
Patrick Georgi | 12aba82 | 2009-04-30 07:07:22 +0000 | [diff] [blame] | 22 | #include <string.h> |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 23 | #include <device/pci_def.h> |
| 24 | #include <device/pci_ids.h> |
| 25 | #include <arch/io.h> |
| 26 | #include <device/pnp_def.h> |
| 27 | #include <arch/romcc_io.h> |
| 28 | #include <cpu/x86/lapic.h> |
| 29 | #include "option_table.h" |
| 30 | #include "pc80/mc146818rtc_early.c" |
| 31 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 32 | #include "pc80/serial.c" |
Stefan Reinauer | 5a1f597 | 2010-03-31 14:34:40 +0000 | [diff] [blame] | 33 | #include "console/console.c" |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 34 | #include <cpu/amd/model_fxx_rev.h> |
| 35 | #include "southbridge/amd/amd8111/amd8111_early_smbus.c" |
Stefan Reinauer | 8f2c616 | 2010-04-06 21:50:21 +0000 | [diff] [blame] | 36 | #include <reset.h> |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 37 | #include "northbridge/amd/amdk8/raminit.h" |
| 38 | #include "cpu/amd/model_fxx/apic_timer.c" |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 39 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 40 | #include "cpu/x86/lapic/boot_cpu.c" |
| 41 | #include "northbridge/amd/amdk8/reset_test.c" |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 42 | |
Yinghai Lu | 5f9624d | 2006-10-04 22:56:21 +0000 | [diff] [blame] | 43 | #include "cpu/x86/bist.h" |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 44 | |
| 45 | #include "lib/delay.c" |
| 46 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 47 | #include "northbridge/amd/amdk8/debug.c" |
Stefan Reinauer | 8f2c616 | 2010-04-06 21:50:21 +0000 | [diff] [blame] | 48 | #include "cpu/x86/mtrr/earlymtrr.c" |
| 49 | #include <cpu/amd/mtrr.h> |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 50 | #include "superio/winbond/w83627hf/w83627hf_early_serial.c" |
| 51 | |
| 52 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
| 53 | |
| 54 | #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) |
| 55 | |
| 56 | #include "southbridge/amd/amd8111/amd8111_early_ctrl.c" |
| 57 | |
| 58 | static void memreset_setup(void) |
| 59 | { |
| 60 | //GPIO on amd8111 to enable MEMRST ???? |
| 61 | outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 |
| 62 | outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); |
| 63 | } |
| 64 | |
| 65 | static void memreset(int controllers, const struct mem_controller *ctrl) |
| 66 | { |
| 67 | } |
| 68 | |
| 69 | static inline void activate_spd_rom(const struct mem_controller *ctrl) |
| 70 | { |
| 71 | #define SMBUS_HUB 0x18 |
| 72 | int ret,i; |
| 73 | unsigned device=(ctrl->channel0[0])>>8; |
| 74 | /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ |
| 75 | i=2; |
| 76 | do { |
| 77 | ret = smbus_write_byte(SMBUS_HUB, 0x01, device); |
| 78 | } while ((ret!=0) && (i-->0)); |
| 79 | |
| 80 | smbus_write_byte(SMBUS_HUB, 0x03, 0); |
| 81 | } |
| 82 | #if 0 |
| 83 | static inline void change_i2c_mux(unsigned device) |
| 84 | { |
| 85 | #define SMBUS_HUB 0x18 |
| 86 | int ret, i; |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 87 | print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 88 | i=2; |
| 89 | do { |
| 90 | ret = smbus_write_byte(SMBUS_HUB, 0x01, device); |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 91 | print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n"); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 92 | } while ((ret!=0) && (i-->0)); |
| 93 | ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 94 | print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n"); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 95 | } |
| 96 | #endif |
| 97 | |
| 98 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 99 | { |
| 100 | return smbus_read_byte(device, address); |
| 101 | } |
| 102 | |
Yinghai Lu | 5f9624d | 2006-10-04 22:56:21 +0000 | [diff] [blame] | 103 | #include "northbridge/amd/amdk8/amdk8.h" |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 104 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
Stefan Reinauer | 23836e2 | 2010-04-15 12:39:29 +0000 | [diff] [blame] | 105 | #include "northbridge/amd/amdk8/coherent_ht.c" |
Myles Watson | 1725703 | 2009-06-04 20:18:42 +0000 | [diff] [blame] | 106 | #include "northbridge/amd/amdk8/raminit_f.c" |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 107 | #include "lib/generic_sdram.c" |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 108 | |
| 109 | /* tyan does not want the default */ |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 110 | #include "resourcemap.c" |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 111 | |
| 112 | #include "cpu/amd/dualcore/dualcore.c" |
| 113 | |
| 114 | #define RC0 ((1<<0)<<8) |
| 115 | #define RC1 ((1<<1)<<8) |
| 116 | #define RC2 ((1<<2)<<8) |
| 117 | #define RC3 ((1<<3)<<8) |
| 118 | |
| 119 | #define DIMM0 0x50 |
| 120 | #define DIMM1 0x51 |
| 121 | #define DIMM2 0x52 |
| 122 | #define DIMM3 0x53 |
| 123 | #define DIMM4 0x54 |
| 124 | #define DIMM5 0x55 |
| 125 | #define DIMM6 0x56 |
| 126 | #define DIMM7 0x57 |
| 127 | |
Stefan Reinauer | 853263b | 2010-04-09 10:43:49 +0000 | [diff] [blame] | 128 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 129 | #include "cpu/amd/car/post_cache_as_ram.c" |
| 130 | |
| 131 | #include "cpu/amd/model_fxx/init_cpus.c" |
| 132 | |
| 133 | #include "cpu/amd/model_fxx/fidvid.c" |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 134 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 135 | #include "southbridge/amd/amd8111/amd8111_enable_rom.c" |
| 136 | #include "northbridge/amd/amdk8/early_ht.c" |
| 137 | |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 138 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 139 | { |
| 140 | static const uint16_t spd_addr[] = { |
| 141 | //first node |
| 142 | RC0|DIMM0, RC0|DIMM2, 0, 0, |
| 143 | RC0|DIMM1, RC0|DIMM3, 0, 0, |
| 144 | #if CONFIG_MAX_PHYSICAL_CPUS > 1 |
| 145 | //second node |
| 146 | RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, |
| 147 | RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, |
| 148 | #endif |
| 149 | #if CONFIG_MAX_PHYSICAL_CPUS > 2 |
| 150 | // third node |
| 151 | RC2|DIMM0, RC2|DIMM2, 0, 0, |
| 152 | RC2|DIMM1, RC2|DIMM3, 0, 0, |
| 153 | // four node |
| 154 | RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6, |
| 155 | RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7, |
| 156 | #endif |
| 157 | |
| 158 | }; |
| 159 | |
Myles Watson | 6e23576 | 2009-09-29 14:56:15 +0000 | [diff] [blame] | 160 | struct sys_info *sysinfo = (void*)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 161 | |
Myles Watson | 6e23576 | 2009-09-29 14:56:15 +0000 | [diff] [blame] | 162 | int needs_reset; |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 163 | unsigned bsp_apicid = 0; |
Myles Watson | 9b43afd | 2010-04-08 15:09:53 +0000 | [diff] [blame] | 164 | #if SET_FIDVID == 1 |
Dan Lykowski | 6ef8e0f | 2009-01-12 16:16:08 +0000 | [diff] [blame] | 165 | struct cpuid_result cpuid1; |
Myles Watson | 6e23576 | 2009-09-29 14:56:15 +0000 | [diff] [blame] | 166 | #endif |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 167 | |
Patrick Georgi | 2bd9100 | 2010-03-18 16:46:50 +0000 | [diff] [blame] | 168 | if (!cpu_init_detectedx && boot_cpu()) { |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 169 | /* Nothing special needs to be done to find bus 0 */ |
| 170 | /* Allow the HT devices to be found */ |
| 171 | |
| 172 | enumerate_ht_chain(); |
| 173 | |
| 174 | /* Setup the rom access for 4M */ |
| 175 | amd8111_enable_rom(); |
| 176 | } |
| 177 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 178 | if (bist == 0) { |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 179 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
| 180 | } |
| 181 | |
| 182 | // post_code(0x32); |
| 183 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 184 | w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 185 | uart_init(); |
| 186 | console_init(); |
| 187 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 188 | // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 189 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 190 | /* Halt if there was a built in self test failure */ |
| 191 | report_bist_failure(bist); |
| 192 | |
Myles Watson | 08e0fb8 | 2010-03-22 16:33:25 +0000 | [diff] [blame] | 193 | printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 194 | |
Yinghai Lu | 5f9624d | 2006-10-04 22:56:21 +0000 | [diff] [blame] | 195 | setup_mb_resource_map(); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 196 | #if 0 |
| 197 | dump_pci_device(PCI_DEV(0, 0x18, 0)); |
| 198 | dump_pci_device(PCI_DEV(0, 0x19, 0)); |
| 199 | #endif |
| 200 | |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 201 | print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 202 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 203 | #if CONFIG_MEM_TRAIN_SEQ == 1 |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 204 | set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 205 | #endif |
| 206 | setup_coherent_ht_domain(); // routing table and start other core0 |
| 207 | |
| 208 | wait_all_core0_started(); |
| 209 | #if CONFIG_LOGICAL_CPUS==1 |
| 210 | // It is said that we should start core1 after all core0 launched |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 211 | /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 212 | * So here need to make sure last core0 is started, esp for two way system, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 213 | * (there may be apic id conflicts in that case) |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 214 | */ |
| 215 | start_other_cores(); |
| 216 | wait_all_other_cores_started(bsp_apicid); |
| 217 | #endif |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 218 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 219 | /* it will set up chains and store link pair for optimization later */ |
| 220 | ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn |
| 221 | |
| 222 | #if 0 |
| 223 | //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. |
| 224 | needs_reset = optimize_link_coherent_ht(); |
| 225 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 226 | #endif |
| 227 | |
Myles Watson | 9b43afd | 2010-04-08 15:09:53 +0000 | [diff] [blame] | 228 | #if SET_FIDVID == 1 |
Dan Lykowski | 6ef8e0f | 2009-01-12 16:16:08 +0000 | [diff] [blame] | 229 | /* Check to see if processor is capable of changing FIDVID */ |
| 230 | /* otherwise it will throw a GP# when reading FIDVID_STATUS */ |
| 231 | cpuid1 = cpuid(0x80000007); |
| 232 | if( (cpuid1.edx & 0x6) == 0x6 ) { |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 233 | |
| 234 | { |
Dan Lykowski | 6ef8e0f | 2009-01-12 16:16:08 +0000 | [diff] [blame] | 235 | /* Read FIDVID_STATUS */ |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 236 | msr_t msr; |
| 237 | msr=rdmsr(0xc0010042); |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 238 | print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 239 | |
| 240 | } |
| 241 | |
| 242 | enable_fid_change(); |
| 243 | |
| 244 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
| 245 | |
| 246 | init_fidvid_bsp(bsp_apicid); |
| 247 | |
| 248 | // show final fid and vid |
| 249 | { |
| 250 | msr_t msr; |
| 251 | msr=rdmsr(0xc0010042); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame^] | 252 | print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 253 | |
| 254 | } |
Dan Lykowski | 6ef8e0f | 2009-01-12 16:16:08 +0000 | [diff] [blame] | 255 | |
| 256 | } else { |
| 257 | print_debug("Changing FIDVID not supported\n"); |
| 258 | } |
| 259 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 260 | #endif |
| 261 | |
| 262 | #if 1 |
| 263 | needs_reset = optimize_link_coherent_ht(); |
| 264 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 265 | |
| 266 | // fidvid change will issue one LDTSTOP and the HT change will be effective too |
| 267 | if (needs_reset) { |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 268 | print_info("ht reset -\n"); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 269 | soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); |
| 270 | } |
| 271 | #endif |
| 272 | allow_all_aps_stop(bsp_apicid); |
| 273 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 274 | //It's the time to set ctrl in sysinfo now; |
| 275 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 276 | |
| 277 | enable_smbus(); |
| 278 | |
| 279 | #if 0 |
Myles Watson | 6e23576 | 2009-09-29 14:56:15 +0000 | [diff] [blame] | 280 | int i; |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 281 | for(i=0;i<4;i++) { |
| 282 | activate_spd_rom(&cpu[i]); |
| 283 | dump_smbus_registers(); |
| 284 | } |
| 285 | #endif |
| 286 | |
| 287 | #if 0 |
| 288 | for(i=1;i<256;i<<=1) { |
| 289 | change_i2c_mux(i); |
| 290 | dump_smbus_registers(); |
| 291 | } |
| 292 | #endif |
| 293 | |
| 294 | memreset_setup(); |
| 295 | |
| 296 | //do we need apci timer, tsc...., only debug need it for better output |
| 297 | /* all ap stopped? */ |
| 298 | // init_timer(); // Need to use TMICT to synconize FID/VID |
| 299 | |
| 300 | sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); |
| 301 | |
| 302 | #if 0 |
| 303 | print_pci_devices(); |
| 304 | #endif |
| 305 | |
| 306 | #if 0 |
| 307 | // dump_pci_devices(); |
| 308 | dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); |
| 309 | dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); |
| 310 | #endif |
| 311 | |
| 312 | post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now |
| 313 | |
| 314 | } |
Stefan Reinauer | 798ef28 | 2010-03-29 22:08:01 +0000 | [diff] [blame] | 315 | |