Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 1 | #if CONFIG_K8_REV_F_SUPPORT == 1 |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 2 | #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 |
Yinghai Lu | 5f9624d | 2006-10-04 22:56:21 +0000 | [diff] [blame] | 3 | #endif |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 4 | |
| 5 | #include <stdint.h> |
Patrick Georgi | 12aba82 | 2009-04-30 07:07:22 +0000 | [diff] [blame] | 6 | #include <string.h> |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 7 | #include <device/pci_def.h> |
| 8 | #include <device/pci_ids.h> |
| 9 | #include <arch/io.h> |
| 10 | #include <device/pnp_def.h> |
| 11 | #include <arch/romcc_io.h> |
| 12 | #include <cpu/x86/lapic.h> |
Edwin Beasant | eb50c7d | 2010-07-06 21:05:04 +0000 | [diff] [blame] | 13 | #include <pc80/mc146818rtc.h> |
Patrick Georgi | 12584e2 | 2010-05-08 09:14:51 +0000 | [diff] [blame] | 14 | #include <console/console.h> |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 15 | #include <cpu/amd/model_fxx_rev.h> |
| 16 | #include "southbridge/amd/amd8111/amd8111_early_smbus.c" |
Stefan Reinauer | 8f2c616 | 2010-04-06 21:50:21 +0000 | [diff] [blame] | 17 | #include <reset.h> |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 18 | #include "northbridge/amd/amdk8/raminit.h" |
| 19 | #include "cpu/amd/model_fxx/apic_timer.c" |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 20 | #include "cpu/x86/lapic/boot_cpu.c" |
| 21 | #include "northbridge/amd/amdk8/reset_test.c" |
Yinghai Lu | 5f9624d | 2006-10-04 22:56:21 +0000 | [diff] [blame] | 22 | #include "cpu/x86/bist.h" |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 23 | #include "lib/delay.c" |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 24 | #include "northbridge/amd/amdk8/debug.c" |
Stefan Reinauer | 8f2c616 | 2010-04-06 21:50:21 +0000 | [diff] [blame] | 25 | #include "cpu/x86/mtrr/earlymtrr.c" |
| 26 | #include <cpu/amd/mtrr.h> |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 27 | #include "superio/winbond/w83627hf/w83627hf_early_serial.c" |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 28 | #include "northbridge/amd/amdk8/setup_resource_map.c" |
Uwe Hermann | 57b2ff8 | 2010-11-21 17:29:59 +0000 | [diff] [blame] | 29 | #include "southbridge/amd/amd8111/amd8111_early_ctrl.c" |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 30 | |
| 31 | #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) |
| 32 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 33 | static void memreset_setup(void) |
| 34 | { |
| 35 | //GPIO on amd8111 to enable MEMRST ???? |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame^] | 36 | outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 |
| 37 | outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 38 | } |
| 39 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame^] | 40 | static void memreset(int controllers, const struct mem_controller *ctrl) { } |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 41 | |
| 42 | static inline void activate_spd_rom(const struct mem_controller *ctrl) |
| 43 | { |
| 44 | #define SMBUS_HUB 0x18 |
| 45 | int ret,i; |
| 46 | unsigned device=(ctrl->channel0[0])>>8; |
| 47 | /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ |
| 48 | i=2; |
| 49 | do { |
| 50 | ret = smbus_write_byte(SMBUS_HUB, 0x01, device); |
| 51 | } while ((ret!=0) && (i-->0)); |
| 52 | |
| 53 | smbus_write_byte(SMBUS_HUB, 0x03, 0); |
| 54 | } |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame^] | 55 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 56 | #if 0 |
| 57 | static inline void change_i2c_mux(unsigned device) |
| 58 | { |
| 59 | #define SMBUS_HUB 0x18 |
| 60 | int ret, i; |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 61 | print_debug("change_i2c_mux i="); print_debug_hex8(device); print_debug("\n"); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 62 | i=2; |
| 63 | do { |
| 64 | ret = smbus_write_byte(SMBUS_HUB, 0x01, device); |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 65 | print_debug("change_i2c_mux 1 ret="); print_debug_hex32(ret); print_debug("\n"); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 66 | } while ((ret!=0) && (i-->0)); |
| 67 | ret = smbus_write_byte(SMBUS_HUB, 0x03, 0); |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 68 | print_debug("change_i2c_mux 2 ret="); print_debug_hex32(ret); print_debug("\n"); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 69 | } |
| 70 | #endif |
| 71 | |
| 72 | static inline int spd_read_byte(unsigned device, unsigned address) |
| 73 | { |
| 74 | return smbus_read_byte(device, address); |
| 75 | } |
| 76 | |
Yinghai Lu | 5f9624d | 2006-10-04 22:56:21 +0000 | [diff] [blame] | 77 | #include "northbridge/amd/amdk8/amdk8.h" |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 78 | #include "northbridge/amd/amdk8/incoherent_ht.c" |
Stefan Reinauer | 23836e2 | 2010-04-15 12:39:29 +0000 | [diff] [blame] | 79 | #include "northbridge/amd/amdk8/coherent_ht.c" |
Myles Watson | 1725703 | 2009-06-04 20:18:42 +0000 | [diff] [blame] | 80 | #include "northbridge/amd/amdk8/raminit_f.c" |
Stefan Reinauer | c13093b | 2009-09-23 18:51:03 +0000 | [diff] [blame] | 81 | #include "lib/generic_sdram.c" |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame^] | 82 | #include "resourcemap.c" |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 83 | #include "cpu/amd/dualcore/dualcore.c" |
Patrick Georgi | 9bd9a90 | 2010-11-20 10:31:00 +0000 | [diff] [blame] | 84 | #include <spd.h> |
Uwe Hermann | 57b2ff8 | 2010-11-21 17:29:59 +0000 | [diff] [blame] | 85 | #include "cpu/amd/car/post_cache_as_ram.c" |
| 86 | #include "cpu/amd/model_fxx/init_cpus.c" |
| 87 | #include "cpu/amd/model_fxx/fidvid.c" |
| 88 | #include "southbridge/amd/amd8111/amd8111_enable_rom.c" |
| 89 | #include "northbridge/amd/amdk8/early_ht.c" |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 90 | |
| 91 | #define RC0 ((1<<0)<<8) |
| 92 | #define RC1 ((1<<1)<<8) |
| 93 | #define RC2 ((1<<2)<<8) |
| 94 | #define RC3 ((1<<3)<<8) |
| 95 | |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 96 | void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 97 | { |
| 98 | static const uint16_t spd_addr[] = { |
| 99 | //first node |
| 100 | RC0|DIMM0, RC0|DIMM2, 0, 0, |
| 101 | RC0|DIMM1, RC0|DIMM3, 0, 0, |
| 102 | #if CONFIG_MAX_PHYSICAL_CPUS > 1 |
| 103 | //second node |
| 104 | RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, |
| 105 | RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, |
| 106 | #endif |
| 107 | #if CONFIG_MAX_PHYSICAL_CPUS > 2 |
| 108 | // third node |
| 109 | RC2|DIMM0, RC2|DIMM2, 0, 0, |
| 110 | RC2|DIMM1, RC2|DIMM3, 0, 0, |
| 111 | // four node |
| 112 | RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6, |
| 113 | RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7, |
| 114 | #endif |
| 115 | |
| 116 | }; |
| 117 | |
Myles Watson | 6e23576 | 2009-09-29 14:56:15 +0000 | [diff] [blame] | 118 | struct sys_info *sysinfo = (void*)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); |
Myles Watson | 6e23576 | 2009-09-29 14:56:15 +0000 | [diff] [blame] | 119 | int needs_reset; |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 120 | unsigned bsp_apicid = 0; |
Patrick Georgi | 76e8152 | 2010-11-16 21:25:29 +0000 | [diff] [blame] | 121 | #if CONFIG_SET_FIDVID |
Dan Lykowski | 6ef8e0f | 2009-01-12 16:16:08 +0000 | [diff] [blame] | 122 | struct cpuid_result cpuid1; |
Myles Watson | 6e23576 | 2009-09-29 14:56:15 +0000 | [diff] [blame] | 123 | #endif |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 124 | |
Patrick Georgi | 2bd9100 | 2010-03-18 16:46:50 +0000 | [diff] [blame] | 125 | if (!cpu_init_detectedx && boot_cpu()) { |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 126 | /* Nothing special needs to be done to find bus 0 */ |
| 127 | /* Allow the HT devices to be found */ |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 128 | enumerate_ht_chain(); |
Patrick Georgi | ce6fb1e | 2010-03-17 22:44:39 +0000 | [diff] [blame] | 129 | amd8111_enable_rom(); |
| 130 | } |
| 131 | |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame^] | 132 | if (bist == 0) |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 133 | bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 134 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 135 | w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 136 | uart_init(); |
| 137 | console_init(); |
| 138 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 139 | // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 140 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 141 | /* Halt if there was a built in self test failure */ |
| 142 | report_bist_failure(bist); |
| 143 | |
Myles Watson | 08e0fb8 | 2010-03-22 16:33:25 +0000 | [diff] [blame] | 144 | printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 145 | |
Yinghai Lu | 5f9624d | 2006-10-04 22:56:21 +0000 | [diff] [blame] | 146 | setup_mb_resource_map(); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 147 | #if 0 |
| 148 | dump_pci_device(PCI_DEV(0, 0x18, 0)); |
| 149 | dump_pci_device(PCI_DEV(0, 0x19, 0)); |
| 150 | #endif |
| 151 | |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 152 | print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 153 | |
Stefan Reinauer | 0867062 | 2009-06-30 15:17:49 +0000 | [diff] [blame] | 154 | #if CONFIG_MEM_TRAIN_SEQ == 1 |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 155 | set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 156 | #endif |
| 157 | setup_coherent_ht_domain(); // routing table and start other core0 |
| 158 | |
| 159 | wait_all_core0_started(); |
| 160 | #if CONFIG_LOGICAL_CPUS==1 |
| 161 | // It is said that we should start core1 after all core0 launched |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 162 | /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 163 | * So here need to make sure last core0 is started, esp for two way system, |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 164 | * (there may be apic id conflicts in that case) |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 165 | */ |
| 166 | start_other_cores(); |
| 167 | wait_all_other_cores_started(bsp_apicid); |
| 168 | #endif |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 169 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 170 | /* it will set up chains and store link pair for optimization later */ |
| 171 | ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn |
| 172 | |
| 173 | #if 0 |
| 174 | //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. |
| 175 | needs_reset = optimize_link_coherent_ht(); |
| 176 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 177 | #endif |
| 178 | |
Patrick Georgi | 76e8152 | 2010-11-16 21:25:29 +0000 | [diff] [blame] | 179 | #if CONFIG_SET_FIDVID |
Dan Lykowski | 6ef8e0f | 2009-01-12 16:16:08 +0000 | [diff] [blame] | 180 | /* Check to see if processor is capable of changing FIDVID */ |
| 181 | /* otherwise it will throw a GP# when reading FIDVID_STATUS */ |
| 182 | cpuid1 = cpuid(0x80000007); |
Uwe Hermann | 7b99705 | 2010-11-21 22:47:22 +0000 | [diff] [blame^] | 183 | if ((cpuid1.edx & 0x6) == 0x6) { |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 184 | |
| 185 | { |
Dan Lykowski | 6ef8e0f | 2009-01-12 16:16:08 +0000 | [diff] [blame] | 186 | /* Read FIDVID_STATUS */ |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 187 | msr_t msr; |
| 188 | msr=rdmsr(0xc0010042); |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 189 | print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 190 | } |
| 191 | |
| 192 | enable_fid_change(); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 193 | enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 194 | init_fidvid_bsp(bsp_apicid); |
| 195 | |
| 196 | // show final fid and vid |
| 197 | { |
| 198 | msr_t msr; |
| 199 | msr=rdmsr(0xc0010042); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 200 | print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 201 | } |
Dan Lykowski | 6ef8e0f | 2009-01-12 16:16:08 +0000 | [diff] [blame] | 202 | |
| 203 | } else { |
| 204 | print_debug("Changing FIDVID not supported\n"); |
| 205 | } |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 206 | #endif |
| 207 | |
| 208 | #if 1 |
| 209 | needs_reset = optimize_link_coherent_ht(); |
| 210 | needs_reset |= optimize_link_incoherent_ht(sysinfo); |
| 211 | |
| 212 | // fidvid change will issue one LDTSTOP and the HT change will be effective too |
| 213 | if (needs_reset) { |
Stefan Reinauer | 64ed2b7 | 2010-03-31 14:47:43 +0000 | [diff] [blame] | 214 | print_info("ht reset -\n"); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 215 | soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); |
| 216 | } |
| 217 | #endif |
| 218 | allow_all_aps_stop(bsp_apicid); |
| 219 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 220 | //It's the time to set ctrl in sysinfo now; |
| 221 | fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 222 | |
| 223 | enable_smbus(); |
| 224 | |
| 225 | #if 0 |
Myles Watson | 6e23576 | 2009-09-29 14:56:15 +0000 | [diff] [blame] | 226 | int i; |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 227 | for(i=0;i<4;i++) { |
| 228 | activate_spd_rom(&cpu[i]); |
| 229 | dump_smbus_registers(); |
| 230 | } |
| 231 | #endif |
| 232 | |
| 233 | #if 0 |
| 234 | for(i=1;i<256;i<<=1) { |
| 235 | change_i2c_mux(i); |
| 236 | dump_smbus_registers(); |
| 237 | } |
| 238 | #endif |
| 239 | |
| 240 | memreset_setup(); |
| 241 | |
| 242 | //do we need apci timer, tsc...., only debug need it for better output |
| 243 | /* all ap stopped? */ |
| 244 | // init_timer(); // Need to use TMICT to synconize FID/VID |
| 245 | |
| 246 | sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); |
| 247 | |
| 248 | #if 0 |
| 249 | print_pci_devices(); |
| 250 | #endif |
| 251 | |
| 252 | #if 0 |
| 253 | // dump_pci_devices(); |
| 254 | dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); |
| 255 | dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); |
| 256 | #endif |
| 257 | |
| 258 | post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 259 | } |