commit 81998090792ebc1a6e39455f5fcb4d2c9ec9c095
author Edward O'Callaghan <eocallaghan@alterapraxis.com> Mon Apr 28 18:07:33 2014 +1000
committer Patrick Georgi <patrick@georgi-clan.de> Wed Apr 30 19:06:47 2014 +0200
tree 214cb0402cdc6224b088a2a513f94719f0fd7405
parent f385ba42e340863df18555bf3cfffe70a96e2d8c

mainboard/: Avoid including early_serial.c from w83627hf

Following the reasoning of:
dbbc136 mainboard/asrock/e350m1: Avoid including early_serial.c

Change-Id: I5d729b90cf6713de2674fb00c726cd2944a3ab4e
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5597
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

src/mainboard/amd/serengeti_cheetah/romstage.c

diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index b103389..14320a5 100644
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -15,7 +15,8 @@
 #include "lib/delay.c"
 #include "northbridge/amd/amdk8/debug.c"
 #include <cpu/amd/mtrr.h>
-#include "superio/winbond/w83627hf/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627hf/w83627hf.h>
 #include "northbridge/amd/amdk8/setup_resource_map.c"
 #include "southbridge/amd/amd8111/early_ctrl.c"
 
@@ -113,8 +114,8 @@
         if (bist == 0)
 		bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
 
- 	w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-        console_init();
+	winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	console_init();
 
 //	dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);