commit 6350a2e43f3657567f50160aa28d5d4305803be0
author Elyes HAOUAS <ehaouas@noos.fr> Fri Sep 16 20:49:38 2016 +0200
committer Patrick Georgi <pgeorgi@google.com> Tue Sep 20 19:06:28 2016 +0200
tree 66473657856456754ab78a636c393c1a744932be
parent ed5f159ed59c52a4731d07ef19bff8ef8de9ae14

src/mainboard/a-trend - emulation: Add space around operators

Change-Id: Ib00a9b2feb723d46642d86b2706728bbca7dd68d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16616
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)

src/mainboard/amd/serengeti_cheetah/romstage.c

diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c
index 51fce31..53adf6c 100644
--- a/src/mainboard/amd/serengeti_cheetah/romstage.c
+++ b/src/mainboard/amd/serengeti_cheetah/romstage.c
@@ -38,8 +38,8 @@
 static void memreset_setup(void)
 {
 	//GPIO on amd8111 to enable MEMRST ????
-        outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN=1
-        outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+        outb((1 << 2)|(1 << 0), SMBUS_IO_BASE + 0xc0 + 16);  //REVC_MEMRST_EN = 1
+        outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17);
 }
 
 static void memreset(int controllers, const struct mem_controller *ctrl) { }
@@ -49,11 +49,11 @@
 #define SMBUS_HUB 0x18
         int ret,i;
         unsigned device=(ctrl->channel0[0])>>8;
-        /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/
-        i=2;
+        /* the very first write always get COL_STS = 1 and ABRT_STS = 1, so try another time*/
+        i = 2;
         do {
                 ret = smbus_write_byte(SMBUS_HUB, 0x01, device);
-        } while ((ret!=0) && (i-->0));
+        } while ((ret != 0) && (i-->0));
 
         smbus_write_byte(SMBUS_HUB, 0x03, 0);
 }
@@ -74,10 +74,10 @@
 #include "cpu/amd/model_fxx/init_cpus.c"
 #include "cpu/amd/model_fxx/fidvid.c"
 
-#define RC0 ((1<<0)<<8)
-#define RC1 ((1<<1)<<8)
-#define RC2 ((1<<2)<<8)
-#define RC3 ((1<<3)<<8)
+#define RC0 ((1 << 0)<<8)
+#define RC1 ((1 << 1)<<8)
+#define RC2 ((1 << 2)<<8)
+#define RC3 ((1 << 3)<<8)
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -161,7 +161,7 @@
         {
 		/* Read FIDVID_STATUS */
                 msr_t msr;
-                msr=rdmsr(0xc0010042);
+                msr = rdmsr(0xc0010042);
                 printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo);
         }
 
@@ -172,7 +172,7 @@
         // show final fid and vid
         {
                 msr_t msr;
-                msr=rdmsr(0xc0010042);
+                msr = rdmsr(0xc0010042);
                 printk(BIOS_DEBUG, "end   msr fid, vid %08x%08x\n", msr.hi, msr.lo);
         }
 
@@ -200,7 +200,7 @@
 
 #if 0
 	int i;
-	for(i=0;i<4;i++) {
+	for(i = 0; i < 4; i++) {
 		activate_spd_rom(&cpu[i]);
 		dump_smbus_registers();
 	}