Angel Pons | 93bcf24 | 2020-04-03 01:22:17 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 2 | |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 3 | |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 4 | #include <AGESA.h> |
Kyösti Mälkki | f61ffcf | 2017-03-04 07:48:32 +0200 | [diff] [blame] | 5 | #include <northbridge/amd/agesa/state_machine.h> |
Kyösti Mälkki | 53052fe | 2016-04-27 09:04:11 +0300 | [diff] [blame] | 6 | #include <PlatformMemoryConfiguration.h> |
Edward O'Callaghan | 5ff4b08 | 2014-03-29 17:54:26 +1100 | [diff] [blame] | 7 | |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 8 | static const PCIe_PORT_DESCRIPTOR PortList[] = { |
| 9 | /* (PCIe port, Lanes 4, PCI Device Number 4, ...) */ |
| 10 | { |
| 11 | 0, |
| 12 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), |
Kyösti Mälkki | c700829 | 2017-09-23 19:12:38 +0300 | [diff] [blame] | 13 | PCIE_PORT_DATA_INITIALIZER(PortEnabled, |
| 14 | ChannelTypeExt6db, |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 15 | 4, |
Kyösti Mälkki | c700829 | 2017-09-23 19:12:38 +0300 | [diff] [blame] | 16 | HotplugDisabled, |
| 17 | PcieGen2, |
| 18 | PcieGen2, |
| 19 | AspmL0sL1, |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 20 | 46) |
| 21 | }, |
| 22 | /* (PCIe port, Lanes 5, PCI Device Number 5, ...) */ |
| 23 | { |
| 24 | 0, |
| 25 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), |
Kyösti Mälkki | c700829 | 2017-09-23 19:12:38 +0300 | [diff] [blame] | 26 | PCIE_PORT_DATA_INITIALIZER(PortEnabled, |
| 27 | ChannelTypeExt6db, |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 28 | 5, |
Kyösti Mälkki | c700829 | 2017-09-23 19:12:38 +0300 | [diff] [blame] | 29 | HotplugDisabled, |
| 30 | PcieGen2, |
| 31 | PcieGen2, |
| 32 | AspmL0sL1, |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 33 | 46) |
| 34 | }, |
| 35 | /* (PCIe port, Lanes 6, PCI Device Number 6, ...) */ |
| 36 | { |
| 37 | 0, |
| 38 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), |
Kyösti Mälkki | c700829 | 2017-09-23 19:12:38 +0300 | [diff] [blame] | 39 | PCIE_PORT_DATA_INITIALIZER(PortEnabled, |
| 40 | ChannelTypeExt6db, |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 41 | 6, |
Kyösti Mälkki | c700829 | 2017-09-23 19:12:38 +0300 | [diff] [blame] | 42 | HotplugDisabled, |
| 43 | PcieGen2, |
| 44 | PcieGen2, |
| 45 | AspmL0sL1, |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 46 | 46) |
| 47 | }, |
| 48 | /* (PCIe port, Lanes 7, PCI Device Number 7, ...) */ |
| 49 | { |
| 50 | 0, |
| 51 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), |
Kyösti Mälkki | c700829 | 2017-09-23 19:12:38 +0300 | [diff] [blame] | 52 | PCIE_PORT_DATA_INITIALIZER(PortDisabled, |
| 53 | ChannelTypeExt6db, |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 54 | 7, |
Kyösti Mälkki | c700829 | 2017-09-23 19:12:38 +0300 | [diff] [blame] | 55 | HotplugDisabled, |
| 56 | PcieGen2, |
| 57 | PcieGen2, |
| 58 | AspmL0sL1, |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 59 | 0) |
| 60 | }, |
| 61 | /* (PCIe port, Lanes 8, PCI Device Number 8, ...) */ |
| 62 | { |
| 63 | DESCRIPTOR_TERMINATE_LIST, |
| 64 | PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), |
Kyösti Mälkki | c700829 | 2017-09-23 19:12:38 +0300 | [diff] [blame] | 65 | PCIE_PORT_DATA_INITIALIZER(PortEnabled, |
| 66 | ChannelTypeExt6db, |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 67 | 8, |
Kyösti Mälkki | c700829 | 2017-09-23 19:12:38 +0300 | [diff] [blame] | 68 | HotplugDisabled, |
| 69 | PcieGen2, |
| 70 | PcieGen2, |
| 71 | AspmL0sL1, |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 72 | 0) |
| 73 | } |
| 74 | }; |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 75 | |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 76 | static const PCIe_DDI_DESCRIPTOR DdiList[] = { |
| 77 | /* (DDI interface Lanes 8:11, DdA, ...) */ |
| 78 | { |
| 79 | 0, |
| 80 | PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 8, 11), |
| 81 | /* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux1, Hdp1) */ |
| 82 | {ConnectorTypeLvds, Aux1, Hdp1} |
| 83 | }, |
| 84 | /* (DDI interface Lanes 12:15, DdB, ...) */ |
| 85 | { |
| 86 | DESCRIPTOR_TERMINATE_LIST, |
| 87 | PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 12, 15), |
| 88 | /* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux2, Hdp2) */ |
| 89 | {ConnectorTypeDP, Aux2, Hdp2} |
| 90 | } |
| 91 | }; |
| 92 | |
| 93 | static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { |
| 94 | .Flags = DESCRIPTOR_TERMINATE_LIST, |
| 95 | .SocketId = 0, |
| 96 | .PciePortList = PortList, |
| 97 | .DdiLinkList = DdiList, |
| 98 | }; |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame] | 99 | |
Kyösti Mälkki | f61ffcf | 2017-03-04 07:48:32 +0200 | [diff] [blame] | 100 | void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 101 | { |
Kyösti Mälkki | 87df267 | 2017-09-23 14:36:16 +0300 | [diff] [blame] | 102 | InitEarly->GnbConfig.PcieComplexList = &PcieComplex; |
| 103 | InitEarly->GnbConfig.PsppPolicy = 0; |
Edward O'Callaghan | 4726a87 | 2014-01-25 07:40:39 +1100 | [diff] [blame] | 104 | } |
Kyösti Mälkki | 6e74b2c | 2014-12-16 07:34:58 +0200 | [diff] [blame] | 105 | |
Kyösti Mälkki | 53052fe | 2016-04-27 09:04:11 +0300 | [diff] [blame] | 106 | /** |
| 107 | * @brief Customer Overides Memory Table |
| 108 | * |
| 109 | * Platform Specific Overriding Table allows IBV/OEM to pass in platform |
| 110 | * information to AGESA |
| 111 | * (e.g. MemClk routing, the number of DIMM slots per channel,...). |
| 112 | * If PlatformSpecificTable is populated, AGESA will base its settings on the |
| 113 | * data from the table. Otherwise, it will use its default conservative settings. |
| 114 | */ |
Kyösti Mälkki | f61ffcf | 2017-03-04 07:48:32 +0200 | [diff] [blame] | 115 | static const PSO_ENTRY ROMDATA PlatformMemoryTable[] = { |
Kyösti Mälkki | e52738b | 2017-09-21 12:32:43 +0300 | [diff] [blame] | 116 | NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), |
| 117 | NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 1), |
Kyösti Mälkki | 53052fe | 2016-04-27 09:04:11 +0300 | [diff] [blame] | 118 | PSO_END |
| 119 | }; |
| 120 | |
Kyösti Mälkki | f61ffcf | 2017-03-04 07:48:32 +0200 | [diff] [blame] | 121 | void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) |
| 122 | { |
| 123 | InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; |
| 124 | } |