Elyes HAOUAS | 3a7346c | 2020-05-07 07:46:17 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
| 2 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 3 | /* |
Martin Roth | d57ace2 | 2019-08-31 10:48:37 -0600 | [diff] [blame] | 4 | * mtrr.c: setting MTRR to decent values for cache initialization on P6 |
| 5 | * Derived from intel_set_mtrr in intel_subr.c and mtrr.c in linux kernel |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 6 | * |
Lee Leahy | c591707 | 2017-03-15 16:38:51 -0700 | [diff] [blame] | 7 | * Reference: Intel Architecture Software Developer's Manual, Volume 3: System |
| 8 | * Programming |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 9 | */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 10 | |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 11 | #include <stddef.h> |
Arthur Heymans | 4ed2260 | 2022-04-11 18:58:09 +0200 | [diff] [blame^] | 12 | #include <stdint.h> |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 13 | #include <string.h> |
Aaron Durbin | bebf669 | 2013-04-24 20:59:43 -0500 | [diff] [blame] | 14 | #include <bootstate.h> |
Elyes HAOUAS | d26844c | 2019-06-21 07:31:40 +0200 | [diff] [blame] | 15 | #include <commonlib/helpers.h> |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 16 | #include <console/console.h> |
| 17 | #include <device/device.h> |
Aaron Durbin | ca4f4b8 | 2014-02-08 15:41:52 -0600 | [diff] [blame] | 18 | #include <device/pci_ids.h> |
Aaron Durbin | ebf142a | 2013-03-29 16:23:23 -0500 | [diff] [blame] | 19 | #include <cpu/cpu.h> |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 20 | #include <cpu/x86/msr.h> |
| 21 | #include <cpu/x86/mtrr.h> |
| 22 | #include <cpu/x86/cache.h> |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 23 | #include <memrange.h> |
Aaron Durbin | 57686f8 | 2013-03-20 15:50:59 -0500 | [diff] [blame] | 24 | #include <cpu/amd/mtrr.h> |
Richard Spiegel | b28025a | 2019-02-20 11:00:19 -0700 | [diff] [blame] | 25 | #include <assert.h> |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 26 | #if CONFIG(X86_AMD_FIXED_MTRRS) |
Aaron Durbin | 57686f8 | 2013-03-20 15:50:59 -0500 | [diff] [blame] | 27 | #define MTRR_FIXED_WRBACK_BITS (MTRR_READ_MEM | MTRR_WRITE_MEM) |
| 28 | #else |
| 29 | #define MTRR_FIXED_WRBACK_BITS 0 |
| 30 | #endif |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 31 | |
Tim Wawrzynczak | 6fcc46d | 2021-04-19 13:47:36 -0600 | [diff] [blame] | 32 | #define MIN_MTRRS 8 |
| 33 | |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 34 | /* |
Isaac Christensen | 81f90c5 | 2014-09-24 14:59:32 -0600 | [diff] [blame] | 35 | * Static storage size for variable MTRRs. It's sized sufficiently large to |
| 36 | * handle different types of CPUs. Empirically, 16 variable MTRRs has not |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 37 | * yet been observed. |
| 38 | */ |
| 39 | #define NUM_MTRR_STATIC_STORAGE 16 |
Stefan Reinauer | c00dfbc | 2012-04-03 16:24:37 -0700 | [diff] [blame] | 40 | |
Tim Wawrzynczak | 6fcc46d | 2021-04-19 13:47:36 -0600 | [diff] [blame] | 41 | static int total_mtrrs; |
Stefan Reinauer | c00dfbc | 2012-04-03 16:24:37 -0700 | [diff] [blame] | 42 | |
| 43 | static void detect_var_mtrrs(void) |
| 44 | { |
Subrata Banik | 7578ea4 | 2022-03-30 23:57:37 +0530 | [diff] [blame] | 45 | total_mtrrs = get_var_mtrr_count(); |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 46 | |
| 47 | if (total_mtrrs > NUM_MTRR_STATIC_STORAGE) { |
| 48 | printk(BIOS_WARNING, |
| 49 | "MTRRs detected (%d) > NUM_MTRR_STATIC_STORAGE (%d)\n", |
| 50 | total_mtrrs, NUM_MTRR_STATIC_STORAGE); |
| 51 | total_mtrrs = NUM_MTRR_STATIC_STORAGE; |
| 52 | } |
Stefan Reinauer | c00dfbc | 2012-04-03 16:24:37 -0700 | [diff] [blame] | 53 | } |
| 54 | |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 55 | void enable_fixed_mtrr(void) |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 56 | { |
| 57 | msr_t msr; |
| 58 | |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 59 | msr = rdmsr(MTRR_DEF_TYPE_MSR); |
| 60 | msr.lo |= MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN; |
| 61 | wrmsr(MTRR_DEF_TYPE_MSR, msr); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 62 | } |
| 63 | |
Marshall Dawson | c0dbeda | 2017-10-19 09:45:16 -0600 | [diff] [blame] | 64 | void fixed_mtrrs_expose_amd_rwdram(void) |
| 65 | { |
| 66 | msr_t syscfg; |
| 67 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 68 | if (!CONFIG(X86_AMD_FIXED_MTRRS)) |
Marshall Dawson | c0dbeda | 2017-10-19 09:45:16 -0600 | [diff] [blame] | 69 | return; |
| 70 | |
| 71 | syscfg = rdmsr(SYSCFG_MSR); |
| 72 | syscfg.lo |= SYSCFG_MSR_MtrrFixDramModEn; |
| 73 | wrmsr(SYSCFG_MSR, syscfg); |
| 74 | } |
| 75 | |
| 76 | void fixed_mtrrs_hide_amd_rwdram(void) |
| 77 | { |
| 78 | msr_t syscfg; |
| 79 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 80 | if (!CONFIG(X86_AMD_FIXED_MTRRS)) |
Marshall Dawson | c0dbeda | 2017-10-19 09:45:16 -0600 | [diff] [blame] | 81 | return; |
| 82 | |
| 83 | syscfg = rdmsr(SYSCFG_MSR); |
| 84 | syscfg.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; |
| 85 | wrmsr(SYSCFG_MSR, syscfg); |
| 86 | } |
| 87 | |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 88 | static void enable_var_mtrr(unsigned char deftype) |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 89 | { |
| 90 | msr_t msr; |
| 91 | |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 92 | msr = rdmsr(MTRR_DEF_TYPE_MSR); |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 93 | msr.lo &= ~0xff; |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 94 | msr.lo |= MTRR_DEF_TYPE_EN | deftype; |
| 95 | wrmsr(MTRR_DEF_TYPE_MSR, msr); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 96 | } |
| 97 | |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 98 | #define MTRR_VERBOSE_LEVEL BIOS_NEVER |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 99 | |
Jonathan Zhang | 320ad93 | 2020-10-14 15:07:51 -0700 | [diff] [blame] | 100 | /* MTRRs are at a 4KiB granularity. */ |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 101 | #define RANGE_SHIFT 12 |
| 102 | #define ADDR_SHIFT_TO_RANGE_SHIFT(x) \ |
| 103 | (((x) > RANGE_SHIFT) ? ((x) - RANGE_SHIFT) : RANGE_SHIFT) |
| 104 | #define PHYS_TO_RANGE_ADDR(x) ((x) >> RANGE_SHIFT) |
| 105 | #define RANGE_TO_PHYS_ADDR(x) (((resource_t)(x)) << RANGE_SHIFT) |
| 106 | #define NUM_FIXED_MTRRS (NUM_FIXED_RANGES / RANGES_PER_FIXED_MTRR) |
| 107 | |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 108 | /* Helpful constants. */ |
Jonathan Zhang | 320ad93 | 2020-10-14 15:07:51 -0700 | [diff] [blame] | 109 | #define RANGE_1MB PHYS_TO_RANGE_ADDR(1ULL << 20) |
| 110 | #define RANGE_4GB (1ULL << (ADDR_SHIFT_TO_RANGE_SHIFT(32))) |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 111 | |
Aaron Durbin | e383442 | 2013-03-28 20:48:51 -0500 | [diff] [blame] | 112 | #define MTRR_ALGO_SHIFT (8) |
| 113 | #define MTRR_TAG_MASK ((1 << MTRR_ALGO_SHIFT) - 1) |
Aaron Durbin | e383442 | 2013-03-28 20:48:51 -0500 | [diff] [blame] | 114 | |
Jonathan Zhang | 320ad93 | 2020-10-14 15:07:51 -0700 | [diff] [blame] | 115 | static inline uint64_t range_entry_base_mtrr_addr(struct range_entry *r) |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 116 | { |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 117 | return PHYS_TO_RANGE_ADDR(range_entry_base(r)); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 118 | } |
| 119 | |
Jonathan Zhang | 320ad93 | 2020-10-14 15:07:51 -0700 | [diff] [blame] | 120 | static inline uint64_t range_entry_end_mtrr_addr(struct range_entry *r) |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 121 | { |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 122 | return PHYS_TO_RANGE_ADDR(range_entry_end(r)); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 123 | } |
| 124 | |
Aaron Durbin | e383442 | 2013-03-28 20:48:51 -0500 | [diff] [blame] | 125 | static inline int range_entry_mtrr_type(struct range_entry *r) |
| 126 | { |
| 127 | return range_entry_tag(r) & MTRR_TAG_MASK; |
| 128 | } |
| 129 | |
Aaron Durbin | ca4f4b8 | 2014-02-08 15:41:52 -0600 | [diff] [blame] | 130 | static int filter_vga_wrcomb(struct device *dev, struct resource *res) |
| 131 | { |
| 132 | /* Only handle PCI devices. */ |
| 133 | if (dev->path.type != DEVICE_PATH_PCI) |
| 134 | return 0; |
| 135 | |
| 136 | /* Only handle VGA class devices. */ |
| 137 | if (((dev->class >> 8) != PCI_CLASS_DISPLAY_VGA)) |
| 138 | return 0; |
| 139 | |
| 140 | /* Add resource as write-combining in the address space. */ |
| 141 | return 1; |
| 142 | } |
| 143 | |
Aaron Durbin | 2bebd7b | 2016-11-10 15:15:35 -0600 | [diff] [blame] | 144 | static void print_physical_address_space(const struct memranges *addr_space, |
| 145 | const char *identifier) |
| 146 | { |
| 147 | const struct range_entry *r; |
| 148 | |
| 149 | if (identifier) |
| 150 | printk(BIOS_DEBUG, "MTRR: %s Physical address space:\n", |
| 151 | identifier); |
| 152 | else |
| 153 | printk(BIOS_DEBUG, "MTRR: Physical address space:\n"); |
| 154 | |
| 155 | memranges_each_entry(r, addr_space) |
| 156 | printk(BIOS_DEBUG, |
| 157 | "0x%016llx - 0x%016llx size 0x%08llx type %ld\n", |
Werner Zeh | eaf11c9 | 2022-04-11 08:35:06 +0200 | [diff] [blame] | 158 | range_entry_base(r), range_entry_end(r) - 1, |
Aaron Durbin | 2bebd7b | 2016-11-10 15:15:35 -0600 | [diff] [blame] | 159 | range_entry_size(r), range_entry_tag(r)); |
| 160 | } |
| 161 | |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 162 | static struct memranges *get_physical_address_space(void) |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 163 | { |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 164 | static struct memranges *addr_space; |
| 165 | static struct memranges addr_space_storage; |
Duncan Laurie | 7389fa9 | 2011-12-22 10:59:40 -0800 | [diff] [blame] | 166 | |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 167 | /* In order to handle some chipsets not being able to pre-determine |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 168 | * uncacheable ranges, such as graphics memory, at resource insertion |
| 169 | * time remove uncacheable regions from the cacheable ones. */ |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 170 | if (addr_space == NULL) { |
Aaron Durbin | 9b027fe | 2013-03-26 14:10:34 -0500 | [diff] [blame] | 171 | unsigned long mask; |
| 172 | unsigned long match; |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 173 | |
| 174 | addr_space = &addr_space_storage; |
| 175 | |
Aaron Durbin | 9b027fe | 2013-03-26 14:10:34 -0500 | [diff] [blame] | 176 | mask = IORESOURCE_CACHEABLE; |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 177 | /* Collect cacheable and uncacheable address ranges. The |
| 178 | * uncacheable regions take precedence over the cacheable |
| 179 | * regions. */ |
| 180 | memranges_init(addr_space, mask, mask, MTRR_TYPE_WRBACK); |
| 181 | memranges_add_resources(addr_space, mask, 0, |
Lee Leahy | a07d0dd | 2017-03-15 14:25:22 -0700 | [diff] [blame] | 182 | MTRR_TYPE_UNCACHEABLE); |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 183 | |
Aaron Durbin | 9b027fe | 2013-03-26 14:10:34 -0500 | [diff] [blame] | 184 | /* Handle any write combining resources. Only prefetchable |
Vladimir Serbinenko | 30fe612 | 2014-02-05 23:25:28 +0100 | [diff] [blame] | 185 | * resources are appropriate for this MTRR type. */ |
| 186 | match = IORESOURCE_PREFETCH; |
Aaron Durbin | 9b027fe | 2013-03-26 14:10:34 -0500 | [diff] [blame] | 187 | mask |= match; |
Lee Leahy | c591707 | 2017-03-15 16:38:51 -0700 | [diff] [blame] | 188 | memranges_add_resources_filter(addr_space, mask, match, |
| 189 | MTRR_TYPE_WRCOMB, filter_vga_wrcomb); |
Aaron Durbin | 9b027fe | 2013-03-26 14:10:34 -0500 | [diff] [blame] | 190 | |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 191 | /* The address space below 4GiB is special. It needs to be |
Martin Roth | 2f91403 | 2016-01-15 10:20:11 -0700 | [diff] [blame] | 192 | * covered entirely by range entries so that MTRR calculations |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 193 | * can be properly done for the full 32-bit address space. |
| 194 | * Therefore, ensure holes are filled up to 4GiB as |
| 195 | * uncacheable */ |
| 196 | memranges_fill_holes_up_to(addr_space, |
Lee Leahy | a07d0dd | 2017-03-15 14:25:22 -0700 | [diff] [blame] | 197 | RANGE_TO_PHYS_ADDR(RANGE_4GB), |
| 198 | MTRR_TYPE_UNCACHEABLE); |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 199 | |
Aaron Durbin | 2bebd7b | 2016-11-10 15:15:35 -0600 | [diff] [blame] | 200 | print_physical_address_space(addr_space, NULL); |
Carl-Daniel Hailfinger | 7dde1da | 2009-02-11 16:57:32 +0000 | [diff] [blame] | 201 | } |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 202 | |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 203 | return addr_space; |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 204 | } |
| 205 | |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 206 | /* Fixed MTRR descriptor. This structure defines the step size and begin |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 207 | * and end (exclusive) address covered by a set of fixed MTRR MSRs. |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 208 | * It also describes the offset in byte intervals to store the calculated MTRR |
| 209 | * type in an array. */ |
| 210 | struct fixed_mtrr_desc { |
| 211 | uint32_t begin; |
| 212 | uint32_t end; |
| 213 | uint32_t step; |
| 214 | int range_index; |
| 215 | int msr_index_base; |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 216 | }; |
| 217 | |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 218 | /* Shared MTRR calculations. Can be reused by APs. */ |
| 219 | static uint8_t fixed_mtrr_types[NUM_FIXED_RANGES]; |
| 220 | |
| 221 | /* Fixed MTRR descriptors. */ |
| 222 | static const struct fixed_mtrr_desc fixed_mtrr_desc[] = { |
| 223 | { PHYS_TO_RANGE_ADDR(0x000000), PHYS_TO_RANGE_ADDR(0x080000), |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 224 | PHYS_TO_RANGE_ADDR(64 * 1024), 0, MTRR_FIX_64K_00000 }, |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 225 | { PHYS_TO_RANGE_ADDR(0x080000), PHYS_TO_RANGE_ADDR(0x0C0000), |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 226 | PHYS_TO_RANGE_ADDR(16 * 1024), 8, MTRR_FIX_16K_80000 }, |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 227 | { PHYS_TO_RANGE_ADDR(0x0C0000), PHYS_TO_RANGE_ADDR(0x100000), |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 228 | PHYS_TO_RANGE_ADDR(4 * 1024), 24, MTRR_FIX_4K_C0000 }, |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 229 | }; |
| 230 | |
| 231 | static void calc_fixed_mtrrs(void) |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 232 | { |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 233 | static int fixed_mtrr_types_initialized; |
| 234 | struct memranges *phys_addr_space; |
| 235 | struct range_entry *r; |
| 236 | const struct fixed_mtrr_desc *desc; |
| 237 | const struct fixed_mtrr_desc *last_desc; |
| 238 | uint32_t begin; |
| 239 | uint32_t end; |
| 240 | int type_index; |
| 241 | |
| 242 | if (fixed_mtrr_types_initialized) |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 243 | return; |
Kyösti Mälkki | 2d42b34 | 2012-07-12 00:18:22 +0300 | [diff] [blame] | 244 | |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 245 | phys_addr_space = get_physical_address_space(); |
Kyösti Mälkki | 2d42b34 | 2012-07-12 00:18:22 +0300 | [diff] [blame] | 246 | |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 247 | /* Set all fixed ranges to uncacheable first. */ |
| 248 | memset(&fixed_mtrr_types[0], MTRR_TYPE_UNCACHEABLE, NUM_FIXED_RANGES); |
Kyösti Mälkki | 2d42b34 | 2012-07-12 00:18:22 +0300 | [diff] [blame] | 249 | |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 250 | desc = &fixed_mtrr_desc[0]; |
| 251 | last_desc = &fixed_mtrr_desc[ARRAY_SIZE(fixed_mtrr_desc) - 1]; |
Kyösti Mälkki | 1ec5e74 | 2012-07-26 23:51:20 +0300 | [diff] [blame] | 252 | |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 253 | memranges_each_entry(r, phys_addr_space) { |
| 254 | begin = range_entry_base_mtrr_addr(r); |
| 255 | end = range_entry_end_mtrr_addr(r); |
Kyösti Mälkki | 2d42b34 | 2012-07-12 00:18:22 +0300 | [diff] [blame] | 256 | |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 257 | if (begin >= last_desc->end) |
| 258 | break; |
| 259 | |
| 260 | if (end > last_desc->end) |
| 261 | end = last_desc->end; |
| 262 | |
| 263 | /* Get to the correct fixed mtrr descriptor. */ |
| 264 | while (begin >= desc->end) |
| 265 | desc++; |
| 266 | |
| 267 | type_index = desc->range_index; |
| 268 | type_index += (begin - desc->begin) / desc->step; |
| 269 | |
| 270 | while (begin != end) { |
| 271 | unsigned char type; |
| 272 | |
| 273 | type = range_entry_tag(r); |
| 274 | printk(MTRR_VERBOSE_LEVEL, |
| 275 | "MTRR addr 0x%x-0x%x set to %d type @ %d\n", |
Werner Zeh | eaf11c9 | 2022-04-11 08:35:06 +0200 | [diff] [blame] | 276 | begin, begin + desc->step - 1, type, type_index); |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 277 | if (type == MTRR_TYPE_WRBACK) |
| 278 | type |= MTRR_FIXED_WRBACK_BITS; |
| 279 | fixed_mtrr_types[type_index] = type; |
| 280 | type_index++; |
| 281 | begin += desc->step; |
| 282 | if (begin == desc->end) |
| 283 | desc++; |
Yinghai Lu | 6360187 | 2005-01-27 22:48:12 +0000 | [diff] [blame] | 284 | } |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 285 | } |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 286 | fixed_mtrr_types_initialized = 1; |
| 287 | } |
| 288 | |
| 289 | static void commit_fixed_mtrrs(void) |
| 290 | { |
| 291 | int i; |
| 292 | int j; |
| 293 | int msr_num; |
| 294 | int type_index; |
| 295 | /* 8 ranges per msr. */ |
| 296 | msr_t fixed_msrs[NUM_FIXED_MTRRS]; |
| 297 | unsigned long msr_index[NUM_FIXED_MTRRS]; |
| 298 | |
Marshall Dawson | c0dbeda | 2017-10-19 09:45:16 -0600 | [diff] [blame] | 299 | fixed_mtrrs_expose_amd_rwdram(); |
| 300 | |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 301 | memset(&fixed_msrs, 0, sizeof(fixed_msrs)); |
| 302 | |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 303 | msr_num = 0; |
| 304 | type_index = 0; |
| 305 | for (i = 0; i < ARRAY_SIZE(fixed_mtrr_desc); i++) { |
| 306 | const struct fixed_mtrr_desc *desc; |
| 307 | int num_ranges; |
| 308 | |
| 309 | desc = &fixed_mtrr_desc[i]; |
| 310 | num_ranges = (desc->end - desc->begin) / desc->step; |
| 311 | for (j = 0; j < num_ranges; j += RANGES_PER_FIXED_MTRR) { |
| 312 | msr_index[msr_num] = desc->msr_index_base + |
| 313 | (j / RANGES_PER_FIXED_MTRR); |
| 314 | fixed_msrs[msr_num].lo |= |
| 315 | fixed_mtrr_types[type_index++] << 0; |
| 316 | fixed_msrs[msr_num].lo |= |
| 317 | fixed_mtrr_types[type_index++] << 8; |
| 318 | fixed_msrs[msr_num].lo |= |
| 319 | fixed_mtrr_types[type_index++] << 16; |
| 320 | fixed_msrs[msr_num].lo |= |
| 321 | fixed_mtrr_types[type_index++] << 24; |
| 322 | fixed_msrs[msr_num].hi |= |
| 323 | fixed_mtrr_types[type_index++] << 0; |
| 324 | fixed_msrs[msr_num].hi |= |
| 325 | fixed_mtrr_types[type_index++] << 8; |
| 326 | fixed_msrs[msr_num].hi |= |
| 327 | fixed_mtrr_types[type_index++] << 16; |
| 328 | fixed_msrs[msr_num].hi |= |
| 329 | fixed_mtrr_types[type_index++] << 24; |
| 330 | msr_num++; |
| 331 | } |
| 332 | } |
| 333 | |
Jacob Garber | 5b92272 | 2019-05-28 11:47:49 -0600 | [diff] [blame] | 334 | /* Ensure that both arrays were fully initialized */ |
| 335 | ASSERT(msr_num == NUM_FIXED_MTRRS) |
| 336 | |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 337 | for (i = 0; i < ARRAY_SIZE(fixed_msrs); i++) |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 338 | printk(BIOS_DEBUG, "MTRR: Fixed MSR 0x%lx 0x%08x%08x\n", |
| 339 | msr_index[i], fixed_msrs[i].hi, fixed_msrs[i].lo); |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 340 | |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 341 | disable_cache(); |
| 342 | for (i = 0; i < ARRAY_SIZE(fixed_msrs); i++) |
| 343 | wrmsr(msr_index[i], fixed_msrs[i]); |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 344 | enable_cache(); |
Marshall Dawson | c0dbeda | 2017-10-19 09:45:16 -0600 | [diff] [blame] | 345 | fixed_mtrrs_hide_amd_rwdram(); |
| 346 | |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 347 | } |
| 348 | |
Aaron Durbin | 57686f8 | 2013-03-20 15:50:59 -0500 | [diff] [blame] | 349 | void x86_setup_fixed_mtrrs_no_enable(void) |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 350 | { |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 351 | calc_fixed_mtrrs(); |
| 352 | commit_fixed_mtrrs(); |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 353 | } |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 354 | |
Aaron Durbin | 57686f8 | 2013-03-20 15:50:59 -0500 | [diff] [blame] | 355 | void x86_setup_fixed_mtrrs(void) |
| 356 | { |
| 357 | x86_setup_fixed_mtrrs_no_enable(); |
| 358 | |
| 359 | printk(BIOS_SPEW, "call enable_fixed_mtrr()\n"); |
| 360 | enable_fixed_mtrr(); |
| 361 | } |
| 362 | |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 363 | struct var_mtrr_regs { |
| 364 | msr_t base; |
| 365 | msr_t mask; |
| 366 | }; |
| 367 | |
| 368 | struct var_mtrr_solution { |
| 369 | int mtrr_default_type; |
| 370 | int num_used; |
| 371 | struct var_mtrr_regs regs[NUM_MTRR_STATIC_STORAGE]; |
| 372 | }; |
| 373 | |
| 374 | /* Global storage for variable MTRR solution. */ |
| 375 | static struct var_mtrr_solution mtrr_global_solution; |
| 376 | |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 377 | struct var_mtrr_state { |
| 378 | struct memranges *addr_space; |
| 379 | int above4gb; |
| 380 | int address_bits; |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 381 | int prepare_msrs; |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 382 | int mtrr_index; |
| 383 | int def_mtrr_type; |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 384 | struct var_mtrr_regs *regs; |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 385 | }; |
Aaron Durbin | 57686f8 | 2013-03-20 15:50:59 -0500 | [diff] [blame] | 386 | |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 387 | static void clear_var_mtrr(int index) |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 388 | { |
Aaron Durbin | 2bebd7b | 2016-11-10 15:15:35 -0600 | [diff] [blame] | 389 | msr_t msr = { .lo = 0, .hi = 0 }; |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 390 | |
Aaron Durbin | 2bebd7b | 2016-11-10 15:15:35 -0600 | [diff] [blame] | 391 | wrmsr(MTRR_PHYS_BASE(index), msr); |
| 392 | wrmsr(MTRR_PHYS_MASK(index), msr); |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 393 | } |
| 394 | |
Tim Wawrzynczak | 6fcc46d | 2021-04-19 13:47:36 -0600 | [diff] [blame] | 395 | static int get_os_reserved_mtrrs(void) |
| 396 | { |
| 397 | return CONFIG(RESERVE_MTRRS_FOR_OS) ? 2 : 0; |
| 398 | } |
| 399 | |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 400 | static void prep_var_mtrr(struct var_mtrr_state *var_state, |
Jonathan Zhang | 320ad93 | 2020-10-14 15:07:51 -0700 | [diff] [blame] | 401 | uint64_t base, uint64_t size, int mtrr_type) |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 402 | { |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 403 | struct var_mtrr_regs *regs; |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 404 | resource_t rbase; |
| 405 | resource_t rsize; |
| 406 | resource_t mask; |
| 407 | |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 408 | if (var_state->mtrr_index >= total_mtrrs) { |
Julius Werner | e966595 | 2022-01-21 17:06:20 -0800 | [diff] [blame] | 409 | printk(BIOS_ERR, "Not enough MTRRs available! MTRR index is %d with %d MTRRs in total.\n", |
Paul Menzel | 6a70dbc | 2015-10-15 12:41:53 +0200 | [diff] [blame] | 410 | var_state->mtrr_index, total_mtrrs); |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 411 | return; |
| 412 | } |
| 413 | |
Tim Wawrzynczak | 6fcc46d | 2021-04-19 13:47:36 -0600 | [diff] [blame] | 414 | /* |
| 415 | * If desired, 2 variable MTRRs are attempted to be saved for the OS to |
| 416 | * use. However, it's more important to try to map the full address |
| 417 | * space properly. |
| 418 | */ |
| 419 | if (var_state->mtrr_index >= total_mtrrs - get_os_reserved_mtrrs()) |
| 420 | printk(BIOS_WARNING, "Taking a reserved OS MTRR.\n"); |
| 421 | |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 422 | rbase = base; |
| 423 | rsize = size; |
| 424 | |
| 425 | rbase = RANGE_TO_PHYS_ADDR(rbase); |
| 426 | rsize = RANGE_TO_PHYS_ADDR(rsize); |
| 427 | rsize = -rsize; |
| 428 | |
| 429 | mask = (1ULL << var_state->address_bits) - 1; |
| 430 | rsize = rsize & mask; |
| 431 | |
| 432 | printk(BIOS_DEBUG, "MTRR: %d base 0x%016llx mask 0x%016llx type %d\n", |
| 433 | var_state->mtrr_index, rbase, rsize, mtrr_type); |
| 434 | |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 435 | regs = &var_state->regs[var_state->mtrr_index]; |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 436 | |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 437 | regs->base.lo = rbase; |
| 438 | regs->base.lo |= mtrr_type; |
| 439 | regs->base.hi = rbase >> 32; |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 440 | |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 441 | regs->mask.lo = rsize; |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 442 | regs->mask.lo |= MTRR_PHYS_MASK_VALID; |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 443 | regs->mask.hi = rsize >> 32; |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 444 | } |
| 445 | |
Jonathan Zhang | 320ad93 | 2020-10-14 15:07:51 -0700 | [diff] [blame] | 446 | /* |
| 447 | * fls64: find least significant bit set in a 64-bit word |
| 448 | * As samples, fls64(0x0) = 64; fls64(0x4400) = 10; |
| 449 | * fls64(0x40400000000) = 34. |
| 450 | */ |
| 451 | static uint32_t fls64(uint64_t x) |
| 452 | { |
| 453 | uint32_t lo = (uint32_t)x; |
| 454 | if (lo) |
| 455 | return fls(lo); |
| 456 | uint32_t hi = x >> 32; |
| 457 | return fls(hi) + 32; |
| 458 | } |
| 459 | |
| 460 | /* |
| 461 | * fms64: find most significant bit set in a 64-bit word |
| 462 | * As samples, fms64(0x0) = 0; fms64(0x4400) = 14; |
| 463 | * fms64(0x40400000000) = 42. |
| 464 | */ |
| 465 | static uint32_t fms64(uint64_t x) |
| 466 | { |
| 467 | uint32_t hi = (uint32_t)(x >> 32); |
| 468 | if (!hi) |
| 469 | return fms((uint32_t)x); |
| 470 | return fms(hi) + 32; |
| 471 | } |
| 472 | |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 473 | static void calc_var_mtrr_range(struct var_mtrr_state *var_state, |
Jonathan Zhang | 320ad93 | 2020-10-14 15:07:51 -0700 | [diff] [blame] | 474 | uint64_t base, uint64_t size, int mtrr_type) |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 475 | { |
| 476 | while (size != 0) { |
| 477 | uint32_t addr_lsb; |
| 478 | uint32_t size_msb; |
Jonathan Zhang | 320ad93 | 2020-10-14 15:07:51 -0700 | [diff] [blame] | 479 | uint64_t mtrr_size; |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 480 | |
Jonathan Zhang | 320ad93 | 2020-10-14 15:07:51 -0700 | [diff] [blame] | 481 | addr_lsb = fls64(base); |
| 482 | size_msb = fms64(size); |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 483 | |
| 484 | /* All MTRR entries need to have their base aligned to the mask |
| 485 | * size. The maximum size is calculated by a function of the |
| 486 | * min base bit set and maximum size bit set. */ |
| 487 | if (addr_lsb > size_msb) |
Jonathan Zhang | 8f594b7 | 2020-10-23 15:20:22 -0700 | [diff] [blame] | 488 | mtrr_size = 1ULL << size_msb; |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 489 | else |
Jonathan Zhang | 8f594b7 | 2020-10-23 15:20:22 -0700 | [diff] [blame] | 490 | mtrr_size = 1ULL << addr_lsb; |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 491 | |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 492 | if (var_state->prepare_msrs) |
| 493 | prep_var_mtrr(var_state, base, mtrr_size, mtrr_type); |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 494 | |
| 495 | size -= mtrr_size; |
| 496 | base += mtrr_size; |
| 497 | var_state->mtrr_index++; |
| 498 | } |
| 499 | } |
| 500 | |
Jonathan Zhang | 320ad93 | 2020-10-14 15:07:51 -0700 | [diff] [blame] | 501 | static uint64_t optimize_var_mtrr_hole(const uint64_t base, |
| 502 | const uint64_t hole, |
Nico Huber | bd5fb66 | 2017-10-07 13:40:19 +0200 | [diff] [blame] | 503 | const uint64_t limit, |
| 504 | const int carve_hole) |
| 505 | { |
| 506 | /* |
| 507 | * With default type UC, we can potentially optimize a WB |
| 508 | * range with unaligned upper end, by aligning it up and |
| 509 | * carving the added "hole" out again. |
| 510 | * |
| 511 | * To optimize the upper end of the hole, we will test |
| 512 | * how many MTRRs calc_var_mtrr_range() will spend for any |
| 513 | * alignment of the hole's upper end. |
| 514 | * |
| 515 | * We take four parameters, the lower end of the WB range |
| 516 | * `base`, upper end of the WB range as start of the `hole`, |
| 517 | * a `limit` how far we may align the upper end of the hole |
| 518 | * up and a flag `carve_hole` whether we should count MTRRs |
| 519 | * for carving the hole out. We return the optimal upper end |
| 520 | * for the hole (which may be the same as the end of the WB |
| 521 | * range in case we don't gain anything by aligning up). |
| 522 | */ |
| 523 | |
| 524 | const int dont_care = 0; |
| 525 | struct var_mtrr_state var_state = { 0, }; |
| 526 | |
| 527 | unsigned int align, best_count; |
| 528 | uint32_t best_end = hole; |
| 529 | |
| 530 | /* calculate MTRR count for the WB range alone (w/o a hole) */ |
| 531 | calc_var_mtrr_range(&var_state, base, hole - base, dont_care); |
| 532 | best_count = var_state.mtrr_index; |
| 533 | var_state.mtrr_index = 0; |
| 534 | |
| 535 | for (align = fls(hole) + 1; align <= fms(hole); ++align) { |
| 536 | const uint64_t hole_end = ALIGN_UP((uint64_t)hole, 1 << align); |
| 537 | if (hole_end > limit) |
| 538 | break; |
| 539 | |
| 540 | /* calculate MTRR count for this alignment */ |
| 541 | calc_var_mtrr_range( |
| 542 | &var_state, base, hole_end - base, dont_care); |
| 543 | if (carve_hole) |
| 544 | calc_var_mtrr_range( |
| 545 | &var_state, hole, hole_end - hole, dont_care); |
| 546 | |
| 547 | if (var_state.mtrr_index < best_count) { |
| 548 | best_count = var_state.mtrr_index; |
| 549 | best_end = hole_end; |
| 550 | } |
| 551 | var_state.mtrr_index = 0; |
| 552 | } |
| 553 | |
| 554 | return best_end; |
| 555 | } |
| 556 | |
Aaron Durbin | e383442 | 2013-03-28 20:48:51 -0500 | [diff] [blame] | 557 | static void calc_var_mtrrs_with_hole(struct var_mtrr_state *var_state, |
Lee Leahy | a07d0dd | 2017-03-15 14:25:22 -0700 | [diff] [blame] | 558 | struct range_entry *r) |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 559 | { |
Jonathan Zhang | 320ad93 | 2020-10-14 15:07:51 -0700 | [diff] [blame] | 560 | uint64_t a1, a2, b1, b2; |
Nico Huber | bd5fb66 | 2017-10-07 13:40:19 +0200 | [diff] [blame] | 561 | int mtrr_type, carve_hole; |
Aaron Durbin | e383442 | 2013-03-28 20:48:51 -0500 | [diff] [blame] | 562 | |
| 563 | /* |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 564 | * Determine MTRRs based on the following algorithm for the given entry: |
Aaron Durbin | e383442 | 2013-03-28 20:48:51 -0500 | [diff] [blame] | 565 | * +------------------+ b2 = ALIGN_UP(end) |
| 566 | * | 0 or more bytes | <-- hole is carved out between b1 and b2 |
Nico Huber | bd5fb66 | 2017-10-07 13:40:19 +0200 | [diff] [blame] | 567 | * +------------------+ a2 = b1 = original end |
Aaron Durbin | e383442 | 2013-03-28 20:48:51 -0500 | [diff] [blame] | 568 | * | | |
| 569 | * +------------------+ a1 = begin |
| 570 | * |
Nico Huber | bd5fb66 | 2017-10-07 13:40:19 +0200 | [diff] [blame] | 571 | * Thus, there are up to 2 sub-ranges to configure variable MTRRs for. |
Aaron Durbin | e383442 | 2013-03-28 20:48:51 -0500 | [diff] [blame] | 572 | */ |
| 573 | mtrr_type = range_entry_mtrr_type(r); |
| 574 | |
| 575 | a1 = range_entry_base_mtrr_addr(r); |
| 576 | a2 = range_entry_end_mtrr_addr(r); |
| 577 | |
Aaron Durbin | a38677b | 2016-07-21 14:26:34 -0500 | [diff] [blame] | 578 | /* The end address is within the first 1MiB. The fixed MTRRs take |
Aaron Durbin | e383442 | 2013-03-28 20:48:51 -0500 | [diff] [blame] | 579 | * precedence over the variable ones. Therefore this range |
| 580 | * can be ignored. */ |
Aaron Durbin | a38677b | 2016-07-21 14:26:34 -0500 | [diff] [blame] | 581 | if (a2 <= RANGE_1MB) |
Aaron Durbin | e383442 | 2013-03-28 20:48:51 -0500 | [diff] [blame] | 582 | return; |
| 583 | |
| 584 | /* Again, the fixed MTRRs take precedence so the beginning |
Aaron Durbin | a38677b | 2016-07-21 14:26:34 -0500 | [diff] [blame] | 585 | * of the range can be set to 0 if it starts at or below 1MiB. */ |
| 586 | if (a1 <= RANGE_1MB) |
Aaron Durbin | e383442 | 2013-03-28 20:48:51 -0500 | [diff] [blame] | 587 | a1 = 0; |
| 588 | |
| 589 | /* If the range starts above 4GiB the processing is done. */ |
| 590 | if (!var_state->above4gb && a1 >= RANGE_4GB) |
| 591 | return; |
| 592 | |
| 593 | /* Clip the upper address to 4GiB if addresses above 4GiB |
| 594 | * are not being processed. */ |
| 595 | if (!var_state->above4gb && a2 > RANGE_4GB) |
| 596 | a2 = RANGE_4GB; |
| 597 | |
| 598 | b1 = a2; |
Nico Huber | 64f0bcb | 2017-10-07 16:37:04 +0200 | [diff] [blame] | 599 | b2 = a2; |
| 600 | carve_hole = 0; |
Aaron Durbin | 5392424 | 2013-03-29 11:48:27 -0500 | [diff] [blame] | 601 | |
Nico Huber | 64f0bcb | 2017-10-07 16:37:04 +0200 | [diff] [blame] | 602 | /* We only consider WB type ranges for hole-carving. */ |
| 603 | if (mtrr_type == MTRR_TYPE_WRBACK) { |
| 604 | struct range_entry *next; |
| 605 | uint64_t b2_limit; |
| 606 | /* |
| 607 | * Depending on the type of the next range, there are three |
| 608 | * different situations to handle: |
| 609 | * |
| 610 | * 1. WB range is last in address space: |
| 611 | * Aligning up, up to the next power of 2, may gain us |
| 612 | * something. |
| 613 | * |
| 614 | * 2. The next range is of type UC: |
| 615 | * We may align up, up to the _end_ of the next range. If |
| 616 | * there is a gap between the current and the next range, |
| 617 | * it would have been covered by the default type UC anyway. |
| 618 | * |
| 619 | * 3. The next range is not of type UC: |
| 620 | * We may align up, up to the _base_ of the next range. This |
| 621 | * may either be the end of the current range (if the next |
| 622 | * range follows immediately) or the end of the gap between |
| 623 | * the ranges. |
| 624 | */ |
| 625 | next = memranges_next_entry(var_state->addr_space, r); |
| 626 | if (next == NULL) { |
| 627 | b2_limit = ALIGN_UP((uint64_t)b1, 1 << fms(b1)); |
| 628 | /* If it's the last range above 4GiB, we won't carve |
| 629 | the hole out. If an OS wanted to move MMIO there, |
| 630 | it would have to override the MTRR setting using |
| 631 | PAT just like it would with WB as default type. */ |
| 632 | carve_hole = a1 < RANGE_4GB; |
| 633 | } else if (range_entry_mtrr_type(next) |
| 634 | == MTRR_TYPE_UNCACHEABLE) { |
| 635 | b2_limit = range_entry_end_mtrr_addr(next); |
| 636 | carve_hole = 1; |
| 637 | } else { |
| 638 | b2_limit = range_entry_base_mtrr_addr(next); |
| 639 | carve_hole = 1; |
| 640 | } |
| 641 | b2 = optimize_var_mtrr_hole(a1, b1, b2_limit, carve_hole); |
Aaron Durbin | 5392424 | 2013-03-29 11:48:27 -0500 | [diff] [blame] | 642 | } |
Aaron Durbin | e383442 | 2013-03-28 20:48:51 -0500 | [diff] [blame] | 643 | |
| 644 | calc_var_mtrr_range(var_state, a1, b2 - a1, mtrr_type); |
Nico Huber | bd5fb66 | 2017-10-07 13:40:19 +0200 | [diff] [blame] | 645 | if (carve_hole && b2 != b1) { |
| 646 | calc_var_mtrr_range(var_state, b1, b2 - b1, |
| 647 | MTRR_TYPE_UNCACHEABLE); |
| 648 | } |
Aaron Durbin | e383442 | 2013-03-28 20:48:51 -0500 | [diff] [blame] | 649 | } |
| 650 | |
Aaron Durbin | 5b9e3b6 | 2014-02-05 16:00:43 -0600 | [diff] [blame] | 651 | static void __calc_var_mtrrs(struct memranges *addr_space, |
Lee Leahy | a07d0dd | 2017-03-15 14:25:22 -0700 | [diff] [blame] | 652 | int above4gb, int address_bits, |
| 653 | int *num_def_wb_mtrrs, int *num_def_uc_mtrrs) |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 654 | { |
| 655 | int wb_deftype_count; |
| 656 | int uc_deftype_count; |
Aaron Durbin | e383442 | 2013-03-28 20:48:51 -0500 | [diff] [blame] | 657 | struct range_entry *r; |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 658 | struct var_mtrr_state var_state; |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 659 | |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 660 | /* The default MTRR cacheability type is determined by calculating |
Paul Menzel | 4fe9813 | 2014-01-25 15:55:28 +0100 | [diff] [blame] | 661 | * the number of MTRRs required for each MTRR type as if it was the |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 662 | * default. */ |
| 663 | var_state.addr_space = addr_space; |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 664 | var_state.above4gb = above4gb; |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 665 | var_state.address_bits = address_bits; |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 666 | var_state.prepare_msrs = 0; |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 667 | |
Aaron Durbin | e383442 | 2013-03-28 20:48:51 -0500 | [diff] [blame] | 668 | wb_deftype_count = 0; |
| 669 | uc_deftype_count = 0; |
Duncan Laurie | 7389fa9 | 2011-12-22 10:59:40 -0800 | [diff] [blame] | 670 | |
Aaron Durbin | e383442 | 2013-03-28 20:48:51 -0500 | [diff] [blame] | 671 | /* |
Nico Huber | 64f0bcb | 2017-10-07 16:37:04 +0200 | [diff] [blame] | 672 | * For each range do 2 calculations: |
| 673 | * 1. UC as default type with possible holes at top of range. |
| 674 | * 2. WB as default. |
Martin Roth | 4c3ab73 | 2013-07-08 16:23:54 -0600 | [diff] [blame] | 675 | * The lowest count is then used as default after totaling all |
Nico Huber | 64f0bcb | 2017-10-07 16:37:04 +0200 | [diff] [blame] | 676 | * MTRRs. UC takes precedence in the MTRR architecture. There- |
| 677 | * fore, only holes can be used when the type of the region is |
| 678 | * MTRR_TYPE_WRBACK with MTRR_TYPE_UNCACHEABLE as the default |
| 679 | * type. |
Aaron Durbin | e383442 | 2013-03-28 20:48:51 -0500 | [diff] [blame] | 680 | */ |
| 681 | memranges_each_entry(r, var_state.addr_space) { |
| 682 | int mtrr_type; |
| 683 | |
| 684 | mtrr_type = range_entry_mtrr_type(r); |
| 685 | |
| 686 | if (mtrr_type != MTRR_TYPE_UNCACHEABLE) { |
Aaron Durbin | e383442 | 2013-03-28 20:48:51 -0500 | [diff] [blame] | 687 | var_state.mtrr_index = 0; |
Nico Huber | 64f0bcb | 2017-10-07 16:37:04 +0200 | [diff] [blame] | 688 | var_state.def_mtrr_type = MTRR_TYPE_UNCACHEABLE; |
| 689 | calc_var_mtrrs_with_hole(&var_state, r); |
| 690 | uc_deftype_count += var_state.mtrr_index; |
Aaron Durbin | e383442 | 2013-03-28 20:48:51 -0500 | [diff] [blame] | 691 | } |
| 692 | |
| 693 | if (mtrr_type != MTRR_TYPE_WRBACK) { |
| 694 | var_state.mtrr_index = 0; |
| 695 | var_state.def_mtrr_type = MTRR_TYPE_WRBACK; |
Nico Huber | 64f0bcb | 2017-10-07 16:37:04 +0200 | [diff] [blame] | 696 | calc_var_mtrrs_with_hole(&var_state, r); |
Aaron Durbin | e383442 | 2013-03-28 20:48:51 -0500 | [diff] [blame] | 697 | wb_deftype_count += var_state.mtrr_index; |
| 698 | } |
| 699 | } |
Jonathan Zhang | 320ad93 | 2020-10-14 15:07:51 -0700 | [diff] [blame] | 700 | |
Aaron Durbin | 5b9e3b6 | 2014-02-05 16:00:43 -0600 | [diff] [blame] | 701 | *num_def_wb_mtrrs = wb_deftype_count; |
| 702 | *num_def_uc_mtrrs = uc_deftype_count; |
| 703 | } |
| 704 | |
| 705 | static int calc_var_mtrrs(struct memranges *addr_space, |
Lee Leahy | a07d0dd | 2017-03-15 14:25:22 -0700 | [diff] [blame] | 706 | int above4gb, int address_bits) |
Aaron Durbin | 5b9e3b6 | 2014-02-05 16:00:43 -0600 | [diff] [blame] | 707 | { |
| 708 | int wb_deftype_count = 0; |
| 709 | int uc_deftype_count = 0; |
| 710 | |
| 711 | __calc_var_mtrrs(addr_space, above4gb, address_bits, &wb_deftype_count, |
Lee Leahy | a07d0dd | 2017-03-15 14:25:22 -0700 | [diff] [blame] | 712 | &uc_deftype_count); |
Aaron Durbin | 5b9e3b6 | 2014-02-05 16:00:43 -0600 | [diff] [blame] | 713 | |
Tim Wawrzynczak | 6fcc46d | 2021-04-19 13:47:36 -0600 | [diff] [blame] | 714 | const int bios_mtrrs = total_mtrrs - get_os_reserved_mtrrs(); |
Aaron Durbin | 5b9e3b6 | 2014-02-05 16:00:43 -0600 | [diff] [blame] | 715 | if (wb_deftype_count > bios_mtrrs && uc_deftype_count > bios_mtrrs) { |
| 716 | printk(BIOS_DEBUG, "MTRR: Removing WRCOMB type. " |
| 717 | "WB/UC MTRR counts: %d/%d > %d.\n", |
| 718 | wb_deftype_count, uc_deftype_count, bios_mtrrs); |
| 719 | memranges_update_tag(addr_space, MTRR_TYPE_WRCOMB, |
Lee Leahy | a07d0dd | 2017-03-15 14:25:22 -0700 | [diff] [blame] | 720 | MTRR_TYPE_UNCACHEABLE); |
Aaron Durbin | 5b9e3b6 | 2014-02-05 16:00:43 -0600 | [diff] [blame] | 721 | __calc_var_mtrrs(addr_space, above4gb, address_bits, |
Lee Leahy | a07d0dd | 2017-03-15 14:25:22 -0700 | [diff] [blame] | 722 | &wb_deftype_count, &uc_deftype_count); |
Aaron Durbin | 5b9e3b6 | 2014-02-05 16:00:43 -0600 | [diff] [blame] | 723 | } |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 724 | |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 725 | printk(BIOS_DEBUG, "MTRR: default type WB/UC MTRR counts: %d/%d.\n", |
| 726 | wb_deftype_count, uc_deftype_count); |
Kyösti Mälkki | ffc1fb3 | 2012-07-11 14:40:19 +0300 | [diff] [blame] | 727 | |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 728 | if (wb_deftype_count < uc_deftype_count) { |
| 729 | printk(BIOS_DEBUG, "MTRR: WB selected as default type.\n"); |
| 730 | return MTRR_TYPE_WRBACK; |
| 731 | } |
| 732 | printk(BIOS_DEBUG, "MTRR: UC selected as default type.\n"); |
| 733 | return MTRR_TYPE_UNCACHEABLE; |
| 734 | } |
Kyösti Mälkki | ffc1fb3 | 2012-07-11 14:40:19 +0300 | [diff] [blame] | 735 | |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 736 | static void prepare_var_mtrrs(struct memranges *addr_space, int def_type, |
| 737 | int above4gb, int address_bits, |
| 738 | struct var_mtrr_solution *sol) |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 739 | { |
Aaron Durbin | e383442 | 2013-03-28 20:48:51 -0500 | [diff] [blame] | 740 | struct range_entry *r; |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 741 | struct var_mtrr_state var_state; |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 742 | |
| 743 | var_state.addr_space = addr_space; |
| 744 | var_state.above4gb = above4gb; |
| 745 | var_state.address_bits = address_bits; |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 746 | /* Prepare the MSRs. */ |
| 747 | var_state.prepare_msrs = 1; |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 748 | var_state.mtrr_index = 0; |
| 749 | var_state.def_mtrr_type = def_type; |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 750 | var_state.regs = &sol->regs[0]; |
Aaron Durbin | e383442 | 2013-03-28 20:48:51 -0500 | [diff] [blame] | 751 | |
| 752 | memranges_each_entry(r, var_state.addr_space) { |
| 753 | if (range_entry_mtrr_type(r) == def_type) |
| 754 | continue; |
Nico Huber | 64f0bcb | 2017-10-07 16:37:04 +0200 | [diff] [blame] | 755 | calc_var_mtrrs_with_hole(&var_state, r); |
Aaron Durbin | e383442 | 2013-03-28 20:48:51 -0500 | [diff] [blame] | 756 | } |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 757 | |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 758 | /* Update the solution. */ |
| 759 | sol->num_used = var_state.mtrr_index; |
| 760 | } |
| 761 | |
Aaron Durbin | d9762f7 | 2017-06-12 12:48:38 -0500 | [diff] [blame] | 762 | static int commit_var_mtrrs(const struct var_mtrr_solution *sol) |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 763 | { |
| 764 | int i; |
| 765 | |
Aaron Durbin | d9762f7 | 2017-06-12 12:48:38 -0500 | [diff] [blame] | 766 | if (sol->num_used > total_mtrrs) { |
| 767 | printk(BIOS_WARNING, "Not enough MTRRs: %d vs %d\n", |
| 768 | sol->num_used, total_mtrrs); |
| 769 | return -1; |
| 770 | } |
| 771 | |
Isaac Christensen | 81f90c5 | 2014-09-24 14:59:32 -0600 | [diff] [blame] | 772 | /* Write out the variable MTRRs. */ |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 773 | disable_cache(); |
| 774 | for (i = 0; i < sol->num_used; i++) { |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 775 | wrmsr(MTRR_PHYS_BASE(i), sol->regs[i].base); |
| 776 | wrmsr(MTRR_PHYS_MASK(i), sol->regs[i].mask); |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 777 | } |
| 778 | /* Clear the ones that are unused. */ |
| 779 | for (; i < total_mtrrs; i++) |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 780 | clear_var_mtrr(i); |
Isaac Christensen | 81f90c5 | 2014-09-24 14:59:32 -0600 | [diff] [blame] | 781 | enable_var_mtrr(sol->mtrr_default_type); |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 782 | enable_cache(); |
| 783 | |
Aaron Durbin | d9762f7 | 2017-06-12 12:48:38 -0500 | [diff] [blame] | 784 | return 0; |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 785 | } |
| 786 | |
| 787 | void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) |
| 788 | { |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 789 | static struct var_mtrr_solution *sol = NULL; |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 790 | struct memranges *addr_space; |
| 791 | |
| 792 | addr_space = get_physical_address_space(); |
| 793 | |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 794 | if (sol == NULL) { |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 795 | sol = &mtrr_global_solution; |
| 796 | sol->mtrr_default_type = |
Aaron Durbin | bb4e79a | 2013-03-26 14:09:47 -0500 | [diff] [blame] | 797 | calc_var_mtrrs(addr_space, !!above4gb, address_bits); |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 798 | prepare_var_mtrrs(addr_space, sol->mtrr_default_type, |
| 799 | !!above4gb, address_bits, sol); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 800 | } |
Stefan Reinauer | 00093a8 | 2011-11-02 16:12:34 -0700 | [diff] [blame] | 801 | |
Gabe Black | 7756fe7 | 2014-02-25 01:40:34 -0800 | [diff] [blame] | 802 | commit_var_mtrrs(sol); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 803 | } |
| 804 | |
Aaron Durbin | 1ebbb16 | 2020-05-28 10:17:34 -0600 | [diff] [blame] | 805 | static void _x86_setup_mtrrs(unsigned int above4gb) |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 806 | { |
Sven Schnelle | adfbcb79 | 2012-01-10 12:01:43 +0100 | [diff] [blame] | 807 | int address_size; |
Aaron Durbin | e63be89 | 2016-03-07 16:05:36 -0600 | [diff] [blame] | 808 | |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 809 | x86_setup_fixed_mtrrs(); |
Sven Schnelle | adfbcb79 | 2012-01-10 12:01:43 +0100 | [diff] [blame] | 810 | address_size = cpu_phys_address_size(); |
Aaron Durbin | e63be89 | 2016-03-07 16:05:36 -0600 | [diff] [blame] | 811 | printk(BIOS_DEBUG, "CPU physical address size: %d bits\n", |
| 812 | address_size); |
Aaron Durbin | 1ebbb16 | 2020-05-28 10:17:34 -0600 | [diff] [blame] | 813 | x86_setup_var_mtrrs(address_size, above4gb); |
| 814 | } |
| 815 | |
| 816 | void x86_setup_mtrrs(void) |
| 817 | { |
Tim Wawrzynczak | 6fcc46d | 2021-04-19 13:47:36 -0600 | [diff] [blame] | 818 | /* Without detect, assume the minimum */ |
| 819 | total_mtrrs = MIN_MTRRS; |
Aaron Durbin | e63be89 | 2016-03-07 16:05:36 -0600 | [diff] [blame] | 820 | /* Always handle addresses above 4GiB. */ |
Aaron Durbin | 1ebbb16 | 2020-05-28 10:17:34 -0600 | [diff] [blame] | 821 | _x86_setup_mtrrs(1); |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 822 | } |
| 823 | |
Aaron Durbin | e63be89 | 2016-03-07 16:05:36 -0600 | [diff] [blame] | 824 | void x86_setup_mtrrs_with_detect(void) |
| 825 | { |
| 826 | detect_var_mtrrs(); |
Aaron Durbin | 1ebbb16 | 2020-05-28 10:17:34 -0600 | [diff] [blame] | 827 | /* Always handle addresses above 4GiB. */ |
| 828 | _x86_setup_mtrrs(1); |
| 829 | } |
| 830 | |
| 831 | void x86_setup_mtrrs_with_detect_no_above_4gb(void) |
| 832 | { |
| 833 | detect_var_mtrrs(); |
| 834 | _x86_setup_mtrrs(0); |
Aaron Durbin | e63be89 | 2016-03-07 16:05:36 -0600 | [diff] [blame] | 835 | } |
| 836 | |
Kyösti Mälkki | 38a8fb0 | 2014-06-30 13:48:18 +0300 | [diff] [blame] | 837 | void x86_mtrr_check(void) |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 838 | { |
| 839 | /* Only Pentium Pro and later have MTRR */ |
| 840 | msr_t msr; |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 841 | printk(BIOS_DEBUG, "\nMTRR check\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 842 | |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 843 | msr = rdmsr(MTRR_DEF_TYPE_MSR); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 844 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 845 | printk(BIOS_DEBUG, "Fixed MTRRs : "); |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 846 | if (msr.lo & MTRR_DEF_TYPE_FIX_EN) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 847 | printk(BIOS_DEBUG, "Enabled\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 848 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 849 | printk(BIOS_DEBUG, "Disabled\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 850 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 851 | printk(BIOS_DEBUG, "Variable MTRRs: "); |
Alexandru Gagniuc | 86091f9 | 2015-09-30 20:23:09 -0700 | [diff] [blame] | 852 | if (msr.lo & MTRR_DEF_TYPE_EN) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 853 | printk(BIOS_DEBUG, "Enabled\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 854 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 855 | printk(BIOS_DEBUG, "Disabled\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 856 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 857 | printk(BIOS_DEBUG, "\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 858 | |
| 859 | post_code(0x93); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 860 | } |
Aaron Durbin | 2bebd7b | 2016-11-10 15:15:35 -0600 | [diff] [blame] | 861 | |
| 862 | static bool put_back_original_solution; |
| 863 | |
Kane Chen | 00aaffa | 2022-04-07 21:02:09 +0800 | [diff] [blame] | 864 | void need_restore_mtrr(void) |
| 865 | { |
| 866 | put_back_original_solution = true; |
| 867 | } |
| 868 | |
Aaron Durbin | 2bebd7b | 2016-11-10 15:15:35 -0600 | [diff] [blame] | 869 | void mtrr_use_temp_range(uintptr_t begin, size_t size, int type) |
| 870 | { |
| 871 | const struct range_entry *r; |
| 872 | const struct memranges *orig; |
| 873 | struct var_mtrr_solution sol; |
| 874 | struct memranges addr_space; |
| 875 | const int above4gb = 1; /* Cover above 4GiB by default. */ |
| 876 | int address_bits; |
Arthur Heymans | 4ed2260 | 2022-04-11 18:58:09 +0200 | [diff] [blame^] | 877 | static struct temp_range { |
| 878 | uintptr_t begin; |
| 879 | size_t size; |
| 880 | int type; |
| 881 | } temp_ranges[10]; |
| 882 | |
| 883 | if (size == 0) |
| 884 | return; |
| 885 | |
| 886 | int i; |
| 887 | for (i = 0; i < ARRAY_SIZE(temp_ranges); i++) { |
| 888 | if (temp_ranges[i].size == 0) { |
| 889 | temp_ranges[i].begin = begin; |
| 890 | temp_ranges[i].size = size; |
| 891 | temp_ranges[i].type = type; |
| 892 | break; |
| 893 | } |
| 894 | } |
| 895 | if (i == ARRAY_SIZE(temp_ranges)) { |
| 896 | printk(BIOS_ERR, "Out of temporary ranges for MTRR use\n"); |
| 897 | return; |
| 898 | } |
Aaron Durbin | 2bebd7b | 2016-11-10 15:15:35 -0600 | [diff] [blame] | 899 | |
| 900 | /* Make a copy of the original address space and tweak it with the |
| 901 | * provided range. */ |
| 902 | memranges_init_empty(&addr_space, NULL, 0); |
| 903 | orig = get_physical_address_space(); |
| 904 | memranges_each_entry(r, orig) { |
| 905 | unsigned long tag = range_entry_tag(r); |
| 906 | |
Aaron Durbin | 2bebd7b | 2016-11-10 15:15:35 -0600 | [diff] [blame] | 907 | /* Remove any write combining MTRRs from the temporary |
| 908 | * solution as it just fragments the address space. */ |
| 909 | if (tag == MTRR_TYPE_WRCOMB) |
| 910 | tag = MTRR_TYPE_UNCACHEABLE; |
| 911 | |
| 912 | memranges_insert(&addr_space, range_entry_base(r), |
| 913 | range_entry_size(r), tag); |
| 914 | } |
| 915 | |
| 916 | /* Place new range into the address space. */ |
Arthur Heymans | 4ed2260 | 2022-04-11 18:58:09 +0200 | [diff] [blame^] | 917 | for (i = 0; i < ARRAY_SIZE(temp_ranges); i++) { |
| 918 | if (temp_ranges[i].size != 0) |
| 919 | memranges_insert(&addr_space, temp_ranges[i].begin, |
| 920 | temp_ranges[i].size, temp_ranges[i].type); |
| 921 | } |
Aaron Durbin | 2bebd7b | 2016-11-10 15:15:35 -0600 | [diff] [blame] | 922 | |
| 923 | print_physical_address_space(&addr_space, "TEMPORARY"); |
| 924 | |
| 925 | /* Calculate a new solution with the updated address space. */ |
| 926 | address_bits = cpu_phys_address_size(); |
| 927 | memset(&sol, 0, sizeof(sol)); |
| 928 | sol.mtrr_default_type = |
| 929 | calc_var_mtrrs(&addr_space, above4gb, address_bits); |
| 930 | prepare_var_mtrrs(&addr_space, sol.mtrr_default_type, |
| 931 | above4gb, address_bits, &sol); |
Aaron Durbin | d9762f7 | 2017-06-12 12:48:38 -0500 | [diff] [blame] | 932 | |
| 933 | if (commit_var_mtrrs(&sol) < 0) |
| 934 | printk(BIOS_WARNING, "Unable to insert temporary MTRR range: 0x%016llx - 0x%016llx size 0x%08llx type %d\n", |
Werner Zeh | eaf11c9 | 2022-04-11 08:35:06 +0200 | [diff] [blame] | 935 | (long long)begin, (long long)begin + size - 1, |
Aaron Durbin | d9762f7 | 2017-06-12 12:48:38 -0500 | [diff] [blame] | 936 | (long long)size, type); |
| 937 | else |
Subrata Banik | 3e4e4ab | 2022-04-08 13:25:49 +0530 | [diff] [blame] | 938 | need_restore_mtrr(); |
Aaron Durbin | 2bebd7b | 2016-11-10 15:15:35 -0600 | [diff] [blame] | 939 | |
| 940 | memranges_teardown(&addr_space); |
Aaron Durbin | 2bebd7b | 2016-11-10 15:15:35 -0600 | [diff] [blame] | 941 | } |
| 942 | |
| 943 | static void remove_temp_solution(void *unused) |
| 944 | { |
| 945 | if (put_back_original_solution) |
| 946 | commit_var_mtrrs(&mtrr_global_solution); |
| 947 | } |
| 948 | |
| 949 | BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, remove_temp_solution, NULL); |
Subrata Banik | 1f09a2a | 2022-03-31 00:06:07 +0530 | [diff] [blame] | 950 | BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, remove_temp_solution, NULL); |