Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | cdc5cc6 | 2007-04-24 18:40:02 +0000 | [diff] [blame] | 2 | * mtrr.c: setting MTRR to decent values for cache initialization on P6 |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 3 | * |
| 4 | * Derived from intel_set_mtrr in intel_subr.c and mtrr.c in linux kernel |
| 5 | * |
| 6 | * Copyright 2000 Silicon Integrated System Corporation |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 21 | * |
| 22 | * |
| 23 | * Reference: Intel Architecture Software Developer's Manual, Volume 3: System Programming |
| 24 | */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 25 | |
Yinghai Lu | 953e0f6 | 2005-01-06 04:55:19 +0000 | [diff] [blame] | 26 | /* |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 27 | 2005.1 yhlu add NC support to spare mtrrs for 64G memory above installed |
| 28 | 2005.6 Eric add address bit in x86_setup_mtrrs |
| 29 | 2005.6 yhlu split x86_setup_var_mtrrs and x86_setup_fixed_mtrrs, |
| 30 | for AMD, it will not use x86_setup_fixed_mtrrs |
Yinghai Lu | 953e0f6 | 2005-01-06 04:55:19 +0000 | [diff] [blame] | 31 | */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 32 | |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 33 | #include <stddef.h> |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 34 | #include <console/console.h> |
| 35 | #include <device/device.h> |
| 36 | #include <cpu/x86/msr.h> |
| 37 | #include <cpu/x86/mtrr.h> |
| 38 | #include <cpu/x86/cache.h> |
Stefan Reinauer | 00093a8 | 2011-11-02 16:12:34 -0700 | [diff] [blame^] | 39 | #include <cpu/x86/lapic.h> |
Sven Schnelle | adfbcb79 | 2012-01-10 12:01:43 +0100 | [diff] [blame] | 40 | #include <arch/cpu.h> |
Stefan Reinauer | 00093a8 | 2011-11-02 16:12:34 -0700 | [diff] [blame^] | 41 | #include <arch/acpi.h> |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 42 | |
Myles Watson | ec0ee64 | 2009-10-19 16:21:30 +0000 | [diff] [blame] | 43 | #if CONFIG_GFXUMA |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 44 | extern uint64_t uma_memory_base, uma_memory_size; |
| 45 | #endif |
| 46 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 47 | static unsigned int mtrr_msr[] = { |
| 48 | MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR, |
| 49 | MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR, |
| 50 | MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR, |
| 51 | }; |
| 52 | |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 53 | void enable_fixed_mtrr(void) |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 54 | { |
| 55 | msr_t msr; |
| 56 | |
| 57 | msr = rdmsr(MTRRdefType_MSR); |
| 58 | msr.lo |= 0xc00; |
| 59 | wrmsr(MTRRdefType_MSR, msr); |
| 60 | } |
| 61 | |
| 62 | static void enable_var_mtrr(void) |
| 63 | { |
| 64 | msr_t msr; |
| 65 | |
| 66 | msr = rdmsr(MTRRdefType_MSR); |
Kevin O'Connor | 5bb9fd6 | 2011-01-19 06:32:35 +0000 | [diff] [blame] | 67 | msr.lo |= MTRRdefTypeEn; |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 68 | wrmsr(MTRRdefType_MSR, msr); |
| 69 | } |
| 70 | |
| 71 | /* setting variable mtrr, comes from linux kernel source */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 72 | static void set_var_mtrr( |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 73 | unsigned int reg, unsigned long basek, unsigned long sizek, |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 74 | unsigned char type, unsigned address_bits) |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 75 | { |
| 76 | msr_t base, mask; |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 77 | unsigned address_mask_high; |
| 78 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 79 | if (reg >= 8) |
| 80 | return; |
| 81 | |
| 82 | // it is recommended that we disable and enable cache when we |
| 83 | // do this. |
| 84 | if (sizek == 0) { |
| 85 | disable_cache(); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 86 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 87 | msr_t zero; |
| 88 | zero.lo = zero.hi = 0; |
| 89 | /* The invalid bit is kept in the mask, so we simply clear the |
| 90 | relevant mask register to disable a range. */ |
| 91 | wrmsr (MTRRphysMask_MSR(reg), zero); |
| 92 | |
| 93 | enable_cache(); |
| 94 | return; |
| 95 | } |
| 96 | |
| 97 | |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 98 | address_mask_high = ((1u << (address_bits - 32u)) - 1u); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 99 | |
| 100 | base.hi = basek >> 22; |
| 101 | base.lo = basek << 10; |
| 102 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 103 | printk(BIOS_SPEW, "ADDRESS_MASK_HIGH=%#x\n", address_mask_high); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 104 | |
| 105 | if (sizek < 4*1024*1024) { |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 106 | mask.hi = address_mask_high; |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 107 | mask.lo = ~((sizek << 10) -1); |
| 108 | } |
| 109 | else { |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 110 | mask.hi = address_mask_high & (~((sizek >> 22) -1)); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 111 | mask.lo = 0; |
| 112 | } |
| 113 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 114 | // it is recommended that we disable and enable cache when we |
| 115 | // do this. |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 116 | disable_cache(); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 117 | |
| 118 | /* Bit 32-35 of MTRRphysMask should be set to 1 */ |
| 119 | base.lo |= type; |
Kevin O'Connor | 5bb9fd6 | 2011-01-19 06:32:35 +0000 | [diff] [blame] | 120 | mask.lo |= MTRRphysMaskValid; |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 121 | wrmsr (MTRRphysBase_MSR(reg), base); |
| 122 | wrmsr (MTRRphysMask_MSR(reg), mask); |
| 123 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 124 | enable_cache(); |
| 125 | } |
| 126 | |
| 127 | /* fms: find most sigificant bit set, stolen from Linux Kernel Source. */ |
| 128 | static inline unsigned int fms(unsigned int x) |
| 129 | { |
| 130 | int r; |
| 131 | |
| 132 | __asm__("bsrl %1,%0\n\t" |
| 133 | "jnz 1f\n\t" |
| 134 | "movl $0,%0\n" |
| 135 | "1:" : "=r" (r) : "g" (x)); |
| 136 | return r; |
| 137 | } |
| 138 | |
Marc Jones | 5cbdc1e | 2009-04-01 22:07:53 +0000 | [diff] [blame] | 139 | /* fls: find least sigificant bit set */ |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 140 | static inline unsigned int fls(unsigned int x) |
| 141 | { |
| 142 | int r; |
| 143 | |
| 144 | __asm__("bsfl %1,%0\n\t" |
| 145 | "jnz 1f\n\t" |
| 146 | "movl $32,%0\n" |
| 147 | "1:" : "=r" (r) : "g" (x)); |
| 148 | return r; |
| 149 | } |
| 150 | |
| 151 | /* setting up variable and fixed mtrr |
| 152 | * |
| 153 | * From Intel Vol. III Section 9.12.4, the Range Size and Base Alignment has some kind of requirement: |
| 154 | * 1. The range size must be 2^N byte for N >= 12 (i.e 4KB minimum). |
| 155 | * 2. The base address must be 2^N aligned, where the N here is equal to the N in previous |
| 156 | * requirement. So a 8K range must be 8K aligned not 4K aligned. |
| 157 | * |
| 158 | * These requirement is meet by "decompositing" the ramsize into Sum(Cn * 2^n, n = [0..N], Cn = [0, 1]). |
| 159 | * For Cm = 1, there is a WB range of 2^m size at base address Sum(Cm * 2^m, m = [N..n]). |
| 160 | * A 124MB (128MB - 4MB SMA) example: |
| 161 | * ramsize = 124MB == 64MB (at 0MB) + 32MB (at 64MB) + 16MB (at 96MB ) + 8MB (at 112MB) + 4MB (120MB). |
| 162 | * But this wastes a lot of MTRR registers so we use another more "aggresive" way with Uncacheable Regions. |
| 163 | * |
| 164 | * In the Uncacheable Region scheme, we try to cover the whole ramsize by one WB region as possible, |
| 165 | * If (an only if) this can not be done we will try to decomposite the ramesize, the mathematical formula |
| 166 | * whould be ramsize = Sum(Cn * 2^n, n = [0..N], Cn = [-1, 0, 1]). For Cn = -1, a Uncachable Region is used. |
| 167 | * The same 124MB example: |
| 168 | * ramsize = 124MB == 128MB WB (at 0MB) + 4MB UC (at 124MB) |
| 169 | * or a 156MB (128MB + 32MB - 4MB SMA) example: |
| 170 | * ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB) |
| 171 | */ |
| 172 | /* 2 MTRRS are reserved for the operating system */ |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 173 | #if 1 |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 174 | #define BIOS_MTRRS 6 |
| 175 | #define OS_MTRRS 2 |
| 176 | #else |
| 177 | #define BIOS_MTRRS 8 |
| 178 | #define OS_MTRRS 0 |
| 179 | #endif |
| 180 | #define MTRRS (BIOS_MTRRS + OS_MTRRS) |
| 181 | |
| 182 | |
| 183 | static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type) |
| 184 | { |
| 185 | unsigned int i; |
| 186 | unsigned int fixed_msr = NUM_FIXED_RANGES >> 3; |
| 187 | msr_t msr; |
| 188 | msr.lo = msr.hi = 0; /* Shut up gcc */ |
| 189 | for(i = first; i < last; i++) { |
| 190 | /* When I switch to a new msr read it in */ |
| 191 | if (fixed_msr != i >> 3) { |
| 192 | /* But first write out the old msr */ |
| 193 | if (fixed_msr < (NUM_FIXED_RANGES >> 3)) { |
| 194 | disable_cache(); |
| 195 | wrmsr(mtrr_msr[fixed_msr], msr); |
| 196 | enable_cache(); |
| 197 | } |
| 198 | fixed_msr = i>>3; |
| 199 | msr = rdmsr(mtrr_msr[fixed_msr]); |
| 200 | } |
| 201 | if ((i & 7) < 4) { |
| 202 | msr.lo &= ~(0xff << ((i&3)*8)); |
| 203 | msr.lo |= type << ((i&3)*8); |
| 204 | } else { |
| 205 | msr.hi &= ~(0xff << ((i&3)*8)); |
| 206 | msr.hi |= type << ((i&3)*8); |
| 207 | } |
| 208 | } |
| 209 | /* Write out the final msr */ |
| 210 | if (fixed_msr < (NUM_FIXED_RANGES >> 3)) { |
| 211 | disable_cache(); |
| 212 | wrmsr(mtrr_msr[fixed_msr], msr); |
| 213 | enable_cache(); |
| 214 | } |
| 215 | } |
| 216 | |
| 217 | static unsigned fixed_mtrr_index(unsigned long addrk) |
| 218 | { |
| 219 | unsigned index; |
| 220 | index = (addrk - 0) >> 6; |
| 221 | if (index >= 8) { |
| 222 | index = ((addrk - 8*64) >> 4) + 8; |
| 223 | } |
| 224 | if (index >= 24) { |
| 225 | index = ((addrk - (8*64 + 16*16)) >> 2) + 24; |
| 226 | } |
| 227 | if (index > NUM_FIXED_RANGES) { |
| 228 | index = NUM_FIXED_RANGES; |
| 229 | } |
| 230 | return index; |
| 231 | } |
| 232 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 233 | static unsigned int range_to_mtrr(unsigned int reg, |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 234 | unsigned long range_startk, unsigned long range_sizek, |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 235 | unsigned long next_range_startk, unsigned char type, |
| 236 | unsigned int address_bits, unsigned int above4gb) |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 237 | { |
Carl-Daniel Hailfinger | 7dde1da | 2009-02-11 16:57:32 +0000 | [diff] [blame] | 238 | if (!range_sizek) { |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 239 | /* If there's no MTRR hole, this function will bail out |
| 240 | * here when called for the hole. |
| 241 | */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 242 | printk(BIOS_SPEW, "Zero-sized MTRR range @%ldKB\n", range_startk); |
Carl-Daniel Hailfinger | 7dde1da | 2009-02-11 16:57:32 +0000 | [diff] [blame] | 243 | return reg; |
| 244 | } |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 245 | |
Carl-Daniel Hailfinger | 7dde1da | 2009-02-11 16:57:32 +0000 | [diff] [blame] | 246 | if (reg >= BIOS_MTRRS) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 247 | printk(BIOS_ERR, "Warning: Out of MTRRs for base: %4ldMB, range: %ldMB, type %s\n", |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 248 | range_startk >>10, range_sizek >> 10, |
| 249 | (type==MTRR_TYPE_UNCACHEABLE)?"UC": |
| 250 | ((type==MTRR_TYPE_WRBACK)?"WB":"Other") ); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 251 | return reg; |
| 252 | } |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 253 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 254 | while(range_sizek) { |
| 255 | unsigned long max_align, align; |
| 256 | unsigned long sizek; |
| 257 | /* Compute the maximum size I can make a range */ |
| 258 | max_align = fls(range_startk); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 259 | align = fms(range_sizek); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 260 | if (align > max_align) { |
| 261 | align = max_align; |
| 262 | } |
| 263 | sizek = 1 << align; |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 264 | printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n", |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 265 | reg, range_startk >>10, sizek >> 10, |
| 266 | (type==MTRR_TYPE_UNCACHEABLE)?"UC": |
| 267 | ((type==MTRR_TYPE_WRBACK)?"WB":"Other") |
Yinghai Lu | 6360187 | 2005-01-27 22:48:12 +0000 | [diff] [blame] | 268 | ); |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 269 | |
| 270 | /* if range is above 4GB, MTRR is needed |
| 271 | * only if above4gb flag is set |
| 272 | */ |
| 273 | if (range_startk < 0x100000000ull / 1024 || above4gb) |
| 274 | set_var_mtrr(reg++, range_startk, sizek, type, address_bits); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 275 | range_startk += sizek; |
| 276 | range_sizek -= sizek; |
Carl-Daniel Hailfinger | 7dde1da | 2009-02-11 16:57:32 +0000 | [diff] [blame] | 277 | if (reg >= BIOS_MTRRS) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 278 | printk(BIOS_ERR, "Running out of variable MTRRs!\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 279 | break; |
Carl-Daniel Hailfinger | 7dde1da | 2009-02-11 16:57:32 +0000 | [diff] [blame] | 280 | } |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 281 | } |
| 282 | return reg; |
| 283 | } |
| 284 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 285 | static unsigned long resk(uint64_t value) |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 286 | { |
| 287 | unsigned long resultk; |
| 288 | if (value < (1ULL << 42)) { |
| 289 | resultk = value >> 10; |
| 290 | } |
| 291 | else { |
| 292 | resultk = 0xffffffff; |
| 293 | } |
| 294 | return resultk; |
| 295 | } |
| 296 | |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 297 | static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resource *res) |
| 298 | { |
| 299 | unsigned int start_mtrr; |
| 300 | unsigned int last_mtrr; |
| 301 | start_mtrr = fixed_mtrr_index(resk(res->base)); |
| 302 | last_mtrr = fixed_mtrr_index(resk((res->base + res->size))); |
| 303 | if (start_mtrr >= NUM_FIXED_RANGES) { |
| 304 | return; |
| 305 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 306 | printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: WB\n", |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 307 | start_mtrr, last_mtrr); |
| 308 | set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 309 | |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 310 | } |
| 311 | |
Yinghai Lu | 21332b8 | 2007-04-06 19:49:05 +0000 | [diff] [blame] | 312 | #ifndef CONFIG_VAR_MTRR_HOLE |
| 313 | #define CONFIG_VAR_MTRR_HOLE 1 |
| 314 | #endif |
| 315 | |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 316 | struct var_mtrr_state { |
| 317 | unsigned long range_startk, range_sizek; |
| 318 | unsigned int reg; |
Yinghai Lu | 6360187 | 2005-01-27 22:48:12 +0000 | [diff] [blame] | 319 | unsigned long hole_startk, hole_sizek; |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 320 | unsigned int address_bits; |
| 321 | unsigned int above4gb; /* Set if MTRRs are needed for DRAM above 4GB */ |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 322 | }; |
| 323 | |
| 324 | void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res) |
| 325 | { |
| 326 | struct var_mtrr_state *state = gp; |
| 327 | unsigned long basek, sizek; |
| 328 | if (state->reg >= BIOS_MTRRS) |
| 329 | return; |
| 330 | basek = resk(res->base); |
| 331 | sizek = resk(res->size); |
| 332 | /* See if I can merge with the last range |
| 333 | * Either I am below 1M and the fixed mtrrs handle it, or |
| 334 | * the ranges touch. |
| 335 | */ |
| 336 | if ((basek <= 1024) || (state->range_startk + state->range_sizek == basek)) { |
| 337 | unsigned long endk = basek + sizek; |
| 338 | state->range_sizek = endk - state->range_startk; |
| 339 | return; |
| 340 | } |
| 341 | /* Write the range mtrrs */ |
| 342 | if (state->range_sizek != 0) { |
Yinghai Lu | 21332b8 | 2007-04-06 19:49:05 +0000 | [diff] [blame] | 343 | #if CONFIG_VAR_MTRR_HOLE |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 344 | if (state->hole_sizek == 0) { |
| 345 | /* We need to put that on to hole */ |
| 346 | unsigned long endk = basek + sizek; |
Yinghai Lu | 6360187 | 2005-01-27 22:48:12 +0000 | [diff] [blame] | 347 | state->hole_startk = state->range_startk + state->range_sizek; |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 348 | state->hole_sizek = basek - state->hole_startk; |
| 349 | state->range_sizek = endk - state->range_startk; |
Yinghai Lu | 6360187 | 2005-01-27 22:48:12 +0000 | [diff] [blame] | 350 | return; |
| 351 | } |
Yinghai Lu | 21332b8 | 2007-04-06 19:49:05 +0000 | [diff] [blame] | 352 | #endif |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 353 | state->reg = range_to_mtrr(state->reg, state->range_startk, |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 354 | state->range_sizek, basek, MTRR_TYPE_WRBACK, |
| 355 | state->address_bits, state->above4gb); |
Yinghai Lu | 21332b8 | 2007-04-06 19:49:05 +0000 | [diff] [blame] | 356 | #if CONFIG_VAR_MTRR_HOLE |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 357 | state->reg = range_to_mtrr(state->reg, state->hole_startk, |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 358 | state->hole_sizek, basek, MTRR_TYPE_UNCACHEABLE, |
| 359 | state->address_bits, state->above4gb); |
Yinghai Lu | 21332b8 | 2007-04-06 19:49:05 +0000 | [diff] [blame] | 360 | #endif |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 361 | state->range_startk = 0; |
| 362 | state->range_sizek = 0; |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 363 | state->hole_startk = 0; |
| 364 | state->hole_sizek = 0; |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 365 | } |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 366 | /* Allocate an msr */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 367 | printk(BIOS_SPEW, " Allocate an msr - basek = %08lx, sizek = %08lx,\n", basek, sizek); |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 368 | state->range_startk = basek; |
| 369 | state->range_sizek = sizek; |
| 370 | } |
| 371 | |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 372 | void x86_setup_fixed_mtrrs(void) |
| 373 | { |
| 374 | /* Try this the simple way of incrementally adding together |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 375 | * mtrrs. If this doesn't work out we can get smart again |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 376 | * and clear out the mtrrs. |
| 377 | */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 378 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 379 | printk(BIOS_DEBUG, "\n"); |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 380 | /* Initialized the fixed_mtrrs to uncached */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 381 | printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: UC\n", |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 382 | 0, NUM_FIXED_RANGES); |
| 383 | set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE); |
| 384 | |
| 385 | /* Now see which of the fixed mtrrs cover ram. |
| 386 | */ |
| 387 | search_global_resources( |
| 388 | IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, |
| 389 | set_fixed_mtrr_resource, NULL); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 390 | printk(BIOS_DEBUG, "DONE fixed MTRRs\n"); |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 391 | |
| 392 | /* enable fixed MTRR */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 393 | printk(BIOS_SPEW, "call enable_fixed_mtrr()\n"); |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 394 | enable_fixed_mtrr(); |
| 395 | |
| 396 | } |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 397 | |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 398 | void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 399 | /* this routine needs to know how many address bits a given processor |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 400 | * supports. CPUs get grumpy when you set too many bits in |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 401 | * their mtrr registers :( I would generically call cpuid here |
| 402 | * and find out how many physically supported but some cpus are |
| 403 | * buggy, and report more bits then they actually support. |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 404 | * If above4gb flag is set, variable MTRR ranges must be used to |
| 405 | * set cacheability of DRAM above 4GB. If above4gb flag is clear, |
| 406 | * some other mechanism is controlling cacheability of DRAM above 4GB. |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 407 | */ |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 408 | { |
| 409 | /* Try this the simple way of incrementally adding together |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 410 | * mtrrs. If this doesn't work out we can get smart again |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 411 | * and clear out the mtrrs. |
| 412 | */ |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 413 | struct var_mtrr_state var_state; |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 414 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 415 | /* Cache as many memory areas as possible */ |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 416 | /* FIXME is there an algorithm for computing the optimal set of mtrrs? |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 417 | * In some cases it is definitely possible to do better. |
| 418 | */ |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 419 | var_state.range_startk = 0; |
| 420 | var_state.range_sizek = 0; |
Yinghai Lu | 6360187 | 2005-01-27 22:48:12 +0000 | [diff] [blame] | 421 | var_state.hole_startk = 0; |
| 422 | var_state.hole_sizek = 0; |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 423 | var_state.reg = 0; |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 424 | var_state.address_bits = address_bits; |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 425 | var_state.above4gb = above4gb; |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 426 | |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 427 | search_global_resources( |
| 428 | IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, |
| 429 | set_var_mtrr_resource, &var_state); |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 430 | |
Zheng Bao | edee9eb | 2009-08-11 03:18:11 +0000 | [diff] [blame] | 431 | #if (CONFIG_GFXUMA == 1) /* UMA or SP. */ |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 432 | /* For now we assume the UMA space is at the end of memory below 4GB */ |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 433 | if (var_state.hole_startk || var_state.hole_sizek) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 434 | printk(BIOS_DEBUG, "Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.\n"); |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 435 | } else { |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 436 | #if CONFIG_VAR_MTRR_HOLE |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 437 | // Increase the base range and set up UMA as an UC hole instead |
| 438 | var_state.range_sizek += (uma_memory_size >> 10); |
Yinghai Lu | 953e0f6 | 2005-01-06 04:55:19 +0000 | [diff] [blame] | 439 | |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 440 | var_state.hole_startk = (uma_memory_base >> 10); |
| 441 | var_state.hole_sizek = (uma_memory_size >> 10); |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 442 | #endif |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 443 | } |
| 444 | #endif |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 445 | /* Write the last range */ |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 446 | var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk, |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 447 | var_state.range_sizek, 0, MTRR_TYPE_WRBACK, |
| 448 | var_state.address_bits, var_state.above4gb); |
Yinghai Lu | 21332b8 | 2007-04-06 19:49:05 +0000 | [diff] [blame] | 449 | #if CONFIG_VAR_MTRR_HOLE |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 450 | var_state.reg = range_to_mtrr(var_state.reg, var_state.hole_startk, |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 451 | var_state.hole_sizek, 0, MTRR_TYPE_UNCACHEABLE, |
| 452 | var_state.address_bits, var_state.above4gb); |
Yinghai Lu | 21332b8 | 2007-04-06 19:49:05 +0000 | [diff] [blame] | 453 | #endif |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 454 | printk(BIOS_DEBUG, "DONE variable MTRRs\n"); |
| 455 | printk(BIOS_DEBUG, "Clear out the extra MTRR's\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 456 | /* Clear out the extra MTRR's */ |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 457 | while(var_state.reg < MTRRS) { |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 458 | set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 459 | } |
Stefan Reinauer | 00093a8 | 2011-11-02 16:12:34 -0700 | [diff] [blame^] | 460 | |
| 461 | #if CONFIG_CACHE_ROM |
| 462 | /* Enable Caching and speculative Reads for the |
| 463 | * complete ROM now that we actually have RAM. |
| 464 | */ |
| 465 | if (boot_cpu() && (acpi_slp_type != 3)) { |
| 466 | set_var_mtrr(7, (4096-4)*1024, 4*1024, |
| 467 | MTRR_TYPE_WRPROT, address_bits); |
| 468 | } |
| 469 | #endif |
| 470 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 471 | printk(BIOS_SPEW, "call enable_var_mtrr()\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 472 | enable_var_mtrr(); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 473 | printk(BIOS_SPEW, "Leave %s\n", __func__); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 474 | post_code(0x6A); |
| 475 | } |
| 476 | |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 477 | |
Sven Schnelle | adfbcb79 | 2012-01-10 12:01:43 +0100 | [diff] [blame] | 478 | void x86_setup_mtrrs(void) |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 479 | { |
Sven Schnelle | adfbcb79 | 2012-01-10 12:01:43 +0100 | [diff] [blame] | 480 | int address_size; |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 481 | x86_setup_fixed_mtrrs(); |
Sven Schnelle | adfbcb79 | 2012-01-10 12:01:43 +0100 | [diff] [blame] | 482 | address_size = cpu_phys_address_size(); |
| 483 | printk(BIOS_DEBUG, "CPU physical address size: %d bits\n", address_size); |
| 484 | x86_setup_var_mtrrs(address_size, 1); |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 485 | } |
| 486 | |
| 487 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 488 | int x86_mtrr_check(void) |
| 489 | { |
| 490 | /* Only Pentium Pro and later have MTRR */ |
| 491 | msr_t msr; |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 492 | printk(BIOS_DEBUG, "\nMTRR check\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 493 | |
| 494 | msr = rdmsr(0x2ff); |
| 495 | msr.lo >>= 10; |
| 496 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 497 | printk(BIOS_DEBUG, "Fixed MTRRs : "); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 498 | if (msr.lo & 0x01) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 499 | printk(BIOS_DEBUG, "Enabled\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 500 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 501 | printk(BIOS_DEBUG, "Disabled\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 502 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 503 | printk(BIOS_DEBUG, "Variable MTRRs: "); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 504 | if (msr.lo & 0x02) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 505 | printk(BIOS_DEBUG, "Enabled\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 506 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 507 | printk(BIOS_DEBUG, "Disabled\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 508 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 509 | printk(BIOS_DEBUG, "\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 510 | |
| 511 | post_code(0x93); |
| 512 | return ((int) msr.lo); |
| 513 | } |