x86/mtrr: Enable MTRR's before enabling caching
Fix up the following commit by enabling the MTRR's before enabling caching.
7756fe7 x86: Minimize work done with the caches disabled in mtrr functions.
Also fix two typos in comments.
Change-Id: If751b815f9dab781fc38c898cf692f0940c57695
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6969
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index e0392f7..69cd2d2 100644
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -51,8 +51,8 @@
#define OS_MTRRS 2
#define MTRRS (BIOS_MTRRS + OS_MTRRS)
/*
- * Static storage size for variable MTRRs. Its sized sufficiently large to
- * handle different types of CPUs. Empiricially, 16 variable MTRRs has not
+ * Static storage size for variable MTRRs. It's sized sufficiently large to
+ * handle different types of CPUs. Empirically, 16 variable MTRRs has not
* yet been observed.
*/
#define NUM_MTRR_STATIC_STORAGE 16
@@ -769,7 +769,7 @@
{
int i;
- /* Write out the variable MTTRs. */
+ /* Write out the variable MTRRs. */
disable_cache();
for (i = 0; i < sol->num_used; i++) {
wrmsr(MTRRphysBase_MSR(i), sol->regs[i].base);
@@ -778,6 +778,7 @@
/* Clear the ones that are unused. */
for (; i < total_mtrrs; i++)
clear_var_mtrr(i);
+ enable_var_mtrr(sol->mtrr_default_type);
enable_cache();
}
@@ -800,7 +801,6 @@
}
commit_var_mtrrs(sol);
- enable_var_mtrr(sol->mtrr_default_type);
}
void x86_setup_mtrrs(void)