Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | cdc5cc6 | 2007-04-24 18:40:02 +0000 | [diff] [blame] | 2 | * mtrr.c: setting MTRR to decent values for cache initialization on P6 |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 3 | * |
| 4 | * Derived from intel_set_mtrr in intel_subr.c and mtrr.c in linux kernel |
| 5 | * |
| 6 | * Copyright 2000 Silicon Integrated System Corporation |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 21 | * |
| 22 | * |
| 23 | * Reference: Intel Architecture Software Developer's Manual, Volume 3: System Programming |
| 24 | */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 25 | |
Yinghai Lu | 953e0f6 | 2005-01-06 04:55:19 +0000 | [diff] [blame] | 26 | /* |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 27 | 2005.1 yhlu add NC support to spare mtrrs for 64G memory above installed |
| 28 | 2005.6 Eric add address bit in x86_setup_mtrrs |
| 29 | 2005.6 yhlu split x86_setup_var_mtrrs and x86_setup_fixed_mtrrs, |
| 30 | for AMD, it will not use x86_setup_fixed_mtrrs |
Yinghai Lu | 953e0f6 | 2005-01-06 04:55:19 +0000 | [diff] [blame] | 31 | */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 32 | |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 33 | #include <stddef.h> |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 34 | #include <console/console.h> |
| 35 | #include <device/device.h> |
| 36 | #include <cpu/x86/msr.h> |
| 37 | #include <cpu/x86/mtrr.h> |
| 38 | #include <cpu/x86/cache.h> |
Stefan Reinauer | 00093a8 | 2011-11-02 16:12:34 -0700 | [diff] [blame] | 39 | #include <cpu/x86/lapic.h> |
Sven Schnelle | adfbcb79 | 2012-01-10 12:01:43 +0100 | [diff] [blame] | 40 | #include <arch/cpu.h> |
Stefan Reinauer | 00093a8 | 2011-11-02 16:12:34 -0700 | [diff] [blame] | 41 | #include <arch/acpi.h> |
Aaron Durbin | 57686f8 | 2013-03-20 15:50:59 -0500 | [diff] [blame^] | 42 | #if CONFIG_X86_AMD_FIXED_MTRRS |
| 43 | #include <cpu/amd/mtrr.h> |
| 44 | #define MTRR_FIXED_WRBACK_BITS (MTRR_READ_MEM | MTRR_WRITE_MEM) |
| 45 | #else |
| 46 | #define MTRR_FIXED_WRBACK_BITS 0 |
| 47 | #endif |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 48 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 49 | static unsigned int mtrr_msr[] = { |
| 50 | MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR, |
| 51 | MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR, |
| 52 | MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR, |
| 53 | }; |
| 54 | |
Stefan Reinauer | c00dfbc | 2012-04-03 16:24:37 -0700 | [diff] [blame] | 55 | /* 2 MTRRS are reserved for the operating system */ |
| 56 | #define BIOS_MTRRS 6 |
| 57 | #define OS_MTRRS 2 |
| 58 | #define MTRRS (BIOS_MTRRS + OS_MTRRS) |
| 59 | |
| 60 | static int total_mtrrs = MTRRS; |
| 61 | static int bios_mtrrs = BIOS_MTRRS; |
| 62 | |
| 63 | static void detect_var_mtrrs(void) |
| 64 | { |
| 65 | msr_t msr; |
| 66 | |
| 67 | msr = rdmsr(MTRRcap_MSR); |
| 68 | |
| 69 | total_mtrrs = msr.lo & 0xff; |
| 70 | bios_mtrrs = total_mtrrs - OS_MTRRS; |
| 71 | } |
| 72 | |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 73 | void enable_fixed_mtrr(void) |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 74 | { |
| 75 | msr_t msr; |
| 76 | |
| 77 | msr = rdmsr(MTRRdefType_MSR); |
| 78 | msr.lo |= 0xc00; |
| 79 | wrmsr(MTRRdefType_MSR, msr); |
| 80 | } |
| 81 | |
| 82 | static void enable_var_mtrr(void) |
| 83 | { |
| 84 | msr_t msr; |
| 85 | |
| 86 | msr = rdmsr(MTRRdefType_MSR); |
Kevin O'Connor | 5bb9fd6 | 2011-01-19 06:32:35 +0000 | [diff] [blame] | 87 | msr.lo |= MTRRdefTypeEn; |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 88 | wrmsr(MTRRdefType_MSR, msr); |
| 89 | } |
| 90 | |
| 91 | /* setting variable mtrr, comes from linux kernel source */ |
Ronald G. Minnich | 69efaa0 | 2013-02-26 10:07:40 -0800 | [diff] [blame] | 92 | void set_var_mtrr( |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 93 | unsigned int reg, unsigned long basek, unsigned long sizek, |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 94 | unsigned char type, unsigned address_bits) |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 95 | { |
| 96 | msr_t base, mask; |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 97 | unsigned address_mask_high; |
| 98 | |
Stefan Reinauer | c00dfbc | 2012-04-03 16:24:37 -0700 | [diff] [blame] | 99 | if (reg >= total_mtrrs) |
| 100 | return; |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 101 | |
| 102 | // it is recommended that we disable and enable cache when we |
| 103 | // do this. |
| 104 | if (sizek == 0) { |
| 105 | disable_cache(); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 106 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 107 | msr_t zero; |
| 108 | zero.lo = zero.hi = 0; |
| 109 | /* The invalid bit is kept in the mask, so we simply clear the |
| 110 | relevant mask register to disable a range. */ |
| 111 | wrmsr (MTRRphysMask_MSR(reg), zero); |
| 112 | |
| 113 | enable_cache(); |
| 114 | return; |
| 115 | } |
| 116 | |
| 117 | |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 118 | address_mask_high = ((1u << (address_bits - 32u)) - 1u); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 119 | |
| 120 | base.hi = basek >> 22; |
| 121 | base.lo = basek << 10; |
| 122 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 123 | if (sizek < 4*1024*1024) { |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 124 | mask.hi = address_mask_high; |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 125 | mask.lo = ~((sizek << 10) -1); |
| 126 | } |
| 127 | else { |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 128 | mask.hi = address_mask_high & (~((sizek >> 22) -1)); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 129 | mask.lo = 0; |
| 130 | } |
| 131 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 132 | // it is recommended that we disable and enable cache when we |
| 133 | // do this. |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 134 | disable_cache(); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 135 | |
| 136 | /* Bit 32-35 of MTRRphysMask should be set to 1 */ |
| 137 | base.lo |= type; |
Kevin O'Connor | 5bb9fd6 | 2011-01-19 06:32:35 +0000 | [diff] [blame] | 138 | mask.lo |= MTRRphysMaskValid; |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 139 | wrmsr (MTRRphysBase_MSR(reg), base); |
| 140 | wrmsr (MTRRphysMask_MSR(reg), mask); |
| 141 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 142 | enable_cache(); |
Denis 'GNUtoo' Carikli | 7c2d058 | 2012-05-26 00:13:22 +0200 | [diff] [blame] | 143 | |
| 144 | printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n", |
| 145 | reg, basek >>10, sizek >> 10, |
| 146 | (type==MTRR_TYPE_UNCACHEABLE)?"UC": |
| 147 | ((type==MTRR_TYPE_WRBACK)?"WB":"Other") |
| 148 | ); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 149 | } |
| 150 | |
| 151 | /* fms: find most sigificant bit set, stolen from Linux Kernel Source. */ |
| 152 | static inline unsigned int fms(unsigned int x) |
| 153 | { |
| 154 | int r; |
| 155 | |
| 156 | __asm__("bsrl %1,%0\n\t" |
| 157 | "jnz 1f\n\t" |
| 158 | "movl $0,%0\n" |
| 159 | "1:" : "=r" (r) : "g" (x)); |
| 160 | return r; |
| 161 | } |
| 162 | |
Marc Jones | 5cbdc1e | 2009-04-01 22:07:53 +0000 | [diff] [blame] | 163 | /* fls: find least sigificant bit set */ |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 164 | static inline unsigned int fls(unsigned int x) |
| 165 | { |
| 166 | int r; |
| 167 | |
| 168 | __asm__("bsfl %1,%0\n\t" |
| 169 | "jnz 1f\n\t" |
| 170 | "movl $32,%0\n" |
| 171 | "1:" : "=r" (r) : "g" (x)); |
| 172 | return r; |
| 173 | } |
| 174 | |
| 175 | /* setting up variable and fixed mtrr |
| 176 | * |
| 177 | * From Intel Vol. III Section 9.12.4, the Range Size and Base Alignment has some kind of requirement: |
| 178 | * 1. The range size must be 2^N byte for N >= 12 (i.e 4KB minimum). |
| 179 | * 2. The base address must be 2^N aligned, where the N here is equal to the N in previous |
| 180 | * requirement. So a 8K range must be 8K aligned not 4K aligned. |
| 181 | * |
| 182 | * These requirement is meet by "decompositing" the ramsize into Sum(Cn * 2^n, n = [0..N], Cn = [0, 1]). |
| 183 | * For Cm = 1, there is a WB range of 2^m size at base address Sum(Cm * 2^m, m = [N..n]). |
| 184 | * A 124MB (128MB - 4MB SMA) example: |
| 185 | * ramsize = 124MB == 64MB (at 0MB) + 32MB (at 64MB) + 16MB (at 96MB ) + 8MB (at 112MB) + 4MB (120MB). |
| 186 | * But this wastes a lot of MTRR registers so we use another more "aggresive" way with Uncacheable Regions. |
| 187 | * |
| 188 | * In the Uncacheable Region scheme, we try to cover the whole ramsize by one WB region as possible, |
| 189 | * If (an only if) this can not be done we will try to decomposite the ramesize, the mathematical formula |
| 190 | * whould be ramsize = Sum(Cn * 2^n, n = [0..N], Cn = [-1, 0, 1]). For Cn = -1, a Uncachable Region is used. |
| 191 | * The same 124MB example: |
| 192 | * ramsize = 124MB == 128MB WB (at 0MB) + 4MB UC (at 124MB) |
| 193 | * or a 156MB (128MB + 32MB - 4MB SMA) example: |
| 194 | * ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB) |
| 195 | */ |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 196 | |
| 197 | static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type) |
| 198 | { |
| 199 | unsigned int i; |
| 200 | unsigned int fixed_msr = NUM_FIXED_RANGES >> 3; |
| 201 | msr_t msr; |
| 202 | msr.lo = msr.hi = 0; /* Shut up gcc */ |
| 203 | for(i = first; i < last; i++) { |
| 204 | /* When I switch to a new msr read it in */ |
| 205 | if (fixed_msr != i >> 3) { |
| 206 | /* But first write out the old msr */ |
| 207 | if (fixed_msr < (NUM_FIXED_RANGES >> 3)) { |
| 208 | disable_cache(); |
| 209 | wrmsr(mtrr_msr[fixed_msr], msr); |
| 210 | enable_cache(); |
| 211 | } |
| 212 | fixed_msr = i>>3; |
| 213 | msr = rdmsr(mtrr_msr[fixed_msr]); |
| 214 | } |
| 215 | if ((i & 7) < 4) { |
| 216 | msr.lo &= ~(0xff << ((i&3)*8)); |
| 217 | msr.lo |= type << ((i&3)*8); |
| 218 | } else { |
| 219 | msr.hi &= ~(0xff << ((i&3)*8)); |
| 220 | msr.hi |= type << ((i&3)*8); |
| 221 | } |
| 222 | } |
| 223 | /* Write out the final msr */ |
| 224 | if (fixed_msr < (NUM_FIXED_RANGES >> 3)) { |
| 225 | disable_cache(); |
| 226 | wrmsr(mtrr_msr[fixed_msr], msr); |
| 227 | enable_cache(); |
| 228 | } |
| 229 | } |
| 230 | |
| 231 | static unsigned fixed_mtrr_index(unsigned long addrk) |
| 232 | { |
| 233 | unsigned index; |
| 234 | index = (addrk - 0) >> 6; |
| 235 | if (index >= 8) { |
| 236 | index = ((addrk - 8*64) >> 4) + 8; |
| 237 | } |
| 238 | if (index >= 24) { |
| 239 | index = ((addrk - (8*64 + 16*16)) >> 2) + 24; |
| 240 | } |
| 241 | if (index > NUM_FIXED_RANGES) { |
| 242 | index = NUM_FIXED_RANGES; |
| 243 | } |
| 244 | return index; |
| 245 | } |
| 246 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 247 | static unsigned int range_to_mtrr(unsigned int reg, |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 248 | unsigned long range_startk, unsigned long range_sizek, |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 249 | unsigned long next_range_startk, unsigned char type, |
| 250 | unsigned int address_bits, unsigned int above4gb) |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 251 | { |
Duncan Laurie | 7389fa9 | 2011-12-22 10:59:40 -0800 | [diff] [blame] | 252 | unsigned long hole_startk = 0, hole_sizek = 0; |
| 253 | |
Carl-Daniel Hailfinger | 7dde1da | 2009-02-11 16:57:32 +0000 | [diff] [blame] | 254 | if (!range_sizek) { |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 255 | /* If there's no MTRR hole, this function will bail out |
| 256 | * here when called for the hole. |
| 257 | */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 258 | printk(BIOS_SPEW, "Zero-sized MTRR range @%ldKB\n", range_startk); |
Carl-Daniel Hailfinger | 7dde1da | 2009-02-11 16:57:32 +0000 | [diff] [blame] | 259 | return reg; |
| 260 | } |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 261 | |
Duncan Laurie | 7389fa9 | 2011-12-22 10:59:40 -0800 | [diff] [blame] | 262 | if (reg >= bios_mtrrs) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 263 | printk(BIOS_ERR, "Warning: Out of MTRRs for base: %4ldMB, range: %ldMB, type %s\n", |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 264 | range_startk >>10, range_sizek >> 10, |
| 265 | (type==MTRR_TYPE_UNCACHEABLE)?"UC": |
| 266 | ((type==MTRR_TYPE_WRBACK)?"WB":"Other") ); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 267 | return reg; |
| 268 | } |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 269 | |
Duncan Laurie | 7b67892 | 2012-01-09 22:05:18 -0800 | [diff] [blame] | 270 | #define MIN_ALIGN 0x10000 /* 64MB */ |
| 271 | |
| 272 | if (above4gb == 2 && type == MTRR_TYPE_WRBACK && |
| 273 | range_sizek > MIN_ALIGN && range_sizek % MIN_ALIGN) { |
Duncan Laurie | 7389fa9 | 2011-12-22 10:59:40 -0800 | [diff] [blame] | 274 | /* |
Duncan Laurie | 7b67892 | 2012-01-09 22:05:18 -0800 | [diff] [blame] | 275 | * If this range is not divisible then instead |
Duncan Laurie | 7389fa9 | 2011-12-22 10:59:40 -0800 | [diff] [blame] | 276 | * make a larger range and carve out an uncached hole. |
| 277 | */ |
| 278 | hole_startk = range_startk + range_sizek; |
Duncan Laurie | 7b67892 | 2012-01-09 22:05:18 -0800 | [diff] [blame] | 279 | hole_sizek = MIN_ALIGN - (range_sizek % MIN_ALIGN); |
Duncan Laurie | 7389fa9 | 2011-12-22 10:59:40 -0800 | [diff] [blame] | 280 | range_sizek += hole_sizek; |
| 281 | } |
| 282 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 283 | while(range_sizek) { |
| 284 | unsigned long max_align, align; |
| 285 | unsigned long sizek; |
| 286 | /* Compute the maximum size I can make a range */ |
| 287 | max_align = fls(range_startk); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 288 | align = fms(range_sizek); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 289 | if (align > max_align) { |
| 290 | align = max_align; |
| 291 | } |
| 292 | sizek = 1 << align; |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 293 | |
| 294 | /* if range is above 4GB, MTRR is needed |
| 295 | * only if above4gb flag is set |
| 296 | */ |
| 297 | if (range_startk < 0x100000000ull / 1024 || above4gb) |
| 298 | set_var_mtrr(reg++, range_startk, sizek, type, address_bits); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 299 | range_startk += sizek; |
| 300 | range_sizek -= sizek; |
Duncan Laurie | 7389fa9 | 2011-12-22 10:59:40 -0800 | [diff] [blame] | 301 | if (reg >= bios_mtrrs) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 302 | printk(BIOS_ERR, "Running out of variable MTRRs!\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 303 | break; |
Carl-Daniel Hailfinger | 7dde1da | 2009-02-11 16:57:32 +0000 | [diff] [blame] | 304 | } |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 305 | } |
Duncan Laurie | 7389fa9 | 2011-12-22 10:59:40 -0800 | [diff] [blame] | 306 | |
| 307 | if (hole_sizek) { |
| 308 | printk(BIOS_DEBUG, "Adding hole at %ldMB-%ldMB\n", |
Duncan Laurie | 527fc74 | 2012-01-06 15:49:30 -0800 | [diff] [blame] | 309 | hole_startk >> 10, (hole_startk + hole_sizek) >> 10); |
Duncan Laurie | 7389fa9 | 2011-12-22 10:59:40 -0800 | [diff] [blame] | 310 | reg = range_to_mtrr(reg, hole_startk, hole_sizek, |
| 311 | next_range_startk, MTRR_TYPE_UNCACHEABLE, |
| 312 | address_bits, above4gb); |
| 313 | } |
| 314 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 315 | return reg; |
| 316 | } |
| 317 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 318 | static unsigned long resk(uint64_t value) |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 319 | { |
| 320 | unsigned long resultk; |
| 321 | if (value < (1ULL << 42)) { |
| 322 | resultk = value >> 10; |
| 323 | } |
| 324 | else { |
| 325 | resultk = 0xffffffff; |
| 326 | } |
| 327 | return resultk; |
| 328 | } |
| 329 | |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 330 | static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resource *res) |
| 331 | { |
| 332 | unsigned int start_mtrr; |
| 333 | unsigned int last_mtrr; |
Aaron Durbin | 57686f8 | 2013-03-20 15:50:59 -0500 | [diff] [blame^] | 334 | const unsigned char type = MTRR_TYPE_WRBACK | MTRR_FIXED_WRBACK_BITS; |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 335 | start_mtrr = fixed_mtrr_index(resk(res->base)); |
| 336 | last_mtrr = fixed_mtrr_index(resk((res->base + res->size))); |
| 337 | if (start_mtrr >= NUM_FIXED_RANGES) { |
| 338 | return; |
| 339 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 340 | printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: WB\n", |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 341 | start_mtrr, last_mtrr); |
Aaron Durbin | 57686f8 | 2013-03-20 15:50:59 -0500 | [diff] [blame^] | 342 | set_fixed_mtrrs(start_mtrr, last_mtrr, type); |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 343 | |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 344 | } |
| 345 | |
| 346 | struct var_mtrr_state { |
| 347 | unsigned long range_startk, range_sizek; |
| 348 | unsigned int reg; |
Yinghai Lu | 6360187 | 2005-01-27 22:48:12 +0000 | [diff] [blame] | 349 | unsigned long hole_startk, hole_sizek; |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 350 | unsigned int address_bits; |
| 351 | unsigned int above4gb; /* Set if MTRRs are needed for DRAM above 4GB */ |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 352 | }; |
| 353 | |
| 354 | void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res) |
| 355 | { |
| 356 | struct var_mtrr_state *state = gp; |
| 357 | unsigned long basek, sizek; |
Duncan Laurie | 7389fa9 | 2011-12-22 10:59:40 -0800 | [diff] [blame] | 358 | if (state->reg >= bios_mtrrs) |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 359 | return; |
Kyösti Mälkki | 2d42b34 | 2012-07-12 00:18:22 +0300 | [diff] [blame] | 360 | |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 361 | basek = resk(res->base); |
| 362 | sizek = resk(res->size); |
Kyösti Mälkki | 2d42b34 | 2012-07-12 00:18:22 +0300 | [diff] [blame] | 363 | |
| 364 | if (res->flags & IORESOURCE_UMA_FB) { |
| 365 | /* FIXME: could I use Write-Combining for Frame Buffer ? */ |
| 366 | state->reg = range_to_mtrr(state->reg, basek, sizek, 0, |
| 367 | MTRR_TYPE_UNCACHEABLE, state->address_bits, state->above4gb); |
| 368 | return; |
| 369 | } |
| 370 | |
Kyösti Mälkki | 1ec5e74 | 2012-07-26 23:51:20 +0300 | [diff] [blame] | 371 | if (res->flags & IORESOURCE_IGNORE_MTRR) { |
| 372 | return; |
| 373 | } |
| 374 | |
Kyösti Mälkki | 2d42b34 | 2012-07-12 00:18:22 +0300 | [diff] [blame] | 375 | if (!(res->flags & IORESOURCE_CACHEABLE)) |
| 376 | return; |
| 377 | |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 378 | /* See if I can merge with the last range |
| 379 | * Either I am below 1M and the fixed mtrrs handle it, or |
| 380 | * the ranges touch. |
| 381 | */ |
| 382 | if ((basek <= 1024) || (state->range_startk + state->range_sizek == basek)) { |
| 383 | unsigned long endk = basek + sizek; |
| 384 | state->range_sizek = endk - state->range_startk; |
| 385 | return; |
| 386 | } |
| 387 | /* Write the range mtrrs */ |
| 388 | if (state->range_sizek != 0) { |
Duncan Laurie | 7389fa9 | 2011-12-22 10:59:40 -0800 | [diff] [blame] | 389 | if (state->hole_sizek == 0 && state->above4gb != 2) { |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 390 | /* We need to put that on to hole */ |
| 391 | unsigned long endk = basek + sizek; |
Yinghai Lu | 6360187 | 2005-01-27 22:48:12 +0000 | [diff] [blame] | 392 | state->hole_startk = state->range_startk + state->range_sizek; |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 393 | state->hole_sizek = basek - state->hole_startk; |
| 394 | state->range_sizek = endk - state->range_startk; |
Yinghai Lu | 6360187 | 2005-01-27 22:48:12 +0000 | [diff] [blame] | 395 | return; |
| 396 | } |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 397 | state->reg = range_to_mtrr(state->reg, state->range_startk, |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 398 | state->range_sizek, basek, MTRR_TYPE_WRBACK, |
| 399 | state->address_bits, state->above4gb); |
Kyösti Mälkki | ffc1fb3 | 2012-07-11 14:40:19 +0300 | [diff] [blame] | 400 | |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 401 | state->reg = range_to_mtrr(state->reg, state->hole_startk, |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 402 | state->hole_sizek, basek, MTRR_TYPE_UNCACHEABLE, |
| 403 | state->address_bits, state->above4gb); |
Kyösti Mälkki | ffc1fb3 | 2012-07-11 14:40:19 +0300 | [diff] [blame] | 404 | |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 405 | state->range_startk = 0; |
| 406 | state->range_sizek = 0; |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 407 | state->hole_startk = 0; |
| 408 | state->hole_sizek = 0; |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 409 | } |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 410 | /* Allocate an msr */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 411 | printk(BIOS_SPEW, " Allocate an msr - basek = %08lx, sizek = %08lx,\n", basek, sizek); |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 412 | state->range_startk = basek; |
| 413 | state->range_sizek = sizek; |
| 414 | } |
| 415 | |
Aaron Durbin | 57686f8 | 2013-03-20 15:50:59 -0500 | [diff] [blame^] | 416 | void x86_setup_fixed_mtrrs_no_enable(void) |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 417 | { |
| 418 | /* Try this the simple way of incrementally adding together |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 419 | * mtrrs. If this doesn't work out we can get smart again |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 420 | * and clear out the mtrrs. |
| 421 | */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 422 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 423 | printk(BIOS_DEBUG, "\n"); |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 424 | /* Initialized the fixed_mtrrs to uncached */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 425 | printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: UC\n", |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 426 | 0, NUM_FIXED_RANGES); |
| 427 | set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE); |
| 428 | |
| 429 | /* Now see which of the fixed mtrrs cover ram. |
| 430 | */ |
| 431 | search_global_resources( |
| 432 | IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, |
| 433 | set_fixed_mtrr_resource, NULL); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 434 | printk(BIOS_DEBUG, "DONE fixed MTRRs\n"); |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 435 | } |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 436 | |
Aaron Durbin | 57686f8 | 2013-03-20 15:50:59 -0500 | [diff] [blame^] | 437 | void x86_setup_fixed_mtrrs(void) |
| 438 | { |
| 439 | x86_setup_fixed_mtrrs_no_enable(); |
| 440 | |
| 441 | printk(BIOS_SPEW, "call enable_fixed_mtrr()\n"); |
| 442 | enable_fixed_mtrr(); |
| 443 | } |
| 444 | |
| 445 | |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 446 | void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 447 | /* this routine needs to know how many address bits a given processor |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 448 | * supports. CPUs get grumpy when you set too many bits in |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 449 | * their mtrr registers :( I would generically call cpuid here |
| 450 | * and find out how many physically supported but some cpus are |
| 451 | * buggy, and report more bits then they actually support. |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 452 | * If above4gb flag is set, variable MTRR ranges must be used to |
| 453 | * set cacheability of DRAM above 4GB. If above4gb flag is clear, |
| 454 | * some other mechanism is controlling cacheability of DRAM above 4GB. |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 455 | */ |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 456 | { |
| 457 | /* Try this the simple way of incrementally adding together |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 458 | * mtrrs. If this doesn't work out we can get smart again |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 459 | * and clear out the mtrrs. |
| 460 | */ |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 461 | struct var_mtrr_state var_state; |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 462 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 463 | /* Cache as many memory areas as possible */ |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 464 | /* FIXME is there an algorithm for computing the optimal set of mtrrs? |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 465 | * In some cases it is definitely possible to do better. |
| 466 | */ |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 467 | var_state.range_startk = 0; |
| 468 | var_state.range_sizek = 0; |
Yinghai Lu | 6360187 | 2005-01-27 22:48:12 +0000 | [diff] [blame] | 469 | var_state.hole_startk = 0; |
| 470 | var_state.hole_sizek = 0; |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 471 | var_state.reg = 0; |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 472 | var_state.address_bits = address_bits; |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 473 | var_state.above4gb = above4gb; |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 474 | |
Duncan Laurie | 7389fa9 | 2011-12-22 10:59:40 -0800 | [diff] [blame] | 475 | /* Detect number of variable MTRRs */ |
| 476 | if (above4gb == 2) |
| 477 | detect_var_mtrrs(); |
| 478 | |
Kyösti Mälkki | 2d42b34 | 2012-07-12 00:18:22 +0300 | [diff] [blame] | 479 | search_global_resources(IORESOURCE_MEM, IORESOURCE_MEM, |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 480 | set_var_mtrr_resource, &var_state); |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 481 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 482 | /* Write the last range */ |
Stefan Reinauer | 14e2277 | 2010-04-27 06:56:47 +0000 | [diff] [blame] | 483 | var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk, |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 484 | var_state.range_sizek, 0, MTRR_TYPE_WRBACK, |
| 485 | var_state.address_bits, var_state.above4gb); |
Kyösti Mälkki | ffc1fb3 | 2012-07-11 14:40:19 +0300 | [diff] [blame] | 486 | |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 487 | var_state.reg = range_to_mtrr(var_state.reg, var_state.hole_startk, |
Scott Duplichan | f3cce2f | 2010-11-13 19:07:59 +0000 | [diff] [blame] | 488 | var_state.hole_sizek, 0, MTRR_TYPE_UNCACHEABLE, |
| 489 | var_state.address_bits, var_state.above4gb); |
Kyösti Mälkki | ffc1fb3 | 2012-07-11 14:40:19 +0300 | [diff] [blame] | 490 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 491 | printk(BIOS_DEBUG, "DONE variable MTRRs\n"); |
| 492 | printk(BIOS_DEBUG, "Clear out the extra MTRR's\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 493 | /* Clear out the extra MTRR's */ |
Duncan Laurie | 7389fa9 | 2011-12-22 10:59:40 -0800 | [diff] [blame] | 494 | while(var_state.reg < total_mtrrs) { |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 495 | set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 496 | } |
Stefan Reinauer | 00093a8 | 2011-11-02 16:12:34 -0700 | [diff] [blame] | 497 | |
| 498 | #if CONFIG_CACHE_ROM |
| 499 | /* Enable Caching and speculative Reads for the |
| 500 | * complete ROM now that we actually have RAM. |
| 501 | */ |
| 502 | if (boot_cpu() && (acpi_slp_type != 3)) { |
Stefan Reinauer | c00dfbc | 2012-04-03 16:24:37 -0700 | [diff] [blame] | 503 | set_var_mtrr(total_mtrrs - 1, (4096 - 8)*1024, 8 * 1024, |
Stefan Reinauer | 00093a8 | 2011-11-02 16:12:34 -0700 | [diff] [blame] | 504 | MTRR_TYPE_WRPROT, address_bits); |
| 505 | } |
| 506 | #endif |
| 507 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 508 | printk(BIOS_SPEW, "call enable_var_mtrr()\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 509 | enable_var_mtrr(); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 510 | printk(BIOS_SPEW, "Leave %s\n", __func__); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 511 | post_code(0x6A); |
| 512 | } |
| 513 | |
Sven Schnelle | adfbcb79 | 2012-01-10 12:01:43 +0100 | [diff] [blame] | 514 | void x86_setup_mtrrs(void) |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 515 | { |
Sven Schnelle | adfbcb79 | 2012-01-10 12:01:43 +0100 | [diff] [blame] | 516 | int address_size; |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 517 | x86_setup_fixed_mtrrs(); |
Sven Schnelle | adfbcb79 | 2012-01-10 12:01:43 +0100 | [diff] [blame] | 518 | address_size = cpu_phys_address_size(); |
| 519 | printk(BIOS_DEBUG, "CPU physical address size: %d bits\n", address_size); |
| 520 | x86_setup_var_mtrrs(address_size, 1); |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 521 | } |
| 522 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 523 | int x86_mtrr_check(void) |
| 524 | { |
| 525 | /* Only Pentium Pro and later have MTRR */ |
| 526 | msr_t msr; |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 527 | printk(BIOS_DEBUG, "\nMTRR check\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 528 | |
| 529 | msr = rdmsr(0x2ff); |
| 530 | msr.lo >>= 10; |
| 531 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 532 | printk(BIOS_DEBUG, "Fixed MTRRs : "); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 533 | if (msr.lo & 0x01) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 534 | printk(BIOS_DEBUG, "Enabled\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 535 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 536 | printk(BIOS_DEBUG, "Disabled\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 537 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 538 | printk(BIOS_DEBUG, "Variable MTRRs: "); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 539 | if (msr.lo & 0x02) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 540 | printk(BIOS_DEBUG, "Enabled\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 541 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 542 | printk(BIOS_DEBUG, "Disabled\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 543 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame] | 544 | printk(BIOS_DEBUG, "\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 545 | |
| 546 | post_code(0x93); |
| 547 | return ((int) msr.lo); |
| 548 | } |