MTRR related improvements for AMD family 10h and family 0Fh systems

-- When building for UMA, reduce the limit for DRAM below 4GB
   from E0000000 to C0000000. This is needed to accomodate the
   UMA frame buffer.
-- Correct problem where msr C0010010 bits 21 and 22 (MtrrTom2En
   and Tom2ForceMemTypeWB) are not set consistently across cores.
-- Enable TOM2 only if DRAM is present above 4GB.
-- Use AMD Tom2ForceMemTypeWB feature to avoid the need for 
   variable MTRR ranges above 4GB.
-- Add above4gb flag argument to function x86_setup_var_mtrrs. Clearing
   this flag causes x86_setup_var_mtrrs() to omit MTRR ranges for
   DRAM above 4GB. AMD systems use this option to conserve MTRRs.
-- Northbridge.c change to deduct UMA memory from DRAM size reported
   by ram_resource. This corrects a problem where mtrr.c generates an
   unexpected variable MTRR range.
-- Correct problem causing build failure when CONFIG_GFXUMA=1 and
-- Reserve the UMA DRAM range for AMD K8 as is already done for AMD
   family 10h.
Tested with mahogany on ECS A780G-GM with 2GB and 4GB.
Tested with mahogany_fam10 on ECS A780G-GM with 2GB and 4GB.
Signed-off-by: Scott Duplichan <>
Acked-by: Peter Stuge <>

git-svn-id: svn:// 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
8 files changed
tree: 2961bfdba8f650fca44d04fe1232c76c71adda05
  1. documentation/
  2. payloads/
  3. src/
  4. util/
  6. Makefile