Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 1 | /* |
Stefan Reinauer | cdc5cc6 | 2007-04-24 18:40:02 +0000 | [diff] [blame] | 2 | * mtrr.c: setting MTRR to decent values for cache initialization on P6 |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 3 | * |
| 4 | * Derived from intel_set_mtrr in intel_subr.c and mtrr.c in linux kernel |
| 5 | * |
| 6 | * Copyright 2000 Silicon Integrated System Corporation |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License as published by |
| 10 | * the Free Software Foundation; either version 2 of the License, or |
| 11 | * (at your option) any later version. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | * GNU General Public License for more details. |
| 17 | * |
| 18 | * You should have received a copy of the GNU General Public License |
| 19 | * along with this program; if not, write to the Free Software |
| 20 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
| 21 | * |
| 22 | * |
| 23 | * Reference: Intel Architecture Software Developer's Manual, Volume 3: System Programming |
| 24 | */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 25 | |
Yinghai Lu | 953e0f6 | 2005-01-06 04:55:19 +0000 | [diff] [blame] | 26 | /* |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 27 | 2005.1 yhlu add NC support to spare mtrrs for 64G memory above installed |
| 28 | 2005.6 Eric add address bit in x86_setup_mtrrs |
| 29 | 2005.6 yhlu split x86_setup_var_mtrrs and x86_setup_fixed_mtrrs, |
| 30 | for AMD, it will not use x86_setup_fixed_mtrrs |
Yinghai Lu | 953e0f6 | 2005-01-06 04:55:19 +0000 | [diff] [blame] | 31 | */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 32 | |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 33 | #include <stddef.h> |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 34 | #include <console/console.h> |
| 35 | #include <device/device.h> |
| 36 | #include <cpu/x86/msr.h> |
| 37 | #include <cpu/x86/mtrr.h> |
| 38 | #include <cpu/x86/cache.h> |
| 39 | |
Myles Watson | ec0ee64 | 2009-10-19 16:21:30 +0000 | [diff] [blame] | 40 | #if CONFIG_GFXUMA |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 41 | extern uint64_t uma_memory_base, uma_memory_size; |
| 42 | #endif |
| 43 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 44 | static unsigned int mtrr_msr[] = { |
| 45 | MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR, |
| 46 | MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR, |
| 47 | MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR, |
| 48 | }; |
| 49 | |
| 50 | |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 51 | void enable_fixed_mtrr(void) |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 52 | { |
| 53 | msr_t msr; |
| 54 | |
| 55 | msr = rdmsr(MTRRdefType_MSR); |
| 56 | msr.lo |= 0xc00; |
| 57 | wrmsr(MTRRdefType_MSR, msr); |
| 58 | } |
| 59 | |
| 60 | static void enable_var_mtrr(void) |
| 61 | { |
| 62 | msr_t msr; |
| 63 | |
| 64 | msr = rdmsr(MTRRdefType_MSR); |
| 65 | msr.lo |= 0x800; |
| 66 | wrmsr(MTRRdefType_MSR, msr); |
| 67 | } |
| 68 | |
| 69 | /* setting variable mtrr, comes from linux kernel source */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 70 | static void set_var_mtrr( |
| 71 | unsigned int reg, unsigned long basek, unsigned long sizek, |
| 72 | unsigned char type, unsigned address_bits) |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 73 | { |
| 74 | msr_t base, mask; |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 75 | unsigned address_mask_high; |
| 76 | |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 77 | if (reg >= 8) |
| 78 | return; |
| 79 | |
| 80 | // it is recommended that we disable and enable cache when we |
| 81 | // do this. |
| 82 | if (sizek == 0) { |
| 83 | disable_cache(); |
| 84 | |
| 85 | msr_t zero; |
| 86 | zero.lo = zero.hi = 0; |
| 87 | /* The invalid bit is kept in the mask, so we simply clear the |
| 88 | relevant mask register to disable a range. */ |
| 89 | wrmsr (MTRRphysMask_MSR(reg), zero); |
| 90 | |
| 91 | enable_cache(); |
| 92 | return; |
| 93 | } |
| 94 | |
| 95 | |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 96 | address_mask_high = ((1u << (address_bits - 32u)) - 1u); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 97 | |
| 98 | base.hi = basek >> 22; |
| 99 | base.lo = basek << 10; |
| 100 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame^] | 101 | printk(BIOS_SPEW, "ADDRESS_MASK_HIGH=%#x\n", address_mask_high); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 102 | |
| 103 | if (sizek < 4*1024*1024) { |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 104 | mask.hi = address_mask_high; |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 105 | mask.lo = ~((sizek << 10) -1); |
| 106 | } |
| 107 | else { |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 108 | mask.hi = address_mask_high & (~((sizek >> 22) -1)); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 109 | mask.lo = 0; |
| 110 | } |
| 111 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 112 | // it is recommended that we disable and enable cache when we |
| 113 | // do this. |
| 114 | disable_cache(); |
Yinghai Lu | d4b278c | 2006-10-04 20:46:15 +0000 | [diff] [blame] | 115 | |
| 116 | /* Bit 32-35 of MTRRphysMask should be set to 1 */ |
| 117 | base.lo |= type; |
| 118 | mask.lo |= 0x800; |
| 119 | wrmsr (MTRRphysBase_MSR(reg), base); |
| 120 | wrmsr (MTRRphysMask_MSR(reg), mask); |
| 121 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 122 | enable_cache(); |
| 123 | } |
| 124 | |
| 125 | /* fms: find most sigificant bit set, stolen from Linux Kernel Source. */ |
| 126 | static inline unsigned int fms(unsigned int x) |
| 127 | { |
| 128 | int r; |
| 129 | |
| 130 | __asm__("bsrl %1,%0\n\t" |
| 131 | "jnz 1f\n\t" |
| 132 | "movl $0,%0\n" |
| 133 | "1:" : "=r" (r) : "g" (x)); |
| 134 | return r; |
| 135 | } |
| 136 | |
Marc Jones | 5cbdc1e | 2009-04-01 22:07:53 +0000 | [diff] [blame] | 137 | /* fls: find least sigificant bit set */ |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 138 | static inline unsigned int fls(unsigned int x) |
| 139 | { |
| 140 | int r; |
| 141 | |
| 142 | __asm__("bsfl %1,%0\n\t" |
| 143 | "jnz 1f\n\t" |
| 144 | "movl $32,%0\n" |
| 145 | "1:" : "=r" (r) : "g" (x)); |
| 146 | return r; |
| 147 | } |
| 148 | |
| 149 | /* setting up variable and fixed mtrr |
| 150 | * |
| 151 | * From Intel Vol. III Section 9.12.4, the Range Size and Base Alignment has some kind of requirement: |
| 152 | * 1. The range size must be 2^N byte for N >= 12 (i.e 4KB minimum). |
| 153 | * 2. The base address must be 2^N aligned, where the N here is equal to the N in previous |
| 154 | * requirement. So a 8K range must be 8K aligned not 4K aligned. |
| 155 | * |
| 156 | * These requirement is meet by "decompositing" the ramsize into Sum(Cn * 2^n, n = [0..N], Cn = [0, 1]). |
| 157 | * For Cm = 1, there is a WB range of 2^m size at base address Sum(Cm * 2^m, m = [N..n]). |
| 158 | * A 124MB (128MB - 4MB SMA) example: |
| 159 | * ramsize = 124MB == 64MB (at 0MB) + 32MB (at 64MB) + 16MB (at 96MB ) + 8MB (at 112MB) + 4MB (120MB). |
| 160 | * But this wastes a lot of MTRR registers so we use another more "aggresive" way with Uncacheable Regions. |
| 161 | * |
| 162 | * In the Uncacheable Region scheme, we try to cover the whole ramsize by one WB region as possible, |
| 163 | * If (an only if) this can not be done we will try to decomposite the ramesize, the mathematical formula |
| 164 | * whould be ramsize = Sum(Cn * 2^n, n = [0..N], Cn = [-1, 0, 1]). For Cn = -1, a Uncachable Region is used. |
| 165 | * The same 124MB example: |
| 166 | * ramsize = 124MB == 128MB WB (at 0MB) + 4MB UC (at 124MB) |
| 167 | * or a 156MB (128MB + 32MB - 4MB SMA) example: |
| 168 | * ramsize = 156MB == 128MB WB (at 0MB) + 32MB WB (at 128MB) + 4MB UC (at 156MB) |
| 169 | */ |
| 170 | /* 2 MTRRS are reserved for the operating system */ |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 171 | #if 1 |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 172 | #define BIOS_MTRRS 6 |
| 173 | #define OS_MTRRS 2 |
| 174 | #else |
| 175 | #define BIOS_MTRRS 8 |
| 176 | #define OS_MTRRS 0 |
| 177 | #endif |
| 178 | #define MTRRS (BIOS_MTRRS + OS_MTRRS) |
| 179 | |
| 180 | |
| 181 | static void set_fixed_mtrrs(unsigned int first, unsigned int last, unsigned char type) |
| 182 | { |
| 183 | unsigned int i; |
| 184 | unsigned int fixed_msr = NUM_FIXED_RANGES >> 3; |
| 185 | msr_t msr; |
| 186 | msr.lo = msr.hi = 0; /* Shut up gcc */ |
| 187 | for(i = first; i < last; i++) { |
| 188 | /* When I switch to a new msr read it in */ |
| 189 | if (fixed_msr != i >> 3) { |
| 190 | /* But first write out the old msr */ |
| 191 | if (fixed_msr < (NUM_FIXED_RANGES >> 3)) { |
| 192 | disable_cache(); |
| 193 | wrmsr(mtrr_msr[fixed_msr], msr); |
| 194 | enable_cache(); |
| 195 | } |
| 196 | fixed_msr = i>>3; |
| 197 | msr = rdmsr(mtrr_msr[fixed_msr]); |
| 198 | } |
| 199 | if ((i & 7) < 4) { |
| 200 | msr.lo &= ~(0xff << ((i&3)*8)); |
| 201 | msr.lo |= type << ((i&3)*8); |
| 202 | } else { |
| 203 | msr.hi &= ~(0xff << ((i&3)*8)); |
| 204 | msr.hi |= type << ((i&3)*8); |
| 205 | } |
| 206 | } |
| 207 | /* Write out the final msr */ |
| 208 | if (fixed_msr < (NUM_FIXED_RANGES >> 3)) { |
| 209 | disable_cache(); |
| 210 | wrmsr(mtrr_msr[fixed_msr], msr); |
| 211 | enable_cache(); |
| 212 | } |
| 213 | } |
| 214 | |
| 215 | static unsigned fixed_mtrr_index(unsigned long addrk) |
| 216 | { |
| 217 | unsigned index; |
| 218 | index = (addrk - 0) >> 6; |
| 219 | if (index >= 8) { |
| 220 | index = ((addrk - 8*64) >> 4) + 8; |
| 221 | } |
| 222 | if (index >= 24) { |
| 223 | index = ((addrk - (8*64 + 16*16)) >> 2) + 24; |
| 224 | } |
| 225 | if (index > NUM_FIXED_RANGES) { |
| 226 | index = NUM_FIXED_RANGES; |
| 227 | } |
| 228 | return index; |
| 229 | } |
| 230 | |
| 231 | static unsigned int range_to_mtrr(unsigned int reg, |
| 232 | unsigned long range_startk, unsigned long range_sizek, |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 233 | unsigned long next_range_startk, unsigned char type, unsigned address_bits) |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 234 | { |
Carl-Daniel Hailfinger | 7dde1da | 2009-02-11 16:57:32 +0000 | [diff] [blame] | 235 | if (!range_sizek) { |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 236 | /* If there's no MTRR hole, this function will bail out |
| 237 | * here when called for the hole. |
| 238 | */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame^] | 239 | printk(BIOS_SPEW, "Zero-sized MTRR range @%ldKB\n", range_startk); |
Carl-Daniel Hailfinger | 7dde1da | 2009-02-11 16:57:32 +0000 | [diff] [blame] | 240 | return reg; |
| 241 | } |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 242 | |
Carl-Daniel Hailfinger | 7dde1da | 2009-02-11 16:57:32 +0000 | [diff] [blame] | 243 | if (reg >= BIOS_MTRRS) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame^] | 244 | printk(BIOS_ERR, "Warning: Out of MTRRs for base: %4ldMB, range: %ldMB, type %s\n", |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 245 | range_startk >>10, range_sizek >> 10, |
| 246 | (type==MTRR_TYPE_UNCACHEABLE)?"UC": |
| 247 | ((type==MTRR_TYPE_WRBACK)?"WB":"Other") ); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 248 | return reg; |
| 249 | } |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 250 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 251 | while(range_sizek) { |
| 252 | unsigned long max_align, align; |
| 253 | unsigned long sizek; |
| 254 | /* Compute the maximum size I can make a range */ |
| 255 | max_align = fls(range_startk); |
| 256 | align = fms(range_sizek); |
| 257 | if (align > max_align) { |
| 258 | align = max_align; |
| 259 | } |
| 260 | sizek = 1 << align; |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame^] | 261 | printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n", |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 262 | reg, range_startk >>10, sizek >> 10, |
| 263 | (type==MTRR_TYPE_UNCACHEABLE)?"UC": |
| 264 | ((type==MTRR_TYPE_WRBACK)?"WB":"Other") |
Yinghai Lu | 6360187 | 2005-01-27 22:48:12 +0000 | [diff] [blame] | 265 | ); |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 266 | set_var_mtrr(reg++, range_startk, sizek, type, address_bits); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 267 | range_startk += sizek; |
| 268 | range_sizek -= sizek; |
Carl-Daniel Hailfinger | 7dde1da | 2009-02-11 16:57:32 +0000 | [diff] [blame] | 269 | if (reg >= BIOS_MTRRS) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame^] | 270 | printk(BIOS_ERR, "Running out of variable MTRRs!\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 271 | break; |
Carl-Daniel Hailfinger | 7dde1da | 2009-02-11 16:57:32 +0000 | [diff] [blame] | 272 | } |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 273 | } |
| 274 | return reg; |
| 275 | } |
| 276 | |
| 277 | static unsigned long resk(uint64_t value) |
| 278 | { |
| 279 | unsigned long resultk; |
| 280 | if (value < (1ULL << 42)) { |
| 281 | resultk = value >> 10; |
| 282 | } |
| 283 | else { |
| 284 | resultk = 0xffffffff; |
| 285 | } |
| 286 | return resultk; |
| 287 | } |
| 288 | |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 289 | static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resource *res) |
| 290 | { |
| 291 | unsigned int start_mtrr; |
| 292 | unsigned int last_mtrr; |
| 293 | start_mtrr = fixed_mtrr_index(resk(res->base)); |
| 294 | last_mtrr = fixed_mtrr_index(resk((res->base + res->size))); |
| 295 | if (start_mtrr >= NUM_FIXED_RANGES) { |
| 296 | return; |
| 297 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame^] | 298 | printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: WB\n", |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 299 | start_mtrr, last_mtrr); |
| 300 | set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK); |
| 301 | |
| 302 | } |
| 303 | |
Yinghai Lu | 21332b8 | 2007-04-06 19:49:05 +0000 | [diff] [blame] | 304 | #ifndef CONFIG_VAR_MTRR_HOLE |
| 305 | #define CONFIG_VAR_MTRR_HOLE 1 |
| 306 | #endif |
| 307 | |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 308 | struct var_mtrr_state { |
| 309 | unsigned long range_startk, range_sizek; |
| 310 | unsigned int reg; |
Yinghai Lu | 21332b8 | 2007-04-06 19:49:05 +0000 | [diff] [blame] | 311 | #if CONFIG_VAR_MTRR_HOLE |
Yinghai Lu | 6360187 | 2005-01-27 22:48:12 +0000 | [diff] [blame] | 312 | unsigned long hole_startk, hole_sizek; |
Yinghai Lu | 21332b8 | 2007-04-06 19:49:05 +0000 | [diff] [blame] | 313 | #endif |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 314 | unsigned address_bits; |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 315 | }; |
| 316 | |
| 317 | void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res) |
| 318 | { |
| 319 | struct var_mtrr_state *state = gp; |
| 320 | unsigned long basek, sizek; |
| 321 | if (state->reg >= BIOS_MTRRS) |
| 322 | return; |
| 323 | basek = resk(res->base); |
| 324 | sizek = resk(res->size); |
| 325 | /* See if I can merge with the last range |
| 326 | * Either I am below 1M and the fixed mtrrs handle it, or |
| 327 | * the ranges touch. |
| 328 | */ |
| 329 | if ((basek <= 1024) || (state->range_startk + state->range_sizek == basek)) { |
| 330 | unsigned long endk = basek + sizek; |
| 331 | state->range_sizek = endk - state->range_startk; |
| 332 | return; |
| 333 | } |
| 334 | /* Write the range mtrrs */ |
| 335 | if (state->range_sizek != 0) { |
Yinghai Lu | 21332b8 | 2007-04-06 19:49:05 +0000 | [diff] [blame] | 336 | #if CONFIG_VAR_MTRR_HOLE |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 337 | if (state->hole_sizek == 0) { |
| 338 | /* We need to put that on to hole */ |
| 339 | unsigned long endk = basek + sizek; |
Yinghai Lu | 6360187 | 2005-01-27 22:48:12 +0000 | [diff] [blame] | 340 | state->hole_startk = state->range_startk + state->range_sizek; |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 341 | state->hole_sizek = basek - state->hole_startk; |
| 342 | state->range_sizek = endk - state->range_startk; |
Yinghai Lu | 6360187 | 2005-01-27 22:48:12 +0000 | [diff] [blame] | 343 | return; |
| 344 | } |
Yinghai Lu | 21332b8 | 2007-04-06 19:49:05 +0000 | [diff] [blame] | 345 | #endif |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 346 | state->reg = range_to_mtrr(state->reg, state->range_startk, |
| 347 | state->range_sizek, basek, MTRR_TYPE_WRBACK, state->address_bits); |
Yinghai Lu | 21332b8 | 2007-04-06 19:49:05 +0000 | [diff] [blame] | 348 | #if CONFIG_VAR_MTRR_HOLE |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 349 | state->reg = range_to_mtrr(state->reg, state->hole_startk, |
| 350 | state->hole_sizek, basek, MTRR_TYPE_UNCACHEABLE, state->address_bits); |
Yinghai Lu | 21332b8 | 2007-04-06 19:49:05 +0000 | [diff] [blame] | 351 | #endif |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 352 | state->range_startk = 0; |
| 353 | state->range_sizek = 0; |
Yinghai Lu | 21332b8 | 2007-04-06 19:49:05 +0000 | [diff] [blame] | 354 | #if CONFIG_VAR_MTRR_HOLE |
Yinghai Lu | 6360187 | 2005-01-27 22:48:12 +0000 | [diff] [blame] | 355 | state->hole_startk = 0; |
| 356 | state->hole_sizek = 0; |
Yinghai Lu | 21332b8 | 2007-04-06 19:49:05 +0000 | [diff] [blame] | 357 | #endif |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 358 | } |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 359 | /* Allocate an msr */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame^] | 360 | printk(BIOS_SPEW, " Allocate an msr - basek = %08lx, sizek = %08lx,\n", basek, sizek); |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 361 | state->range_startk = basek; |
| 362 | state->range_sizek = sizek; |
| 363 | } |
| 364 | |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 365 | void x86_setup_fixed_mtrrs(void) |
| 366 | { |
| 367 | /* Try this the simple way of incrementally adding together |
| 368 | * mtrrs. If this doesn't work out we can get smart again |
| 369 | * and clear out the mtrrs. |
| 370 | */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 371 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame^] | 372 | printk(BIOS_DEBUG, "\n"); |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 373 | /* Initialized the fixed_mtrrs to uncached */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame^] | 374 | printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: UC\n", |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 375 | 0, NUM_FIXED_RANGES); |
| 376 | set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE); |
| 377 | |
| 378 | /* Now see which of the fixed mtrrs cover ram. |
| 379 | */ |
| 380 | search_global_resources( |
| 381 | IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, |
| 382 | set_fixed_mtrr_resource, NULL); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame^] | 383 | printk(BIOS_DEBUG, "DONE fixed MTRRs\n"); |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 384 | |
| 385 | /* enable fixed MTRR */ |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame^] | 386 | printk(BIOS_SPEW, "call enable_fixed_mtrr()\n"); |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 387 | enable_fixed_mtrr(); |
| 388 | |
| 389 | } |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 390 | |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 391 | void x86_setup_var_mtrrs(unsigned address_bits) |
| 392 | /* this routine needs to know how many address bits a given processor |
| 393 | * supports. CPUs get grumpy when you set too many bits in |
| 394 | * their mtrr registers :( I would generically call cpuid here |
| 395 | * and find out how many physically supported but some cpus are |
| 396 | * buggy, and report more bits then they actually support. |
| 397 | */ |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 398 | { |
| 399 | /* Try this the simple way of incrementally adding together |
| 400 | * mtrrs. If this doesn't work out we can get smart again |
| 401 | * and clear out the mtrrs. |
| 402 | */ |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 403 | struct var_mtrr_state var_state; |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 404 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 405 | /* Cache as many memory areas as possible */ |
| 406 | /* FIXME is there an algorithm for computing the optimal set of mtrrs? |
| 407 | * In some cases it is definitely possible to do better. |
| 408 | */ |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 409 | var_state.range_startk = 0; |
| 410 | var_state.range_sizek = 0; |
Yinghai Lu | 21332b8 | 2007-04-06 19:49:05 +0000 | [diff] [blame] | 411 | #if CONFIG_VAR_MTRR_HOLE |
Yinghai Lu | 6360187 | 2005-01-27 22:48:12 +0000 | [diff] [blame] | 412 | var_state.hole_startk = 0; |
| 413 | var_state.hole_sizek = 0; |
Yinghai Lu | 21332b8 | 2007-04-06 19:49:05 +0000 | [diff] [blame] | 414 | #endif |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 415 | var_state.reg = 0; |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 416 | var_state.address_bits = address_bits; |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 417 | |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 418 | search_global_resources( |
| 419 | IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, |
| 420 | set_var_mtrr_resource, &var_state); |
Zheng Bao | edee9eb | 2009-08-11 03:18:11 +0000 | [diff] [blame] | 421 | #if (CONFIG_GFXUMA == 1) /* UMA or SP. */ |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 422 | // For now we assume the UMA space is at the end of memory |
| 423 | if (var_state.hole_startk || var_state.hole_sizek) { |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame^] | 424 | printk(BIOS_DEBUG, "Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.\n"); |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 425 | } else { |
| 426 | // Increase the base range and set up UMA as an UC hole instead |
| 427 | var_state.range_sizek += (uma_memory_size >> 10); |
Yinghai Lu | 953e0f6 | 2005-01-06 04:55:19 +0000 | [diff] [blame] | 428 | |
Stefan Reinauer | 7f86ed1 | 2009-02-12 16:02:16 +0000 | [diff] [blame] | 429 | var_state.hole_startk = (uma_memory_base >> 10); |
| 430 | var_state.hole_sizek = (uma_memory_size >> 10); |
| 431 | } |
| 432 | #endif |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 433 | /* Write the last range */ |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 434 | var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk, |
| 435 | var_state.range_sizek, 0, MTRR_TYPE_WRBACK, var_state.address_bits); |
Yinghai Lu | 21332b8 | 2007-04-06 19:49:05 +0000 | [diff] [blame] | 436 | #if CONFIG_VAR_MTRR_HOLE |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 437 | var_state.reg = range_to_mtrr(var_state.reg, var_state.hole_startk, |
| 438 | var_state.hole_sizek, 0, MTRR_TYPE_UNCACHEABLE, var_state.address_bits); |
Yinghai Lu | 21332b8 | 2007-04-06 19:49:05 +0000 | [diff] [blame] | 439 | #endif |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame^] | 440 | printk(BIOS_DEBUG, "DONE variable MTRRs\n"); |
| 441 | printk(BIOS_DEBUG, "Clear out the extra MTRR's\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 442 | /* Clear out the extra MTRR's */ |
Eric Biederman | f8a2ddd | 2004-10-30 08:05:41 +0000 | [diff] [blame] | 443 | while(var_state.reg < MTRRS) { |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 444 | set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 445 | } |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame^] | 446 | printk(BIOS_SPEW, "call enable_var_mtrr()\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 447 | enable_var_mtrr(); |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame^] | 448 | printk(BIOS_SPEW, "Leave %s\n", __func__); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 449 | post_code(0x6A); |
| 450 | } |
| 451 | |
Yinghai Lu | 13f1c2a | 2005-07-08 02:49:49 +0000 | [diff] [blame] | 452 | void x86_setup_mtrrs(unsigned address_bits) |
| 453 | { |
| 454 | x86_setup_fixed_mtrrs(); |
| 455 | x86_setup_var_mtrrs(address_bits); |
| 456 | } |
| 457 | |
| 458 | |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 459 | int x86_mtrr_check(void) |
| 460 | { |
| 461 | /* Only Pentium Pro and later have MTRR */ |
| 462 | msr_t msr; |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame^] | 463 | printk(BIOS_DEBUG, "\nMTRR check\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 464 | |
| 465 | msr = rdmsr(0x2ff); |
| 466 | msr.lo >>= 10; |
| 467 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame^] | 468 | printk(BIOS_DEBUG, "Fixed MTRRs : "); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 469 | if (msr.lo & 0x01) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame^] | 470 | printk(BIOS_DEBUG, "Enabled\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 471 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame^] | 472 | printk(BIOS_DEBUG, "Disabled\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 473 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame^] | 474 | printk(BIOS_DEBUG, "Variable MTRRs: "); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 475 | if (msr.lo & 0x02) |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame^] | 476 | printk(BIOS_DEBUG, "Enabled\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 477 | else |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame^] | 478 | printk(BIOS_DEBUG, "Disabled\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 479 | |
Stefan Reinauer | c02b4fc | 2010-03-22 11:42:32 +0000 | [diff] [blame^] | 480 | printk(BIOS_DEBUG, "\n"); |
Eric Biederman | fcd5ace | 2004-10-14 19:29:29 +0000 | [diff] [blame] | 481 | |
| 482 | post_code(0x93); |
| 483 | return ((int) msr.lo); |
| 484 | } |