Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 2 | |
Angel Pons | c826ba4 | 2022-08-14 11:07:42 +0200 | [diff] [blame] | 3 | #include <commonlib/bsd/clamp.h> |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 4 | #include <console/console.h> |
| 5 | #include <console/usb.h> |
Angel Pons | 47a80a0 | 2020-12-07 13:15:23 +0100 | [diff] [blame] | 6 | #include <cpu/intel/model_206ax/model_206ax.h> |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 7 | #include <delay.h> |
Angel Pons | fc93024 | 2020-03-24 11:12:09 +0100 | [diff] [blame] | 8 | #include <device/device.h> |
| 9 | #include <device/pci_def.h> |
Patrick Rudolph | cab4d3d | 2016-11-24 19:40:23 +0100 | [diff] [blame] | 10 | #include <device/pci_ops.h> |
Angel Pons | fc93024 | 2020-03-24 11:12:09 +0100 | [diff] [blame] | 11 | #include <northbridge/intel/sandybridge/chip.h> |
Elyes HAOUAS | 1d6484a | 2020-07-10 11:18:11 +0200 | [diff] [blame] | 12 | #include <stdbool.h> |
| 13 | #include <stdint.h> |
| 14 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 15 | #include "raminit_native.h" |
| 16 | #include "raminit_common.h" |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 17 | #include "raminit_tables.h" |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 18 | |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 19 | #define SNB_MIN_DCLK_133_MULT 3 |
| 20 | #define SNB_MAX_DCLK_133_MULT 8 |
Angel Pons | a6c8b4b | 2020-03-23 22:38:08 +0100 | [diff] [blame] | 21 | #define IVB_MIN_DCLK_133_MULT 3 |
| 22 | #define IVB_MAX_DCLK_133_MULT 10 |
| 23 | #define IVB_MIN_DCLK_100_MULT 7 |
| 24 | #define IVB_MAX_DCLK_100_MULT 12 |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 25 | |
Angel Pons | a6c8b4b | 2020-03-23 22:38:08 +0100 | [diff] [blame] | 26 | /* Frequency multiplier */ |
| 27 | static u32 get_FRQ(const ramctr_timing *ctrl) |
| 28 | { |
| 29 | const u32 FRQ = 256000 / (ctrl->tCK * ctrl->base_freq); |
| 30 | |
| 31 | if (IS_IVY_CPU(ctrl->cpu)) { |
| 32 | if (ctrl->base_freq == 100) |
| 33 | return clamp_u32(IVB_MIN_DCLK_100_MULT, FRQ, IVB_MAX_DCLK_100_MULT); |
| 34 | |
| 35 | if (ctrl->base_freq == 133) |
| 36 | return clamp_u32(IVB_MIN_DCLK_133_MULT, FRQ, IVB_MAX_DCLK_133_MULT); |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 37 | |
| 38 | } else if (IS_SANDY_CPU(ctrl->cpu)) { |
| 39 | if (ctrl->base_freq == 133) |
| 40 | return clamp_u32(SNB_MIN_DCLK_133_MULT, FRQ, SNB_MAX_DCLK_133_MULT); |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 41 | } |
| 42 | |
Angel Pons | a6c8b4b | 2020-03-23 22:38:08 +0100 | [diff] [blame] | 43 | die("Unsupported CPU or base frequency."); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 44 | } |
| 45 | |
Angel Pons | 2f3cc00 | 2020-11-11 18:49:31 +0100 | [diff] [blame] | 46 | /* CAS write latency. To be programmed in MR2. See DDR3 SPEC for MR2 documentation. */ |
| 47 | static u8 get_CWL(u32 tCK) |
| 48 | { |
| 49 | /* Get CWL based on tCK using the following rule */ |
| 50 | switch (tCK) { |
| 51 | case TCK_1333MHZ: |
| 52 | return 12; |
| 53 | |
| 54 | case TCK_1200MHZ: |
| 55 | case TCK_1100MHZ: |
| 56 | return 11; |
| 57 | |
| 58 | case TCK_1066MHZ: |
| 59 | case TCK_1000MHZ: |
| 60 | return 10; |
| 61 | |
| 62 | case TCK_933MHZ: |
| 63 | case TCK_900MHZ: |
| 64 | return 9; |
| 65 | |
| 66 | case TCK_800MHZ: |
| 67 | case TCK_700MHZ: |
| 68 | return 8; |
| 69 | |
| 70 | case TCK_666MHZ: |
| 71 | return 7; |
| 72 | |
| 73 | case TCK_533MHZ: |
| 74 | return 6; |
| 75 | |
| 76 | default: |
| 77 | return 5; |
| 78 | } |
| 79 | } |
| 80 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 81 | /* Get REFI based on frequency index, tREFI = 7.8usec */ |
| 82 | static u32 get_REFI(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 83 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 84 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 85 | return frq_refi_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 86 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 87 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 88 | return frq_refi_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 89 | } |
| 90 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 91 | /* Get XSOffset based on frequency index, tXS-Offset: tXS = tRFC + 10ns */ |
| 92 | static u8 get_XSOffset(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 93 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 94 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 95 | return frq_xs_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 96 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 97 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 98 | return frq_xs_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 99 | } |
| 100 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 101 | /* Get MOD based on frequency index */ |
| 102 | static u8 get_MOD(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 103 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 104 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 105 | return frq_mod_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 106 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 107 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 108 | return frq_mod_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 109 | } |
| 110 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 111 | /* Get Write Leveling Output delay based on frequency index */ |
| 112 | static u8 get_WLO(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 113 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 114 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 115 | return frq_wlo_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 116 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 117 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 118 | return frq_wlo_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 119 | } |
| 120 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 121 | /* Get CKE based on frequency index */ |
| 122 | static u8 get_CKE(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 123 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 124 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 125 | return frq_cke_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 126 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 127 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 128 | return frq_cke_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 129 | } |
| 130 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 131 | /* Get XPDLL based on frequency index */ |
| 132 | static u8 get_XPDLL(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 133 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 134 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 135 | return frq_xpdll_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 136 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 137 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 138 | return frq_xpdll_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 139 | } |
| 140 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 141 | /* Get XP based on frequency index */ |
| 142 | static u8 get_XP(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 143 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 144 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 145 | return frq_xp_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 146 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 147 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 148 | return frq_xp_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 149 | } |
| 150 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 151 | /* Get AONPD based on frequency index */ |
| 152 | static u8 get_AONPD(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 153 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 154 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 155 | return frq_aonpd_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 156 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 157 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 158 | return frq_aonpd_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 159 | } |
| 160 | |
Angel Pons | 2921cbf | 2020-11-19 16:41:40 +0100 | [diff] [blame] | 161 | /* Get COMP2 based on CPU generation and clock speed */ |
| 162 | static u32 get_COMP2(const ramctr_timing *ctrl) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 163 | { |
Angel Pons | 2921cbf | 2020-11-19 16:41:40 +0100 | [diff] [blame] | 164 | const bool is_ivybridge = IS_IVY_CPU(ctrl->cpu); |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 165 | |
Angel Pons | 2921cbf | 2020-11-19 16:41:40 +0100 | [diff] [blame] | 166 | if (ctrl->tCK <= TCK_1066MHZ) |
| 167 | return is_ivybridge ? 0x0C235924 : 0x0C21410C; |
| 168 | else if (ctrl->tCK <= TCK_933MHZ) |
| 169 | return is_ivybridge ? 0x0C446964 : 0x0C42514C; |
| 170 | else if (ctrl->tCK <= TCK_800MHZ) |
| 171 | return is_ivybridge ? 0x0C6671E4 : 0x0C6369CC; |
| 172 | else if (ctrl->tCK <= TCK_666MHZ) |
| 173 | return is_ivybridge ? 0x0CA8C264 : 0x0CA57A4C; |
| 174 | else if (ctrl->tCK <= TCK_533MHZ) |
| 175 | return is_ivybridge ? 0x0CEBDB64 : 0x0CE7C34C; |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 176 | else |
Angel Pons | 2921cbf | 2020-11-19 16:41:40 +0100 | [diff] [blame] | 177 | return is_ivybridge ? 0x0D6FF5E4 : 0x0D6BEDCC; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 178 | } |
| 179 | |
Angel Pons | 4f86d63 | 2020-11-19 17:18:46 +0100 | [diff] [blame] | 180 | /* Get updated COMP1 based on CPU generation and stepping */ |
| 181 | static u32 get_COMP1(ramctr_timing *ctrl, const int channel) |
| 182 | { |
| 183 | const union comp_ofst_1_reg orig_comp = { |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 184 | .raw = mchbar_read32(CRCOMPOFST1_ch(channel)), |
Angel Pons | 4f86d63 | 2020-11-19 17:18:46 +0100 | [diff] [blame] | 185 | }; |
| 186 | |
| 187 | if (IS_SANDY_CPU(ctrl->cpu) && !IS_SANDY_CPU_D2(ctrl->cpu)) { |
| 188 | union comp_ofst_1_reg comp_ofst_1 = orig_comp; |
| 189 | |
| 190 | comp_ofst_1.clk_odt_up = 1; |
| 191 | comp_ofst_1.clk_drv_up = 1; |
| 192 | comp_ofst_1.ctl_drv_up = 1; |
| 193 | |
| 194 | return comp_ofst_1.raw; |
| 195 | } |
| 196 | |
| 197 | /* Fix PCODE COMP offset bug: revert to default values */ |
| 198 | union comp_ofst_1_reg comp_ofst_1 = { |
| 199 | .dq_odt_down = 4, |
| 200 | .dq_odt_up = 4, |
| 201 | .clk_odt_down = 4, |
| 202 | .clk_odt_up = orig_comp.clk_odt_up, |
| 203 | .dq_drv_down = 4, |
| 204 | .dq_drv_up = orig_comp.dq_drv_up, |
| 205 | .clk_drv_down = 4, |
| 206 | .clk_drv_up = orig_comp.clk_drv_up, |
| 207 | .ctl_drv_down = 4, |
| 208 | .ctl_drv_up = orig_comp.ctl_drv_up, |
| 209 | }; |
| 210 | |
| 211 | if (IS_IVY_CPU(ctrl->cpu)) |
| 212 | comp_ofst_1.dq_drv_up = 2; /* 28p6 ohms */ |
| 213 | |
| 214 | return comp_ofst_1.raw; |
| 215 | } |
| 216 | |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 217 | static void normalize_tclk(ramctr_timing *ctrl, bool ref_100mhz_support) |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 218 | { |
| 219 | if (ctrl->tCK <= TCK_1200MHZ) { |
| 220 | ctrl->tCK = TCK_1200MHZ; |
Angel Pons | 0a20872 | 2020-09-18 00:52:26 +0200 | [diff] [blame] | 221 | ctrl->base_freq = 133; |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 222 | } else if (ctrl->tCK <= TCK_1100MHZ) { |
| 223 | ctrl->tCK = TCK_1100MHZ; |
| 224 | ctrl->base_freq = 100; |
| 225 | } else if (ctrl->tCK <= TCK_1066MHZ) { |
| 226 | ctrl->tCK = TCK_1066MHZ; |
| 227 | ctrl->base_freq = 133; |
| 228 | } else if (ctrl->tCK <= TCK_1000MHZ) { |
| 229 | ctrl->tCK = TCK_1000MHZ; |
| 230 | ctrl->base_freq = 100; |
| 231 | } else if (ctrl->tCK <= TCK_933MHZ) { |
| 232 | ctrl->tCK = TCK_933MHZ; |
| 233 | ctrl->base_freq = 133; |
| 234 | } else if (ctrl->tCK <= TCK_900MHZ) { |
| 235 | ctrl->tCK = TCK_900MHZ; |
| 236 | ctrl->base_freq = 100; |
| 237 | } else if (ctrl->tCK <= TCK_800MHZ) { |
| 238 | ctrl->tCK = TCK_800MHZ; |
| 239 | ctrl->base_freq = 133; |
| 240 | } else if (ctrl->tCK <= TCK_700MHZ) { |
| 241 | ctrl->tCK = TCK_700MHZ; |
| 242 | ctrl->base_freq = 100; |
| 243 | } else if (ctrl->tCK <= TCK_666MHZ) { |
| 244 | ctrl->tCK = TCK_666MHZ; |
| 245 | ctrl->base_freq = 133; |
| 246 | } else if (ctrl->tCK <= TCK_533MHZ) { |
| 247 | ctrl->tCK = TCK_533MHZ; |
| 248 | ctrl->base_freq = 133; |
| 249 | } else if (ctrl->tCK <= TCK_400MHZ) { |
| 250 | ctrl->tCK = TCK_400MHZ; |
| 251 | ctrl->base_freq = 133; |
| 252 | } else { |
| 253 | ctrl->tCK = 0; |
| 254 | return; |
| 255 | } |
| 256 | |
| 257 | if (!ref_100mhz_support && ctrl->base_freq == 100) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 258 | /* Skip unsupported frequency */ |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 259 | ctrl->tCK++; |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 260 | normalize_tclk(ctrl, ref_100mhz_support); |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 261 | } |
| 262 | } |
| 263 | |
Angel Pons | fc93024 | 2020-03-24 11:12:09 +0100 | [diff] [blame] | 264 | #define DEFAULT_TCK TCK_800MHZ |
| 265 | |
| 266 | static unsigned int get_mem_min_tck(void) |
| 267 | { |
| 268 | u32 reg32; |
| 269 | u8 rev; |
| 270 | const struct northbridge_intel_sandybridge_config *cfg = NULL; |
| 271 | |
| 272 | /* Actually, config of MCH or Host Bridge */ |
| 273 | cfg = config_of_soc(); |
| 274 | |
| 275 | /* If non-zero, it was set in the devicetree */ |
| 276 | if (cfg->max_mem_clock_mhz) { |
| 277 | |
| 278 | if (cfg->max_mem_clock_mhz >= 1066) |
| 279 | return TCK_1066MHZ; |
| 280 | |
| 281 | else if (cfg->max_mem_clock_mhz >= 933) |
| 282 | return TCK_933MHZ; |
| 283 | |
| 284 | else if (cfg->max_mem_clock_mhz >= 800) |
| 285 | return TCK_800MHZ; |
| 286 | |
| 287 | else if (cfg->max_mem_clock_mhz >= 666) |
| 288 | return TCK_666MHZ; |
| 289 | |
| 290 | else if (cfg->max_mem_clock_mhz >= 533) |
| 291 | return TCK_533MHZ; |
| 292 | |
| 293 | else |
| 294 | return TCK_400MHZ; |
| 295 | } |
| 296 | |
| 297 | if (CONFIG(NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES)) |
| 298 | return TCK_1333MHZ; |
| 299 | |
| 300 | rev = pci_read_config8(HOST_BRIDGE, PCI_DEVICE_ID); |
| 301 | |
| 302 | if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { |
| 303 | /* Read Capabilities A Register DMFC bits */ |
| 304 | reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); |
| 305 | reg32 &= 0x7; |
| 306 | |
| 307 | switch (reg32) { |
| 308 | case 7: return TCK_533MHZ; |
| 309 | case 6: return TCK_666MHZ; |
| 310 | case 5: return TCK_800MHZ; |
| 311 | /* Reserved */ |
| 312 | default: |
| 313 | break; |
| 314 | } |
| 315 | } else { |
| 316 | /* Read Capabilities B Register DMFC bits */ |
| 317 | reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B); |
| 318 | reg32 = (reg32 >> 4) & 0x7; |
| 319 | |
| 320 | switch (reg32) { |
| 321 | case 7: return TCK_533MHZ; |
| 322 | case 6: return TCK_666MHZ; |
| 323 | case 5: return TCK_800MHZ; |
| 324 | case 4: return TCK_933MHZ; |
| 325 | case 3: return TCK_1066MHZ; |
| 326 | case 2: return TCK_1200MHZ; |
| 327 | case 1: return TCK_1333MHZ; |
| 328 | /* Reserved */ |
| 329 | default: |
| 330 | break; |
| 331 | } |
| 332 | } |
| 333 | return DEFAULT_TCK; |
| 334 | } |
| 335 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 336 | static void find_cas_tck(ramctr_timing *ctrl) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 337 | { |
| 338 | u8 val; |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 339 | u32 reg32; |
| 340 | u8 ref_100mhz_support; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 341 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 342 | /* 100 MHz reference clock supported */ |
| 343 | reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B); |
Angel Pons | 29f391ec | 2020-03-23 22:51:05 +0100 | [diff] [blame] | 344 | ref_100mhz_support = (reg32 >> 21) & 0x7; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 345 | printk(BIOS_DEBUG, "100MHz reference clock support: %s\n", ref_100mhz_support ? "yes" |
| 346 | : "no"); |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 347 | |
Angel Pons | 29f391ec | 2020-03-23 22:51:05 +0100 | [diff] [blame] | 348 | printk(BIOS_DEBUG, "PLL_REF100_CFG value: 0x%x\n", ref_100mhz_support); |
| 349 | |
Angel Pons | fc93024 | 2020-03-24 11:12:09 +0100 | [diff] [blame] | 350 | ctrl->tCK = get_mem_min_tck(); |
| 351 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 352 | /* Find CAS latency */ |
| 353 | while (1) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 354 | /* |
| 355 | * Normalising tCK before computing clock could potentially |
| 356 | * result in a lower selected CAS, which is desired. |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 357 | */ |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 358 | normalize_tclk(ctrl, ref_100mhz_support); |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 359 | if (!(ctrl->tCK)) |
| 360 | die("Couldn't find compatible clock / CAS settings\n"); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 361 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 362 | val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK); |
| 363 | printk(BIOS_DEBUG, "Trying CAS %u, tCK %u.\n", val, ctrl->tCK); |
| 364 | for (; val <= MAX_CAS; val++) |
| 365 | if ((ctrl->cas_supported >> (val - MIN_CAS)) & 1) |
| 366 | break; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 367 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 368 | if (val == (MAX_CAS + 1)) { |
| 369 | ctrl->tCK++; |
| 370 | continue; |
| 371 | } else { |
| 372 | printk(BIOS_DEBUG, "Found compatible clock, CAS pair.\n"); |
| 373 | break; |
| 374 | } |
| 375 | } |
| 376 | |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 377 | /* Frequency multiplier */ |
Angel Pons | a6c8b4b | 2020-03-23 22:38:08 +0100 | [diff] [blame] | 378 | ctrl->FRQ = get_FRQ(ctrl); |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 379 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 380 | printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", NS2MHZ_DIV256 / ctrl->tCK); |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 381 | printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", val); |
| 382 | ctrl->CAS = val; |
| 383 | } |
| 384 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 385 | static void dram_timing(ramctr_timing *ctrl) |
| 386 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 387 | /* |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 388 | * On Sandy Bridge, the maximum supported DDR3 frequency is 1066MHz (DDR3 2133). |
| 389 | * Cap it for faster DIMMs, and align it to the closest JEDEC standard frequency. |
| 390 | */ |
| 391 | /* |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 392 | * On Ivy Bridge, the maximum supported DDR3 frequency is 1400MHz (DDR3 2800). |
| 393 | * Cap it at 1200MHz (DDR3 2400), and align it to the closest JEDEC standard frequency. |
| 394 | */ |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 395 | if (ctrl->tCK == TCK_1200MHZ) { |
Patrick Rudolph | cb7d6a1 | 2016-11-25 15:40:49 +0100 | [diff] [blame] | 396 | ctrl->edge_offset[0] = 18; //XXX: guessed |
| 397 | ctrl->edge_offset[1] = 8; |
| 398 | ctrl->edge_offset[2] = 8; |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 399 | ctrl->tx_dq_offset[0] = 20; //XXX: guessed |
| 400 | ctrl->tx_dq_offset[1] = 8; |
| 401 | ctrl->tx_dq_offset[2] = 8; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 402 | ctrl->pi_coding_threshold = 10; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 403 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 404 | } else if (ctrl->tCK == TCK_1100MHZ) { |
Patrick Rudolph | cb7d6a1 | 2016-11-25 15:40:49 +0100 | [diff] [blame] | 405 | ctrl->edge_offset[0] = 17; //XXX: guessed |
| 406 | ctrl->edge_offset[1] = 7; |
| 407 | ctrl->edge_offset[2] = 7; |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 408 | ctrl->tx_dq_offset[0] = 19; //XXX: guessed |
| 409 | ctrl->tx_dq_offset[1] = 7; |
| 410 | ctrl->tx_dq_offset[2] = 7; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 411 | ctrl->pi_coding_threshold = 13; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 412 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 413 | } else if (ctrl->tCK == TCK_1066MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 414 | ctrl->edge_offset[0] = 16; |
| 415 | ctrl->edge_offset[1] = 7; |
| 416 | ctrl->edge_offset[2] = 7; |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 417 | ctrl->tx_dq_offset[0] = 18; |
| 418 | ctrl->tx_dq_offset[1] = 7; |
| 419 | ctrl->tx_dq_offset[2] = 7; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 420 | ctrl->pi_coding_threshold = 13; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 421 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 422 | } else if (ctrl->tCK == TCK_1000MHZ) { |
Patrick Rudolph | cb7d6a1 | 2016-11-25 15:40:49 +0100 | [diff] [blame] | 423 | ctrl->edge_offset[0] = 15; //XXX: guessed |
| 424 | ctrl->edge_offset[1] = 6; |
| 425 | ctrl->edge_offset[2] = 6; |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 426 | ctrl->tx_dq_offset[0] = 17; //XXX: guessed |
| 427 | ctrl->tx_dq_offset[1] = 6; |
| 428 | ctrl->tx_dq_offset[2] = 6; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 429 | ctrl->pi_coding_threshold = 13; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 430 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 431 | } else if (ctrl->tCK == TCK_933MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 432 | ctrl->edge_offset[0] = 14; |
| 433 | ctrl->edge_offset[1] = 6; |
| 434 | ctrl->edge_offset[2] = 6; |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 435 | ctrl->tx_dq_offset[0] = 15; |
| 436 | ctrl->tx_dq_offset[1] = 6; |
| 437 | ctrl->tx_dq_offset[2] = 6; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 438 | ctrl->pi_coding_threshold = 15; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 439 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 440 | } else if (ctrl->tCK == TCK_900MHZ) { |
Patrick Rudolph | cb7d6a1 | 2016-11-25 15:40:49 +0100 | [diff] [blame] | 441 | ctrl->edge_offset[0] = 14; //XXX: guessed |
| 442 | ctrl->edge_offset[1] = 6; |
| 443 | ctrl->edge_offset[2] = 6; |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 444 | ctrl->tx_dq_offset[0] = 15; //XXX: guessed |
| 445 | ctrl->tx_dq_offset[1] = 6; |
| 446 | ctrl->tx_dq_offset[2] = 6; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 447 | ctrl->pi_coding_threshold = 12; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 448 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 449 | } else if (ctrl->tCK == TCK_800MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 450 | ctrl->edge_offset[0] = 13; |
| 451 | ctrl->edge_offset[1] = 5; |
| 452 | ctrl->edge_offset[2] = 5; |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 453 | ctrl->tx_dq_offset[0] = 14; |
| 454 | ctrl->tx_dq_offset[1] = 5; |
| 455 | ctrl->tx_dq_offset[2] = 5; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 456 | ctrl->pi_coding_threshold = 15; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 457 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 458 | } else if (ctrl->tCK == TCK_700MHZ) { |
Patrick Rudolph | cb7d6a1 | 2016-11-25 15:40:49 +0100 | [diff] [blame] | 459 | ctrl->edge_offset[0] = 13; //XXX: guessed |
| 460 | ctrl->edge_offset[1] = 5; |
| 461 | ctrl->edge_offset[2] = 5; |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 462 | ctrl->tx_dq_offset[0] = 14; //XXX: guessed |
| 463 | ctrl->tx_dq_offset[1] = 5; |
| 464 | ctrl->tx_dq_offset[2] = 5; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 465 | ctrl->pi_coding_threshold = 16; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 466 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 467 | } else if (ctrl->tCK == TCK_666MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 468 | ctrl->edge_offset[0] = 10; |
| 469 | ctrl->edge_offset[1] = 4; |
| 470 | ctrl->edge_offset[2] = 4; |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 471 | ctrl->tx_dq_offset[0] = 11; |
| 472 | ctrl->tx_dq_offset[1] = 4; |
| 473 | ctrl->tx_dq_offset[2] = 4; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 474 | ctrl->pi_coding_threshold = 16; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 475 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 476 | } else if (ctrl->tCK == TCK_533MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 477 | ctrl->edge_offset[0] = 8; |
| 478 | ctrl->edge_offset[1] = 3; |
| 479 | ctrl->edge_offset[2] = 3; |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 480 | ctrl->tx_dq_offset[0] = 9; |
| 481 | ctrl->tx_dq_offset[1] = 3; |
| 482 | ctrl->tx_dq_offset[2] = 3; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 483 | ctrl->pi_coding_threshold = 17; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 484 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 485 | } else { /* TCK_400MHZ */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 486 | ctrl->edge_offset[0] = 6; |
| 487 | ctrl->edge_offset[1] = 2; |
| 488 | ctrl->edge_offset[2] = 2; |
Angel Pons | c8ac2cc | 2020-11-19 22:50:54 +0100 | [diff] [blame] | 489 | ctrl->tx_dq_offset[0] = 6; |
| 490 | ctrl->tx_dq_offset[1] = 2; |
| 491 | ctrl->tx_dq_offset[2] = 2; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 492 | ctrl->pi_coding_threshold = 17; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 493 | } |
| 494 | |
| 495 | /* Initial phase between CLK/CMD pins */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 496 | ctrl->pi_code_offset = (256000 / ctrl->tCK) / 66; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 497 | |
| 498 | /* DLL_CONFIG_MDLL_W_TIMER */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 499 | ctrl->mdll_wake_delay = (128000 / ctrl->tCK) + 3; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 500 | |
Dan Elkouby | dabebc3 | 2018-04-13 18:47:10 +0300 | [diff] [blame] | 501 | if (ctrl->tCWL) |
| 502 | ctrl->CWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK); |
| 503 | else |
| 504 | ctrl->CWL = get_CWL(ctrl->tCK); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 505 | |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 506 | ctrl->tRCD = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 507 | ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK); |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 508 | ctrl->tRAS = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 509 | ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK); |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 510 | ctrl->tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK); |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 511 | ctrl->tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK); |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 512 | ctrl->tRTP = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK); |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 513 | ctrl->tWTR = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK); |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 514 | ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 515 | |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 516 | ctrl->tREFI = get_REFI(ctrl->FRQ, ctrl->base_freq); |
| 517 | ctrl->tMOD = get_MOD(ctrl->FRQ, ctrl->base_freq); |
| 518 | ctrl->tXSOffset = get_XSOffset(ctrl->FRQ, ctrl->base_freq); |
| 519 | ctrl->tWLO = get_WLO(ctrl->FRQ, ctrl->base_freq); |
| 520 | ctrl->tCKE = get_CKE(ctrl->FRQ, ctrl->base_freq); |
| 521 | ctrl->tXPDLL = get_XPDLL(ctrl->FRQ, ctrl->base_freq); |
| 522 | ctrl->tXP = get_XP(ctrl->FRQ, ctrl->base_freq); |
| 523 | ctrl->tAONPD = get_AONPD(ctrl->FRQ, ctrl->base_freq); |
Angel Pons | d992944 | 2020-09-18 00:29:38 +0200 | [diff] [blame] | 524 | |
| 525 | printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL); |
| 526 | printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD); |
| 527 | printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP); |
| 528 | printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS); |
| 529 | printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR); |
| 530 | printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW); |
| 531 | printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD); |
| 532 | printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP); |
| 533 | printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR); |
| 534 | printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 535 | } |
| 536 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 537 | static void dram_freq(ramctr_timing *ctrl) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 538 | { |
| 539 | if (ctrl->tCK > TCK_400MHZ) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 540 | printk(BIOS_ERR, |
| 541 | "DRAM frequency is under lowest supported frequency (400 MHz). " |
Angel Pons | fe276fb | 2020-09-18 00:36:07 +0200 | [diff] [blame] | 542 | "Increasing to 400 MHz as last resort.\n"); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 543 | ctrl->tCK = TCK_400MHZ; |
| 544 | } |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 545 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 546 | while (1) { |
| 547 | u8 val2; |
| 548 | u32 reg1 = 0; |
| 549 | |
Angel Pons | fe276fb | 2020-09-18 00:36:07 +0200 | [diff] [blame] | 550 | /* Step 1 - Determine target MPLL frequency */ |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 551 | find_cas_tck(ctrl); |
Patrick Rudolph | cab4d3d | 2016-11-24 19:40:23 +0100 | [diff] [blame] | 552 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 553 | /* |
Angel Pons | fe276fb | 2020-09-18 00:36:07 +0200 | [diff] [blame] | 554 | * The MPLL will never lock if the requested frequency is already set. |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 555 | * Exit early to prevent a system hang. |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 556 | */ |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 557 | reg1 = mchbar_read32(MC_BIOS_DATA); |
Elyes Haouas | 3a99807 | 2022-11-18 15:11:02 +0100 | [diff] [blame] | 558 | val2 = (u8)reg1; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 559 | if (val2) |
| 560 | return; |
| 561 | |
Angel Pons | fe276fb | 2020-09-18 00:36:07 +0200 | [diff] [blame] | 562 | /* Step 2 - Request MPLL frequency through the PCU */ |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 563 | reg1 = ctrl->FRQ; |
Patrick Rudolph | cab4d3d | 2016-11-24 19:40:23 +0100 | [diff] [blame] | 564 | if (ctrl->base_freq == 100) |
Angel Pons | fe276fb | 2020-09-18 00:36:07 +0200 | [diff] [blame] | 565 | reg1 |= (1 << 8); /* Use 100MHz reference clock */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 566 | |
Angel Pons | fe276fb | 2020-09-18 00:36:07 +0200 | [diff] [blame] | 567 | reg1 |= (1 << 31); /* Set running bit */ |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 568 | mchbar_write32(MC_BIOS_REQ, reg1); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 569 | int i = 0; |
Angel Pons | fe276fb | 2020-09-18 00:36:07 +0200 | [diff] [blame] | 570 | printk(BIOS_DEBUG, "MPLL busy... "); |
Angel Pons | 5db1b15 | 2020-12-13 16:37:53 +0100 | [diff] [blame] | 571 | while (reg1 & (1 << 31)) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 572 | udelay(10); |
| 573 | i++; |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 574 | reg1 = mchbar_read32(MC_BIOS_REQ); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 575 | } |
| 576 | printk(BIOS_DEBUG, "done in %d us\n", i * 10); |
| 577 | |
| 578 | /* Step 3 - Verify lock frequency */ |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 579 | reg1 = mchbar_read32(MC_BIOS_DATA); |
Elyes Haouas | 3a99807 | 2022-11-18 15:11:02 +0100 | [diff] [blame] | 580 | val2 = (u8)reg1; |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 581 | if (val2 >= ctrl->FRQ) { |
Angel Pons | fe276fb | 2020-09-18 00:36:07 +0200 | [diff] [blame] | 582 | printk(BIOS_DEBUG, "MPLL frequency is set at : %d MHz\n", |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 583 | (1000 << 8) / ctrl->tCK); |
| 584 | return; |
| 585 | } |
Angel Pons | fe276fb | 2020-09-18 00:36:07 +0200 | [diff] [blame] | 586 | printk(BIOS_DEBUG, "MPLL didn't lock. Retrying at lower frequency\n"); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 587 | ctrl->tCK++; |
| 588 | } |
| 589 | } |
| 590 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 591 | static void dram_ioregs(ramctr_timing *ctrl) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 592 | { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 593 | int channel; |
| 594 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 595 | /* IO clock */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 596 | FOR_ALL_CHANNELS { |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 597 | mchbar_write32(GDCRCLKRANKSUSED_ch(channel), ctrl->rankmap[channel]); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 598 | } |
| 599 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 600 | /* IO command */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 601 | FOR_ALL_CHANNELS { |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 602 | mchbar_write32(GDCRCTLRANKSUSED_ch(channel), ctrl->rankmap[channel]); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 603 | } |
| 604 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 605 | /* IO control */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 606 | FOR_ALL_POPULATED_CHANNELS { |
| 607 | program_timings(ctrl, channel); |
| 608 | } |
| 609 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 610 | /* Perform RCOMP */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 611 | printram("RCOMP..."); |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 612 | while (!(mchbar_read32(RCOMP_TIMER) & (1 << 16))) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 613 | ; |
| 614 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 615 | printram("done\n"); |
| 616 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 617 | /* Set COMP2 */ |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 618 | mchbar_write32(CRCOMPOFST2, get_COMP2(ctrl)); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 619 | printram("COMP2 done\n"); |
| 620 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 621 | /* Set COMP1 */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 622 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 623 | mchbar_write32(CRCOMPOFST1_ch(channel), get_COMP1(ctrl, channel)); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 624 | } |
| 625 | printram("COMP1 done\n"); |
| 626 | |
| 627 | printram("FORCE RCOMP and wait 20us..."); |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 628 | mchbar_setbits32(M_COMP, 1 << 8); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 629 | udelay(20); |
| 630 | printram("done\n"); |
| 631 | } |
| 632 | |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 633 | int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 634 | { |
| 635 | int err; |
| 636 | |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 637 | printk(BIOS_DEBUG, "Starting %s Bridge RAM training (%s).\n", |
| 638 | IS_SANDY_CPU(ctrl->cpu) ? "Sandy" : "Ivy", |
| 639 | fast_boot ? "fast boot" : "full initialization"); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 640 | |
| 641 | if (!fast_boot) { |
| 642 | /* Find fastest common supported parameters */ |
| 643 | dram_find_common_params(ctrl); |
| 644 | |
| 645 | dram_dimm_mapping(ctrl); |
| 646 | } |
| 647 | |
Angel Pons | fe276fb | 2020-09-18 00:36:07 +0200 | [diff] [blame] | 648 | /* Set MPLL frequency */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 649 | dram_freq(ctrl); |
| 650 | |
| 651 | if (!fast_boot) { |
| 652 | /* Calculate timings */ |
| 653 | dram_timing(ctrl); |
| 654 | } |
| 655 | |
| 656 | /* Set version register */ |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 657 | mchbar_write32(MRC_REVISION, 0xc04eb002); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 658 | |
| 659 | /* Enable crossover */ |
| 660 | dram_xover(ctrl); |
| 661 | |
| 662 | /* Set timing and refresh registers */ |
| 663 | dram_timing_regs(ctrl); |
| 664 | |
| 665 | /* Power mode preset */ |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 666 | mchbar_write32(PM_THML_STAT, 0x5500); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 667 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 668 | /* Set scheduler chicken bits */ |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 669 | mchbar_write32(SCHED_CBIT, 0x10100005); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 670 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 671 | /* Set up watermarks and starvation counter */ |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 672 | set_wmm_behavior(ctrl->cpu); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 673 | |
| 674 | /* Clear IO reset bit */ |
Angel Pons | 66780a0 | 2021-03-26 13:33:22 +0100 | [diff] [blame] | 675 | mchbar_clrbits32(MC_INIT_STATE_G, 1 << 5); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 676 | |
| 677 | /* Set MAD-DIMM registers */ |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 678 | dram_dimm_set_mapping(ctrl, 1); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 679 | printk(BIOS_DEBUG, "Done dimm mapping\n"); |
| 680 | |
| 681 | /* Zone config */ |
| 682 | dram_zones(ctrl, 1); |
| 683 | |
| 684 | /* Set memory map */ |
| 685 | dram_memorymap(ctrl, me_uma_size); |
| 686 | printk(BIOS_DEBUG, "Done memory map\n"); |
| 687 | |
| 688 | /* Set IO registers */ |
| 689 | dram_ioregs(ctrl); |
| 690 | printk(BIOS_DEBUG, "Done io registers\n"); |
| 691 | |
| 692 | udelay(1); |
| 693 | |
| 694 | if (fast_boot) { |
| 695 | restore_timings(ctrl); |
| 696 | } else { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 697 | /* Do JEDEC DDR3 reset sequence */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 698 | dram_jedecreset(ctrl); |
| 699 | printk(BIOS_DEBUG, "Done jedec reset\n"); |
| 700 | |
| 701 | /* MRS commands */ |
| 702 | dram_mrscommands(ctrl); |
| 703 | printk(BIOS_DEBUG, "Done MRS commands\n"); |
| 704 | |
| 705 | /* Prepare for memory training */ |
| 706 | prepare_training(ctrl); |
| 707 | |
Angel Pons | 7f5a97c | 2020-11-13 16:58:46 +0100 | [diff] [blame] | 708 | err = receive_enable_calibration(ctrl); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 709 | if (err) |
| 710 | return err; |
| 711 | |
Angel Pons | 068c259 | 2020-11-14 01:31:15 +0100 | [diff] [blame] | 712 | err = read_mpr_training(ctrl); |
| 713 | if (err) |
| 714 | return err; |
| 715 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 716 | err = write_training(ctrl); |
| 717 | if (err) |
| 718 | return err; |
| 719 | |
| 720 | printram("CP5a\n"); |
| 721 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 722 | printram("CP5b\n"); |
| 723 | |
| 724 | err = command_training(ctrl); |
| 725 | if (err) |
| 726 | return err; |
| 727 | |
| 728 | printram("CP5c\n"); |
| 729 | |
Angel Pons | 08f749d | 2020-11-17 16:50:56 +0100 | [diff] [blame] | 730 | err = aggressive_read_training(ctrl); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 731 | if (err) |
| 732 | return err; |
| 733 | |
Angel Pons | 2a7d752 | 2020-11-19 12:49:07 +0100 | [diff] [blame] | 734 | err = aggressive_write_training(ctrl); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 735 | if (err) |
| 736 | return err; |
| 737 | |
| 738 | normalize_training(ctrl); |
| 739 | } |
| 740 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 741 | set_read_write_timings(ctrl); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 742 | |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 743 | if (!s3resume) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 744 | err = channel_test(ctrl); |
| 745 | if (err) |
| 746 | return err; |
| 747 | } |
| 748 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 749 | /* Set MAD-DIMM registers */ |
| 750 | dram_dimm_set_mapping(ctrl, 0); |
| 751 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 752 | return 0; |
| 753 | } |