nb/intel/sandybridge: Add print for PLL_REF100_CFG
This field can take eight different values, depending on the maximum
supported speed for the memory when using the 100 MHz reference clock.
Change-Id: I8f2f04f9444831319d4f7bf0d246d01030b6f864
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/northbridge/intel/sandybridge/raminit_ivy.c b/src/northbridge/intel/sandybridge/raminit_ivy.c
index 6ff82dd..7d684b2 100644
--- a/src/northbridge/intel/sandybridge/raminit_ivy.c
+++ b/src/northbridge/intel/sandybridge/raminit_ivy.c
@@ -176,10 +176,12 @@
/* 100 MHz reference clock supported */
reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B);
- ref_100mhz_support = !!((reg32 >> 21) & 0x7);
+ ref_100mhz_support = (reg32 >> 21) & 0x7;
printk(BIOS_DEBUG, "100MHz reference clock support: %s\n", ref_100mhz_support ? "yes"
: "no");
+ printk(BIOS_DEBUG, "PLL_REF100_CFG value: 0x%x\n", ref_100mhz_support);
+
/* Find CAS latency */
while (1) {
/*