Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 2 | |
Angel Pons | a6c8b4b | 2020-03-23 22:38:08 +0100 | [diff] [blame] | 3 | #include <commonlib/clamp.h> |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 4 | #include <console/console.h> |
| 5 | #include <console/usb.h> |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 6 | #include <delay.h> |
Angel Pons | fc93024 | 2020-03-24 11:12:09 +0100 | [diff] [blame] | 7 | #include <device/device.h> |
| 8 | #include <device/pci_def.h> |
Patrick Rudolph | cab4d3d | 2016-11-24 19:40:23 +0100 | [diff] [blame] | 9 | #include <device/pci_ops.h> |
Angel Pons | fc93024 | 2020-03-24 11:12:09 +0100 | [diff] [blame] | 10 | #include <northbridge/intel/sandybridge/chip.h> |
Elyes HAOUAS | 1d6484a | 2020-07-10 11:18:11 +0200 | [diff] [blame^] | 11 | #include <stdbool.h> |
| 12 | #include <stdint.h> |
| 13 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 14 | #include "raminit_native.h" |
| 15 | #include "raminit_common.h" |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 16 | #include "raminit_tables.h" |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 17 | |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 18 | #define SNB_MIN_DCLK_133_MULT 3 |
| 19 | #define SNB_MAX_DCLK_133_MULT 8 |
Angel Pons | a6c8b4b | 2020-03-23 22:38:08 +0100 | [diff] [blame] | 20 | #define IVB_MIN_DCLK_133_MULT 3 |
| 21 | #define IVB_MAX_DCLK_133_MULT 10 |
| 22 | #define IVB_MIN_DCLK_100_MULT 7 |
| 23 | #define IVB_MAX_DCLK_100_MULT 12 |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 24 | |
Angel Pons | a6c8b4b | 2020-03-23 22:38:08 +0100 | [diff] [blame] | 25 | /* Frequency multiplier */ |
| 26 | static u32 get_FRQ(const ramctr_timing *ctrl) |
| 27 | { |
| 28 | const u32 FRQ = 256000 / (ctrl->tCK * ctrl->base_freq); |
| 29 | |
| 30 | if (IS_IVY_CPU(ctrl->cpu)) { |
| 31 | if (ctrl->base_freq == 100) |
| 32 | return clamp_u32(IVB_MIN_DCLK_100_MULT, FRQ, IVB_MAX_DCLK_100_MULT); |
| 33 | |
| 34 | if (ctrl->base_freq == 133) |
| 35 | return clamp_u32(IVB_MIN_DCLK_133_MULT, FRQ, IVB_MAX_DCLK_133_MULT); |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 36 | |
| 37 | } else if (IS_SANDY_CPU(ctrl->cpu)) { |
| 38 | if (ctrl->base_freq == 133) |
| 39 | return clamp_u32(SNB_MIN_DCLK_133_MULT, FRQ, SNB_MAX_DCLK_133_MULT); |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 40 | } |
| 41 | |
Angel Pons | a6c8b4b | 2020-03-23 22:38:08 +0100 | [diff] [blame] | 42 | die("Unsupported CPU or base frequency."); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 43 | } |
| 44 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 45 | /* Get REFI based on frequency index, tREFI = 7.8usec */ |
| 46 | static u32 get_REFI(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 47 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 48 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 49 | return frq_refi_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 50 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 51 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 52 | return frq_refi_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 53 | } |
| 54 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 55 | /* Get XSOffset based on frequency index, tXS-Offset: tXS = tRFC + 10ns */ |
| 56 | static u8 get_XSOffset(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 57 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 58 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 59 | return frq_xs_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 60 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 61 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 62 | return frq_xs_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 63 | } |
| 64 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 65 | /* Get MOD based on frequency index */ |
| 66 | static u8 get_MOD(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 67 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 68 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 69 | return frq_mod_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 70 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 71 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 72 | return frq_mod_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 73 | } |
| 74 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 75 | /* Get Write Leveling Output delay based on frequency index */ |
| 76 | static u8 get_WLO(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 77 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 78 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 79 | return frq_wlo_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 80 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 81 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 82 | return frq_wlo_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 83 | } |
| 84 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 85 | /* Get CKE based on frequency index */ |
| 86 | static u8 get_CKE(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 87 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 88 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 89 | return frq_cke_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 90 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 91 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 92 | return frq_cke_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 93 | } |
| 94 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 95 | /* Get XPDLL based on frequency index */ |
| 96 | static u8 get_XPDLL(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 97 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 98 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 99 | return frq_xpdll_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 100 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 101 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 102 | return frq_xpdll_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 103 | } |
| 104 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 105 | /* Get XP based on frequency index */ |
| 106 | static u8 get_XP(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 107 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 108 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 109 | return frq_xp_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 110 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 111 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 112 | return frq_xp_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 113 | } |
| 114 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 115 | /* Get AONPD based on frequency index */ |
| 116 | static u8 get_AONPD(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 117 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 118 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 119 | return frq_aonpd_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 120 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 121 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 122 | return frq_aonpd_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 123 | } |
| 124 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 125 | /* Get COMP2 based on frequency index */ |
| 126 | static u32 get_COMP2(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 127 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 128 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 129 | return frq_comp2_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 130 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 131 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 132 | return frq_comp2_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 133 | } |
| 134 | |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 135 | static void normalize_tclk(ramctr_timing *ctrl, bool ref_100mhz_support) |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 136 | { |
| 137 | if (ctrl->tCK <= TCK_1200MHZ) { |
| 138 | ctrl->tCK = TCK_1200MHZ; |
| 139 | ctrl->base_freq = 100; |
| 140 | } else if (ctrl->tCK <= TCK_1100MHZ) { |
| 141 | ctrl->tCK = TCK_1100MHZ; |
| 142 | ctrl->base_freq = 100; |
| 143 | } else if (ctrl->tCK <= TCK_1066MHZ) { |
| 144 | ctrl->tCK = TCK_1066MHZ; |
| 145 | ctrl->base_freq = 133; |
| 146 | } else if (ctrl->tCK <= TCK_1000MHZ) { |
| 147 | ctrl->tCK = TCK_1000MHZ; |
| 148 | ctrl->base_freq = 100; |
| 149 | } else if (ctrl->tCK <= TCK_933MHZ) { |
| 150 | ctrl->tCK = TCK_933MHZ; |
| 151 | ctrl->base_freq = 133; |
| 152 | } else if (ctrl->tCK <= TCK_900MHZ) { |
| 153 | ctrl->tCK = TCK_900MHZ; |
| 154 | ctrl->base_freq = 100; |
| 155 | } else if (ctrl->tCK <= TCK_800MHZ) { |
| 156 | ctrl->tCK = TCK_800MHZ; |
| 157 | ctrl->base_freq = 133; |
| 158 | } else if (ctrl->tCK <= TCK_700MHZ) { |
| 159 | ctrl->tCK = TCK_700MHZ; |
| 160 | ctrl->base_freq = 100; |
| 161 | } else if (ctrl->tCK <= TCK_666MHZ) { |
| 162 | ctrl->tCK = TCK_666MHZ; |
| 163 | ctrl->base_freq = 133; |
| 164 | } else if (ctrl->tCK <= TCK_533MHZ) { |
| 165 | ctrl->tCK = TCK_533MHZ; |
| 166 | ctrl->base_freq = 133; |
| 167 | } else if (ctrl->tCK <= TCK_400MHZ) { |
| 168 | ctrl->tCK = TCK_400MHZ; |
| 169 | ctrl->base_freq = 133; |
| 170 | } else { |
| 171 | ctrl->tCK = 0; |
| 172 | return; |
| 173 | } |
| 174 | |
| 175 | if (!ref_100mhz_support && ctrl->base_freq == 100) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 176 | /* Skip unsupported frequency */ |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 177 | ctrl->tCK++; |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 178 | normalize_tclk(ctrl, ref_100mhz_support); |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 179 | } |
| 180 | } |
| 181 | |
Angel Pons | fc93024 | 2020-03-24 11:12:09 +0100 | [diff] [blame] | 182 | #define DEFAULT_TCK TCK_800MHZ |
| 183 | |
| 184 | static unsigned int get_mem_min_tck(void) |
| 185 | { |
| 186 | u32 reg32; |
| 187 | u8 rev; |
| 188 | const struct northbridge_intel_sandybridge_config *cfg = NULL; |
| 189 | |
| 190 | /* Actually, config of MCH or Host Bridge */ |
| 191 | cfg = config_of_soc(); |
| 192 | |
| 193 | /* If non-zero, it was set in the devicetree */ |
| 194 | if (cfg->max_mem_clock_mhz) { |
| 195 | |
| 196 | if (cfg->max_mem_clock_mhz >= 1066) |
| 197 | return TCK_1066MHZ; |
| 198 | |
| 199 | else if (cfg->max_mem_clock_mhz >= 933) |
| 200 | return TCK_933MHZ; |
| 201 | |
| 202 | else if (cfg->max_mem_clock_mhz >= 800) |
| 203 | return TCK_800MHZ; |
| 204 | |
| 205 | else if (cfg->max_mem_clock_mhz >= 666) |
| 206 | return TCK_666MHZ; |
| 207 | |
| 208 | else if (cfg->max_mem_clock_mhz >= 533) |
| 209 | return TCK_533MHZ; |
| 210 | |
| 211 | else |
| 212 | return TCK_400MHZ; |
| 213 | } |
| 214 | |
| 215 | if (CONFIG(NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES)) |
| 216 | return TCK_1333MHZ; |
| 217 | |
| 218 | rev = pci_read_config8(HOST_BRIDGE, PCI_DEVICE_ID); |
| 219 | |
| 220 | if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { |
| 221 | /* Read Capabilities A Register DMFC bits */ |
| 222 | reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_A); |
| 223 | reg32 &= 0x7; |
| 224 | |
| 225 | switch (reg32) { |
| 226 | case 7: return TCK_533MHZ; |
| 227 | case 6: return TCK_666MHZ; |
| 228 | case 5: return TCK_800MHZ; |
| 229 | /* Reserved */ |
| 230 | default: |
| 231 | break; |
| 232 | } |
| 233 | } else { |
| 234 | /* Read Capabilities B Register DMFC bits */ |
| 235 | reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B); |
| 236 | reg32 = (reg32 >> 4) & 0x7; |
| 237 | |
| 238 | switch (reg32) { |
| 239 | case 7: return TCK_533MHZ; |
| 240 | case 6: return TCK_666MHZ; |
| 241 | case 5: return TCK_800MHZ; |
| 242 | case 4: return TCK_933MHZ; |
| 243 | case 3: return TCK_1066MHZ; |
| 244 | case 2: return TCK_1200MHZ; |
| 245 | case 1: return TCK_1333MHZ; |
| 246 | /* Reserved */ |
| 247 | default: |
| 248 | break; |
| 249 | } |
| 250 | } |
| 251 | return DEFAULT_TCK; |
| 252 | } |
| 253 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 254 | static void find_cas_tck(ramctr_timing *ctrl) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 255 | { |
| 256 | u8 val; |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 257 | u32 reg32; |
| 258 | u8 ref_100mhz_support; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 259 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 260 | /* 100 MHz reference clock supported */ |
| 261 | reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B); |
Angel Pons | 29f391ec | 2020-03-23 22:51:05 +0100 | [diff] [blame] | 262 | ref_100mhz_support = (reg32 >> 21) & 0x7; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 263 | printk(BIOS_DEBUG, "100MHz reference clock support: %s\n", ref_100mhz_support ? "yes" |
| 264 | : "no"); |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 265 | |
Angel Pons | 29f391ec | 2020-03-23 22:51:05 +0100 | [diff] [blame] | 266 | printk(BIOS_DEBUG, "PLL_REF100_CFG value: 0x%x\n", ref_100mhz_support); |
| 267 | |
Angel Pons | fc93024 | 2020-03-24 11:12:09 +0100 | [diff] [blame] | 268 | ctrl->tCK = get_mem_min_tck(); |
| 269 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 270 | /* Find CAS latency */ |
| 271 | while (1) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 272 | /* |
| 273 | * Normalising tCK before computing clock could potentially |
| 274 | * result in a lower selected CAS, which is desired. |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 275 | */ |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 276 | normalize_tclk(ctrl, ref_100mhz_support); |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 277 | if (!(ctrl->tCK)) |
| 278 | die("Couldn't find compatible clock / CAS settings\n"); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 279 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 280 | val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK); |
| 281 | printk(BIOS_DEBUG, "Trying CAS %u, tCK %u.\n", val, ctrl->tCK); |
| 282 | for (; val <= MAX_CAS; val++) |
| 283 | if ((ctrl->cas_supported >> (val - MIN_CAS)) & 1) |
| 284 | break; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 285 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 286 | if (val == (MAX_CAS + 1)) { |
| 287 | ctrl->tCK++; |
| 288 | continue; |
| 289 | } else { |
| 290 | printk(BIOS_DEBUG, "Found compatible clock, CAS pair.\n"); |
| 291 | break; |
| 292 | } |
| 293 | } |
| 294 | |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 295 | /* Frequency multiplier */ |
Angel Pons | a6c8b4b | 2020-03-23 22:38:08 +0100 | [diff] [blame] | 296 | ctrl->FRQ = get_FRQ(ctrl); |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 297 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 298 | printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", NS2MHZ_DIV256 / ctrl->tCK); |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 299 | printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", val); |
| 300 | ctrl->CAS = val; |
| 301 | } |
| 302 | |
| 303 | |
| 304 | static void dram_timing(ramctr_timing *ctrl) |
| 305 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 306 | /* |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 307 | * On Sandy Bridge, the maximum supported DDR3 frequency is 1066MHz (DDR3 2133). |
| 308 | * Cap it for faster DIMMs, and align it to the closest JEDEC standard frequency. |
| 309 | */ |
| 310 | /* |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 311 | * On Ivy Bridge, the maximum supported DDR3 frequency is 1400MHz (DDR3 2800). |
| 312 | * Cap it at 1200MHz (DDR3 2400), and align it to the closest JEDEC standard frequency. |
| 313 | */ |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 314 | if (ctrl->tCK == TCK_1200MHZ) { |
Patrick Rudolph | cb7d6a1 | 2016-11-25 15:40:49 +0100 | [diff] [blame] | 315 | ctrl->edge_offset[0] = 18; //XXX: guessed |
| 316 | ctrl->edge_offset[1] = 8; |
| 317 | ctrl->edge_offset[2] = 8; |
| 318 | ctrl->timC_offset[0] = 20; //XXX: guessed |
| 319 | ctrl->timC_offset[1] = 8; |
| 320 | ctrl->timC_offset[2] = 8; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 321 | ctrl->pi_coding_threshold = 10; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 322 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 323 | } else if (ctrl->tCK == TCK_1100MHZ) { |
Patrick Rudolph | cb7d6a1 | 2016-11-25 15:40:49 +0100 | [diff] [blame] | 324 | ctrl->edge_offset[0] = 17; //XXX: guessed |
| 325 | ctrl->edge_offset[1] = 7; |
| 326 | ctrl->edge_offset[2] = 7; |
| 327 | ctrl->timC_offset[0] = 19; //XXX: guessed |
| 328 | ctrl->timC_offset[1] = 7; |
| 329 | ctrl->timC_offset[2] = 7; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 330 | ctrl->pi_coding_threshold = 13; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 331 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 332 | } else if (ctrl->tCK == TCK_1066MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 333 | ctrl->edge_offset[0] = 16; |
| 334 | ctrl->edge_offset[1] = 7; |
| 335 | ctrl->edge_offset[2] = 7; |
| 336 | ctrl->timC_offset[0] = 18; |
| 337 | ctrl->timC_offset[1] = 7; |
| 338 | ctrl->timC_offset[2] = 7; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 339 | ctrl->pi_coding_threshold = 13; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 340 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 341 | } else if (ctrl->tCK == TCK_1000MHZ) { |
Patrick Rudolph | cb7d6a1 | 2016-11-25 15:40:49 +0100 | [diff] [blame] | 342 | ctrl->edge_offset[0] = 15; //XXX: guessed |
| 343 | ctrl->edge_offset[1] = 6; |
| 344 | ctrl->edge_offset[2] = 6; |
| 345 | ctrl->timC_offset[0] = 17; //XXX: guessed |
| 346 | ctrl->timC_offset[1] = 6; |
| 347 | ctrl->timC_offset[2] = 6; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 348 | ctrl->pi_coding_threshold = 13; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 349 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 350 | } else if (ctrl->tCK == TCK_933MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 351 | ctrl->edge_offset[0] = 14; |
| 352 | ctrl->edge_offset[1] = 6; |
| 353 | ctrl->edge_offset[2] = 6; |
| 354 | ctrl->timC_offset[0] = 15; |
| 355 | ctrl->timC_offset[1] = 6; |
| 356 | ctrl->timC_offset[2] = 6; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 357 | ctrl->pi_coding_threshold = 15; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 358 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 359 | } else if (ctrl->tCK == TCK_900MHZ) { |
Patrick Rudolph | cb7d6a1 | 2016-11-25 15:40:49 +0100 | [diff] [blame] | 360 | ctrl->edge_offset[0] = 14; //XXX: guessed |
| 361 | ctrl->edge_offset[1] = 6; |
| 362 | ctrl->edge_offset[2] = 6; |
| 363 | ctrl->timC_offset[0] = 15; //XXX: guessed |
| 364 | ctrl->timC_offset[1] = 6; |
| 365 | ctrl->timC_offset[2] = 6; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 366 | ctrl->pi_coding_threshold = 12; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 367 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 368 | } else if (ctrl->tCK == TCK_800MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 369 | ctrl->edge_offset[0] = 13; |
| 370 | ctrl->edge_offset[1] = 5; |
| 371 | ctrl->edge_offset[2] = 5; |
| 372 | ctrl->timC_offset[0] = 14; |
| 373 | ctrl->timC_offset[1] = 5; |
| 374 | ctrl->timC_offset[2] = 5; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 375 | ctrl->pi_coding_threshold = 15; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 376 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 377 | } else if (ctrl->tCK == TCK_700MHZ) { |
Patrick Rudolph | cb7d6a1 | 2016-11-25 15:40:49 +0100 | [diff] [blame] | 378 | ctrl->edge_offset[0] = 13; //XXX: guessed |
| 379 | ctrl->edge_offset[1] = 5; |
| 380 | ctrl->edge_offset[2] = 5; |
| 381 | ctrl->timC_offset[0] = 14; //XXX: guessed |
| 382 | ctrl->timC_offset[1] = 5; |
| 383 | ctrl->timC_offset[2] = 5; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 384 | ctrl->pi_coding_threshold = 16; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 385 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 386 | } else if (ctrl->tCK == TCK_666MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 387 | ctrl->edge_offset[0] = 10; |
| 388 | ctrl->edge_offset[1] = 4; |
| 389 | ctrl->edge_offset[2] = 4; |
| 390 | ctrl->timC_offset[0] = 11; |
| 391 | ctrl->timC_offset[1] = 4; |
| 392 | ctrl->timC_offset[2] = 4; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 393 | ctrl->pi_coding_threshold = 16; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 394 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 395 | } else if (ctrl->tCK == TCK_533MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 396 | ctrl->edge_offset[0] = 8; |
| 397 | ctrl->edge_offset[1] = 3; |
| 398 | ctrl->edge_offset[2] = 3; |
| 399 | ctrl->timC_offset[0] = 9; |
| 400 | ctrl->timC_offset[1] = 3; |
| 401 | ctrl->timC_offset[2] = 3; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 402 | ctrl->pi_coding_threshold = 17; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 403 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 404 | } else { /* TCK_400MHZ */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 405 | ctrl->edge_offset[0] = 6; |
| 406 | ctrl->edge_offset[1] = 2; |
| 407 | ctrl->edge_offset[2] = 2; |
| 408 | ctrl->timC_offset[0] = 6; |
| 409 | ctrl->timC_offset[1] = 2; |
| 410 | ctrl->timC_offset[2] = 2; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 411 | ctrl->pi_coding_threshold = 17; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 412 | } |
| 413 | |
| 414 | /* Initial phase between CLK/CMD pins */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 415 | ctrl->pi_code_offset = (256000 / ctrl->tCK) / 66; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 416 | |
| 417 | /* DLL_CONFIG_MDLL_W_TIMER */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 418 | ctrl->mdll_wake_delay = (128000 / ctrl->tCK) + 3; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 419 | |
Dan Elkouby | dabebc3 | 2018-04-13 18:47:10 +0300 | [diff] [blame] | 420 | if (ctrl->tCWL) |
| 421 | ctrl->CWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK); |
| 422 | else |
| 423 | ctrl->CWL = get_CWL(ctrl->tCK); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 424 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 425 | printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL); |
| 426 | |
| 427 | /* Find tRCD */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 428 | ctrl->tRCD = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 429 | printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD); |
| 430 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 431 | ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 432 | printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP); |
| 433 | |
| 434 | /* Find tRAS */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 435 | ctrl->tRAS = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 436 | printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS); |
| 437 | |
| 438 | /* Find tWR */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 439 | ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 440 | printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR); |
| 441 | |
| 442 | /* Find tFAW */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 443 | ctrl->tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 444 | printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW); |
| 445 | |
| 446 | /* Find tRRD */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 447 | ctrl->tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 448 | printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD); |
| 449 | |
| 450 | /* Find tRTP */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 451 | ctrl->tRTP = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 452 | printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP); |
| 453 | |
| 454 | /* Find tWTR */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 455 | ctrl->tWTR = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 456 | printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR); |
| 457 | |
| 458 | /* Refresh-to-Active or Refresh-to-Refresh (tRFC) */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 459 | ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 460 | printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); |
| 461 | |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 462 | ctrl->tREFI = get_REFI(ctrl->FRQ, ctrl->base_freq); |
| 463 | ctrl->tMOD = get_MOD(ctrl->FRQ, ctrl->base_freq); |
| 464 | ctrl->tXSOffset = get_XSOffset(ctrl->FRQ, ctrl->base_freq); |
| 465 | ctrl->tWLO = get_WLO(ctrl->FRQ, ctrl->base_freq); |
| 466 | ctrl->tCKE = get_CKE(ctrl->FRQ, ctrl->base_freq); |
| 467 | ctrl->tXPDLL = get_XPDLL(ctrl->FRQ, ctrl->base_freq); |
| 468 | ctrl->tXP = get_XP(ctrl->FRQ, ctrl->base_freq); |
| 469 | ctrl->tAONPD = get_AONPD(ctrl->FRQ, ctrl->base_freq); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 470 | } |
| 471 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 472 | static void dram_freq(ramctr_timing *ctrl) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 473 | { |
| 474 | if (ctrl->tCK > TCK_400MHZ) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 475 | printk(BIOS_ERR, |
| 476 | "DRAM frequency is under lowest supported frequency (400 MHz). " |
| 477 | "Increasing to 400 MHz as last resort"); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 478 | ctrl->tCK = TCK_400MHZ; |
| 479 | } |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 480 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 481 | while (1) { |
| 482 | u8 val2; |
| 483 | u32 reg1 = 0; |
| 484 | |
| 485 | /* Step 1 - Set target PCU frequency */ |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 486 | find_cas_tck(ctrl); |
Patrick Rudolph | cab4d3d | 2016-11-24 19:40:23 +0100 | [diff] [blame] | 487 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 488 | /* |
| 489 | * The PLL will never lock if the required frequency is already set. |
| 490 | * Exit early to prevent a system hang. |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 491 | */ |
| 492 | reg1 = MCHBAR32(MC_BIOS_DATA); |
| 493 | val2 = (u8) reg1; |
| 494 | if (val2) |
| 495 | return; |
| 496 | |
| 497 | /* Step 2 - Select frequency in the MCU */ |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 498 | reg1 = ctrl->FRQ; |
Patrick Rudolph | cab4d3d | 2016-11-24 19:40:23 +0100 | [diff] [blame] | 499 | if (ctrl->base_freq == 100) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 500 | reg1 |= 0x100; /* Enable 100Mhz REF clock */ |
| 501 | |
| 502 | reg1 |= 0x80000000; /* set running bit */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 503 | MCHBAR32(MC_BIOS_REQ) = reg1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 504 | int i = 0; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 505 | printk(BIOS_DEBUG, "PLL busy... "); |
| 506 | while (reg1 & 0x80000000) { |
| 507 | udelay(10); |
| 508 | i++; |
| 509 | reg1 = MCHBAR32(MC_BIOS_REQ); |
| 510 | } |
| 511 | printk(BIOS_DEBUG, "done in %d us\n", i * 10); |
| 512 | |
| 513 | /* Step 3 - Verify lock frequency */ |
| 514 | reg1 = MCHBAR32(MC_BIOS_DATA); |
| 515 | val2 = (u8) reg1; |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 516 | if (val2 >= ctrl->FRQ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 517 | printk(BIOS_DEBUG, "MCU frequency is set at : %d MHz\n", |
| 518 | (1000 << 8) / ctrl->tCK); |
| 519 | return; |
| 520 | } |
| 521 | printk(BIOS_DEBUG, "PLL didn't lock. Retrying at lower frequency\n"); |
| 522 | ctrl->tCK++; |
| 523 | } |
| 524 | } |
| 525 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 526 | static void dram_ioregs(ramctr_timing *ctrl) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 527 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 528 | u32 reg; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 529 | |
| 530 | int channel; |
| 531 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 532 | /* IO clock */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 533 | FOR_ALL_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 534 | MCHBAR32(GDCRCLKRANKSUSED_ch(channel)) = ctrl->rankmap[channel]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 535 | } |
| 536 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 537 | /* IO command */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 538 | FOR_ALL_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 539 | MCHBAR32(GDCRCTLRANKSUSED_ch(channel)) = ctrl->rankmap[channel]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 540 | } |
| 541 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 542 | /* IO control */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 543 | FOR_ALL_POPULATED_CHANNELS { |
| 544 | program_timings(ctrl, channel); |
| 545 | } |
| 546 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 547 | /* Perform RCOMP */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 548 | printram("RCOMP..."); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 549 | while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) |
| 550 | ; |
| 551 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 552 | printram("done\n"); |
| 553 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 554 | /* Set COMP2 */ |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 555 | MCHBAR32(CRCOMPOFST2) = get_COMP2(ctrl->FRQ, ctrl->base_freq); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 556 | printram("COMP2 done\n"); |
| 557 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 558 | /* Set COMP1 */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 559 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 560 | reg = MCHBAR32(CRCOMPOFST1_ch(channel)); |
| 561 | reg = (reg & ~0x00000e00) | (1 << 9); /* ODT */ |
| 562 | reg = (reg & ~0x00e00000) | (1 << 21); /* clk drive up */ |
| 563 | reg = (reg & ~0x38000000) | (1 << 27); /* ctl drive up */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 564 | MCHBAR32(CRCOMPOFST1_ch(channel)) = reg; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 565 | } |
| 566 | printram("COMP1 done\n"); |
| 567 | |
| 568 | printram("FORCE RCOMP and wait 20us..."); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 569 | MCHBAR32(M_COMP) |= (1 << 8); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 570 | udelay(20); |
| 571 | printram("done\n"); |
| 572 | } |
| 573 | |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 574 | int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 575 | { |
| 576 | int err; |
| 577 | |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 578 | printk(BIOS_DEBUG, "Starting %s Bridge RAM training (%s).\n", |
| 579 | IS_SANDY_CPU(ctrl->cpu) ? "Sandy" : "Ivy", |
| 580 | fast_boot ? "fast boot" : "full initialization"); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 581 | |
| 582 | if (!fast_boot) { |
| 583 | /* Find fastest common supported parameters */ |
| 584 | dram_find_common_params(ctrl); |
| 585 | |
| 586 | dram_dimm_mapping(ctrl); |
| 587 | } |
| 588 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 589 | /* Set MC frequency */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 590 | dram_freq(ctrl); |
| 591 | |
| 592 | if (!fast_boot) { |
| 593 | /* Calculate timings */ |
| 594 | dram_timing(ctrl); |
| 595 | } |
| 596 | |
| 597 | /* Set version register */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 598 | MCHBAR32(MRC_REVISION) = 0xc04eb002; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 599 | |
| 600 | /* Enable crossover */ |
| 601 | dram_xover(ctrl); |
| 602 | |
| 603 | /* Set timing and refresh registers */ |
| 604 | dram_timing_regs(ctrl); |
| 605 | |
| 606 | /* Power mode preset */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 607 | MCHBAR32(PM_THML_STAT) = 0x5500; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 608 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 609 | /* Set scheduler chicken bits */ |
| 610 | MCHBAR32(SCHED_CBIT) = 0x10100005; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 611 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 612 | /* Set up watermarks and starvation counter */ |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 613 | set_wmm_behavior(ctrl->cpu); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 614 | |
| 615 | /* Clear IO reset bit */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 616 | MCHBAR32(MC_INIT_STATE_G) &= ~(1 << 5); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 617 | |
| 618 | /* Set MAD-DIMM registers */ |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 619 | dram_dimm_set_mapping(ctrl, 1); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 620 | printk(BIOS_DEBUG, "Done dimm mapping\n"); |
| 621 | |
| 622 | /* Zone config */ |
| 623 | dram_zones(ctrl, 1); |
| 624 | |
| 625 | /* Set memory map */ |
| 626 | dram_memorymap(ctrl, me_uma_size); |
| 627 | printk(BIOS_DEBUG, "Done memory map\n"); |
| 628 | |
| 629 | /* Set IO registers */ |
| 630 | dram_ioregs(ctrl); |
| 631 | printk(BIOS_DEBUG, "Done io registers\n"); |
| 632 | |
| 633 | udelay(1); |
| 634 | |
| 635 | if (fast_boot) { |
| 636 | restore_timings(ctrl); |
| 637 | } else { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 638 | /* Do JEDEC DDR3 reset sequence */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 639 | dram_jedecreset(ctrl); |
| 640 | printk(BIOS_DEBUG, "Done jedec reset\n"); |
| 641 | |
| 642 | /* MRS commands */ |
| 643 | dram_mrscommands(ctrl); |
| 644 | printk(BIOS_DEBUG, "Done MRS commands\n"); |
| 645 | |
| 646 | /* Prepare for memory training */ |
| 647 | prepare_training(ctrl); |
| 648 | |
| 649 | err = read_training(ctrl); |
| 650 | if (err) |
| 651 | return err; |
| 652 | |
| 653 | err = write_training(ctrl); |
| 654 | if (err) |
| 655 | return err; |
| 656 | |
| 657 | printram("CP5a\n"); |
| 658 | |
| 659 | err = discover_edges(ctrl); |
| 660 | if (err) |
| 661 | return err; |
| 662 | |
| 663 | printram("CP5b\n"); |
| 664 | |
| 665 | err = command_training(ctrl); |
| 666 | if (err) |
| 667 | return err; |
| 668 | |
| 669 | printram("CP5c\n"); |
| 670 | |
| 671 | err = discover_edges_write(ctrl); |
| 672 | if (err) |
| 673 | return err; |
| 674 | |
| 675 | err = discover_timC_write(ctrl); |
| 676 | if (err) |
| 677 | return err; |
| 678 | |
| 679 | normalize_training(ctrl); |
| 680 | } |
| 681 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 682 | set_read_write_timings(ctrl); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 683 | |
| 684 | write_controller_mr(ctrl); |
| 685 | |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 686 | if (!s3resume) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 687 | err = channel_test(ctrl); |
| 688 | if (err) |
| 689 | return err; |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 690 | |
| 691 | if (ctrl->ecc_enabled) |
| 692 | channel_scrub(ctrl); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 693 | } |
| 694 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame] | 695 | /* Set MAD-DIMM registers */ |
| 696 | dram_dimm_set_mapping(ctrl, 0); |
| 697 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 698 | return 0; |
| 699 | } |