Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 3 | |
Angel Pons | a6c8b4b | 2020-03-23 22:38:08 +0100 | [diff] [blame] | 4 | #include <commonlib/clamp.h> |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 5 | #include <console/console.h> |
| 6 | #include <console/usb.h> |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 7 | #include <delay.h> |
Patrick Rudolph | cab4d3d | 2016-11-24 19:40:23 +0100 | [diff] [blame] | 8 | #include <device/pci_ops.h> |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 9 | #include "raminit_native.h" |
| 10 | #include "raminit_common.h" |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 11 | #include "raminit_tables.h" |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 12 | |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 13 | #define SNB_MIN_DCLK_133_MULT 3 |
| 14 | #define SNB_MAX_DCLK_133_MULT 8 |
Angel Pons | a6c8b4b | 2020-03-23 22:38:08 +0100 | [diff] [blame] | 15 | #define IVB_MIN_DCLK_133_MULT 3 |
| 16 | #define IVB_MAX_DCLK_133_MULT 10 |
| 17 | #define IVB_MIN_DCLK_100_MULT 7 |
| 18 | #define IVB_MAX_DCLK_100_MULT 12 |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 19 | |
Angel Pons | a6c8b4b | 2020-03-23 22:38:08 +0100 | [diff] [blame] | 20 | /* Frequency multiplier */ |
| 21 | static u32 get_FRQ(const ramctr_timing *ctrl) |
| 22 | { |
| 23 | const u32 FRQ = 256000 / (ctrl->tCK * ctrl->base_freq); |
| 24 | |
| 25 | if (IS_IVY_CPU(ctrl->cpu)) { |
| 26 | if (ctrl->base_freq == 100) |
| 27 | return clamp_u32(IVB_MIN_DCLK_100_MULT, FRQ, IVB_MAX_DCLK_100_MULT); |
| 28 | |
| 29 | if (ctrl->base_freq == 133) |
| 30 | return clamp_u32(IVB_MIN_DCLK_133_MULT, FRQ, IVB_MAX_DCLK_133_MULT); |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 31 | |
| 32 | } else if (IS_SANDY_CPU(ctrl->cpu)) { |
| 33 | if (ctrl->base_freq == 133) |
| 34 | return clamp_u32(SNB_MIN_DCLK_133_MULT, FRQ, SNB_MAX_DCLK_133_MULT); |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 35 | } |
| 36 | |
Angel Pons | a6c8b4b | 2020-03-23 22:38:08 +0100 | [diff] [blame] | 37 | die("Unsupported CPU or base frequency."); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 38 | } |
| 39 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 40 | /* Get REFI based on frequency index, tREFI = 7.8usec */ |
| 41 | static u32 get_REFI(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 42 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 43 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 44 | return frq_refi_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 45 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 46 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 47 | return frq_refi_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 48 | } |
| 49 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 50 | /* Get XSOffset based on frequency index, tXS-Offset: tXS = tRFC + 10ns */ |
| 51 | static u8 get_XSOffset(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 52 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 53 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 54 | return frq_xs_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 55 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 56 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 57 | return frq_xs_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 58 | } |
| 59 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 60 | /* Get MOD based on frequency index */ |
| 61 | static u8 get_MOD(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 62 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 63 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 64 | return frq_mod_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 65 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 66 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 67 | return frq_mod_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 68 | } |
| 69 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 70 | /* Get Write Leveling Output delay based on frequency index */ |
| 71 | static u8 get_WLO(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 72 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 73 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 74 | return frq_wlo_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 75 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 76 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 77 | return frq_wlo_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 78 | } |
| 79 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 80 | /* Get CKE based on frequency index */ |
| 81 | static u8 get_CKE(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 82 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 83 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 84 | return frq_cke_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 85 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 86 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 87 | return frq_cke_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 88 | } |
| 89 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 90 | /* Get XPDLL based on frequency index */ |
| 91 | static u8 get_XPDLL(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 92 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 93 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 94 | return frq_xpdll_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 95 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 96 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 97 | return frq_xpdll_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 98 | } |
| 99 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 100 | /* Get XP based on frequency index */ |
| 101 | static u8 get_XP(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 102 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 103 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 104 | return frq_xp_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 105 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 106 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 107 | return frq_xp_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 108 | } |
| 109 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 110 | /* Get AONPD based on frequency index */ |
| 111 | static u8 get_AONPD(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 112 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 113 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 114 | return frq_aonpd_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 115 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 116 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 117 | return frq_aonpd_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 118 | } |
| 119 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 120 | /* Get COMP2 based on frequency index */ |
| 121 | static u32 get_COMP2(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 122 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 123 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 124 | return frq_comp2_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 125 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 126 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 127 | return frq_comp2_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 128 | } |
| 129 | |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 130 | static void normalize_tclk(ramctr_timing *ctrl, bool ref_100mhz_support) |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 131 | { |
| 132 | if (ctrl->tCK <= TCK_1200MHZ) { |
| 133 | ctrl->tCK = TCK_1200MHZ; |
| 134 | ctrl->base_freq = 100; |
| 135 | } else if (ctrl->tCK <= TCK_1100MHZ) { |
| 136 | ctrl->tCK = TCK_1100MHZ; |
| 137 | ctrl->base_freq = 100; |
| 138 | } else if (ctrl->tCK <= TCK_1066MHZ) { |
| 139 | ctrl->tCK = TCK_1066MHZ; |
| 140 | ctrl->base_freq = 133; |
| 141 | } else if (ctrl->tCK <= TCK_1000MHZ) { |
| 142 | ctrl->tCK = TCK_1000MHZ; |
| 143 | ctrl->base_freq = 100; |
| 144 | } else if (ctrl->tCK <= TCK_933MHZ) { |
| 145 | ctrl->tCK = TCK_933MHZ; |
| 146 | ctrl->base_freq = 133; |
| 147 | } else if (ctrl->tCK <= TCK_900MHZ) { |
| 148 | ctrl->tCK = TCK_900MHZ; |
| 149 | ctrl->base_freq = 100; |
| 150 | } else if (ctrl->tCK <= TCK_800MHZ) { |
| 151 | ctrl->tCK = TCK_800MHZ; |
| 152 | ctrl->base_freq = 133; |
| 153 | } else if (ctrl->tCK <= TCK_700MHZ) { |
| 154 | ctrl->tCK = TCK_700MHZ; |
| 155 | ctrl->base_freq = 100; |
| 156 | } else if (ctrl->tCK <= TCK_666MHZ) { |
| 157 | ctrl->tCK = TCK_666MHZ; |
| 158 | ctrl->base_freq = 133; |
| 159 | } else if (ctrl->tCK <= TCK_533MHZ) { |
| 160 | ctrl->tCK = TCK_533MHZ; |
| 161 | ctrl->base_freq = 133; |
| 162 | } else if (ctrl->tCK <= TCK_400MHZ) { |
| 163 | ctrl->tCK = TCK_400MHZ; |
| 164 | ctrl->base_freq = 133; |
| 165 | } else { |
| 166 | ctrl->tCK = 0; |
| 167 | return; |
| 168 | } |
| 169 | |
| 170 | if (!ref_100mhz_support && ctrl->base_freq == 100) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 171 | /* Skip unsupported frequency */ |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 172 | ctrl->tCK++; |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 173 | normalize_tclk(ctrl, ref_100mhz_support); |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 174 | } |
| 175 | } |
| 176 | |
| 177 | static void find_cas_tck(ramctr_timing *ctrl) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 178 | { |
| 179 | u8 val; |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 180 | u32 reg32; |
| 181 | u8 ref_100mhz_support; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 182 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 183 | /* 100 MHz reference clock supported */ |
| 184 | reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B); |
Angel Pons | 29f391ec | 2020-03-23 22:51:05 +0100 | [diff] [blame] | 185 | ref_100mhz_support = (reg32 >> 21) & 0x7; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 186 | printk(BIOS_DEBUG, "100MHz reference clock support: %s\n", ref_100mhz_support ? "yes" |
| 187 | : "no"); |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 188 | |
Angel Pons | 29f391ec | 2020-03-23 22:51:05 +0100 | [diff] [blame] | 189 | printk(BIOS_DEBUG, "PLL_REF100_CFG value: 0x%x\n", ref_100mhz_support); |
| 190 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 191 | /* Find CAS latency */ |
| 192 | while (1) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 193 | /* |
| 194 | * Normalising tCK before computing clock could potentially |
| 195 | * result in a lower selected CAS, which is desired. |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 196 | */ |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 197 | normalize_tclk(ctrl, ref_100mhz_support); |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 198 | if (!(ctrl->tCK)) |
| 199 | die("Couldn't find compatible clock / CAS settings\n"); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 200 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 201 | val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK); |
| 202 | printk(BIOS_DEBUG, "Trying CAS %u, tCK %u.\n", val, ctrl->tCK); |
| 203 | for (; val <= MAX_CAS; val++) |
| 204 | if ((ctrl->cas_supported >> (val - MIN_CAS)) & 1) |
| 205 | break; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 206 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 207 | if (val == (MAX_CAS + 1)) { |
| 208 | ctrl->tCK++; |
| 209 | continue; |
| 210 | } else { |
| 211 | printk(BIOS_DEBUG, "Found compatible clock, CAS pair.\n"); |
| 212 | break; |
| 213 | } |
| 214 | } |
| 215 | |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 216 | /* Frequency multiplier */ |
Angel Pons | a6c8b4b | 2020-03-23 22:38:08 +0100 | [diff] [blame] | 217 | ctrl->FRQ = get_FRQ(ctrl); |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 218 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 219 | printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", NS2MHZ_DIV256 / ctrl->tCK); |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 220 | printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", val); |
| 221 | ctrl->CAS = val; |
| 222 | } |
| 223 | |
| 224 | |
| 225 | static void dram_timing(ramctr_timing *ctrl) |
| 226 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 227 | /* |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 228 | * On Sandy Bridge, the maximum supported DDR3 frequency is 1066MHz (DDR3 2133). |
| 229 | * Cap it for faster DIMMs, and align it to the closest JEDEC standard frequency. |
| 230 | */ |
| 231 | /* |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 232 | * On Ivy Bridge, the maximum supported DDR3 frequency is 1400MHz (DDR3 2800). |
| 233 | * Cap it at 1200MHz (DDR3 2400), and align it to the closest JEDEC standard frequency. |
| 234 | */ |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 235 | if (ctrl->tCK == TCK_1200MHZ) { |
Patrick Rudolph | cb7d6a1 | 2016-11-25 15:40:49 +0100 | [diff] [blame] | 236 | ctrl->edge_offset[0] = 18; //XXX: guessed |
| 237 | ctrl->edge_offset[1] = 8; |
| 238 | ctrl->edge_offset[2] = 8; |
| 239 | ctrl->timC_offset[0] = 20; //XXX: guessed |
| 240 | ctrl->timC_offset[1] = 8; |
| 241 | ctrl->timC_offset[2] = 8; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 242 | ctrl->pi_coding_threshold = 10; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 243 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 244 | } else if (ctrl->tCK == TCK_1100MHZ) { |
Patrick Rudolph | cb7d6a1 | 2016-11-25 15:40:49 +0100 | [diff] [blame] | 245 | ctrl->edge_offset[0] = 17; //XXX: guessed |
| 246 | ctrl->edge_offset[1] = 7; |
| 247 | ctrl->edge_offset[2] = 7; |
| 248 | ctrl->timC_offset[0] = 19; //XXX: guessed |
| 249 | ctrl->timC_offset[1] = 7; |
| 250 | ctrl->timC_offset[2] = 7; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 251 | ctrl->pi_coding_threshold = 13; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 252 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 253 | } else if (ctrl->tCK == TCK_1066MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 254 | ctrl->edge_offset[0] = 16; |
| 255 | ctrl->edge_offset[1] = 7; |
| 256 | ctrl->edge_offset[2] = 7; |
| 257 | ctrl->timC_offset[0] = 18; |
| 258 | ctrl->timC_offset[1] = 7; |
| 259 | ctrl->timC_offset[2] = 7; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 260 | ctrl->pi_coding_threshold = 13; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 261 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 262 | } else if (ctrl->tCK == TCK_1000MHZ) { |
Patrick Rudolph | cb7d6a1 | 2016-11-25 15:40:49 +0100 | [diff] [blame] | 263 | ctrl->edge_offset[0] = 15; //XXX: guessed |
| 264 | ctrl->edge_offset[1] = 6; |
| 265 | ctrl->edge_offset[2] = 6; |
| 266 | ctrl->timC_offset[0] = 17; //XXX: guessed |
| 267 | ctrl->timC_offset[1] = 6; |
| 268 | ctrl->timC_offset[2] = 6; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 269 | ctrl->pi_coding_threshold = 13; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 270 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 271 | } else if (ctrl->tCK == TCK_933MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 272 | ctrl->edge_offset[0] = 14; |
| 273 | ctrl->edge_offset[1] = 6; |
| 274 | ctrl->edge_offset[2] = 6; |
| 275 | ctrl->timC_offset[0] = 15; |
| 276 | ctrl->timC_offset[1] = 6; |
| 277 | ctrl->timC_offset[2] = 6; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 278 | ctrl->pi_coding_threshold = 15; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 279 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 280 | } else if (ctrl->tCK == TCK_900MHZ) { |
Patrick Rudolph | cb7d6a1 | 2016-11-25 15:40:49 +0100 | [diff] [blame] | 281 | ctrl->edge_offset[0] = 14; //XXX: guessed |
| 282 | ctrl->edge_offset[1] = 6; |
| 283 | ctrl->edge_offset[2] = 6; |
| 284 | ctrl->timC_offset[0] = 15; //XXX: guessed |
| 285 | ctrl->timC_offset[1] = 6; |
| 286 | ctrl->timC_offset[2] = 6; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 287 | ctrl->pi_coding_threshold = 12; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 288 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 289 | } else if (ctrl->tCK == TCK_800MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 290 | ctrl->edge_offset[0] = 13; |
| 291 | ctrl->edge_offset[1] = 5; |
| 292 | ctrl->edge_offset[2] = 5; |
| 293 | ctrl->timC_offset[0] = 14; |
| 294 | ctrl->timC_offset[1] = 5; |
| 295 | ctrl->timC_offset[2] = 5; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 296 | ctrl->pi_coding_threshold = 15; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 297 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 298 | } else if (ctrl->tCK == TCK_700MHZ) { |
Patrick Rudolph | cb7d6a1 | 2016-11-25 15:40:49 +0100 | [diff] [blame] | 299 | ctrl->edge_offset[0] = 13; //XXX: guessed |
| 300 | ctrl->edge_offset[1] = 5; |
| 301 | ctrl->edge_offset[2] = 5; |
| 302 | ctrl->timC_offset[0] = 14; //XXX: guessed |
| 303 | ctrl->timC_offset[1] = 5; |
| 304 | ctrl->timC_offset[2] = 5; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 305 | ctrl->pi_coding_threshold = 16; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 306 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 307 | } else if (ctrl->tCK == TCK_666MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 308 | ctrl->edge_offset[0] = 10; |
| 309 | ctrl->edge_offset[1] = 4; |
| 310 | ctrl->edge_offset[2] = 4; |
| 311 | ctrl->timC_offset[0] = 11; |
| 312 | ctrl->timC_offset[1] = 4; |
| 313 | ctrl->timC_offset[2] = 4; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 314 | ctrl->pi_coding_threshold = 16; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 315 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 316 | } else if (ctrl->tCK == TCK_533MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 317 | ctrl->edge_offset[0] = 8; |
| 318 | ctrl->edge_offset[1] = 3; |
| 319 | ctrl->edge_offset[2] = 3; |
| 320 | ctrl->timC_offset[0] = 9; |
| 321 | ctrl->timC_offset[1] = 3; |
| 322 | ctrl->timC_offset[2] = 3; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 323 | ctrl->pi_coding_threshold = 17; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 324 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 325 | } else { /* TCK_400MHZ */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 326 | ctrl->edge_offset[0] = 6; |
| 327 | ctrl->edge_offset[1] = 2; |
| 328 | ctrl->edge_offset[2] = 2; |
| 329 | ctrl->timC_offset[0] = 6; |
| 330 | ctrl->timC_offset[1] = 2; |
| 331 | ctrl->timC_offset[2] = 2; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 332 | ctrl->pi_coding_threshold = 17; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 333 | } |
| 334 | |
| 335 | /* Initial phase between CLK/CMD pins */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 336 | ctrl->pi_code_offset = (256000 / ctrl->tCK) / 66; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 337 | |
| 338 | /* DLL_CONFIG_MDLL_W_TIMER */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 339 | ctrl->mdll_wake_delay = (128000 / ctrl->tCK) + 3; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 340 | |
Dan Elkouby | dabebc3 | 2018-04-13 18:47:10 +0300 | [diff] [blame] | 341 | if (ctrl->tCWL) |
| 342 | ctrl->CWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK); |
| 343 | else |
| 344 | ctrl->CWL = get_CWL(ctrl->tCK); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 345 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 346 | printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL); |
| 347 | |
| 348 | /* Find tRCD */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 349 | ctrl->tRCD = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 350 | printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD); |
| 351 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 352 | ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 353 | printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP); |
| 354 | |
| 355 | /* Find tRAS */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 356 | ctrl->tRAS = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 357 | printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS); |
| 358 | |
| 359 | /* Find tWR */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 360 | ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 361 | printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR); |
| 362 | |
| 363 | /* Find tFAW */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 364 | ctrl->tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 365 | printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW); |
| 366 | |
| 367 | /* Find tRRD */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 368 | ctrl->tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 369 | printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD); |
| 370 | |
| 371 | /* Find tRTP */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 372 | ctrl->tRTP = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 373 | printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP); |
| 374 | |
| 375 | /* Find tWTR */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 376 | ctrl->tWTR = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 377 | printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR); |
| 378 | |
| 379 | /* Refresh-to-Active or Refresh-to-Refresh (tRFC) */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 380 | ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 381 | printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); |
| 382 | |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 383 | ctrl->tREFI = get_REFI(ctrl->FRQ, ctrl->base_freq); |
| 384 | ctrl->tMOD = get_MOD(ctrl->FRQ, ctrl->base_freq); |
| 385 | ctrl->tXSOffset = get_XSOffset(ctrl->FRQ, ctrl->base_freq); |
| 386 | ctrl->tWLO = get_WLO(ctrl->FRQ, ctrl->base_freq); |
| 387 | ctrl->tCKE = get_CKE(ctrl->FRQ, ctrl->base_freq); |
| 388 | ctrl->tXPDLL = get_XPDLL(ctrl->FRQ, ctrl->base_freq); |
| 389 | ctrl->tXP = get_XP(ctrl->FRQ, ctrl->base_freq); |
| 390 | ctrl->tAONPD = get_AONPD(ctrl->FRQ, ctrl->base_freq); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 391 | } |
| 392 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 393 | static void dram_freq(ramctr_timing *ctrl) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 394 | { |
| 395 | if (ctrl->tCK > TCK_400MHZ) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 396 | printk(BIOS_ERR, |
| 397 | "DRAM frequency is under lowest supported frequency (400 MHz). " |
| 398 | "Increasing to 400 MHz as last resort"); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 399 | ctrl->tCK = TCK_400MHZ; |
| 400 | } |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 401 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 402 | while (1) { |
| 403 | u8 val2; |
| 404 | u32 reg1 = 0; |
| 405 | |
| 406 | /* Step 1 - Set target PCU frequency */ |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 407 | find_cas_tck(ctrl); |
Patrick Rudolph | cab4d3d | 2016-11-24 19:40:23 +0100 | [diff] [blame] | 408 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 409 | /* |
| 410 | * The PLL will never lock if the required frequency is already set. |
| 411 | * Exit early to prevent a system hang. |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 412 | */ |
| 413 | reg1 = MCHBAR32(MC_BIOS_DATA); |
| 414 | val2 = (u8) reg1; |
| 415 | if (val2) |
| 416 | return; |
| 417 | |
| 418 | /* Step 2 - Select frequency in the MCU */ |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 419 | reg1 = ctrl->FRQ; |
Patrick Rudolph | cab4d3d | 2016-11-24 19:40:23 +0100 | [diff] [blame] | 420 | if (ctrl->base_freq == 100) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 421 | reg1 |= 0x100; /* Enable 100Mhz REF clock */ |
| 422 | |
| 423 | reg1 |= 0x80000000; /* set running bit */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 424 | MCHBAR32(MC_BIOS_REQ) = reg1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 425 | int i = 0; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 426 | printk(BIOS_DEBUG, "PLL busy... "); |
| 427 | while (reg1 & 0x80000000) { |
| 428 | udelay(10); |
| 429 | i++; |
| 430 | reg1 = MCHBAR32(MC_BIOS_REQ); |
| 431 | } |
| 432 | printk(BIOS_DEBUG, "done in %d us\n", i * 10); |
| 433 | |
| 434 | /* Step 3 - Verify lock frequency */ |
| 435 | reg1 = MCHBAR32(MC_BIOS_DATA); |
| 436 | val2 = (u8) reg1; |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 437 | if (val2 >= ctrl->FRQ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 438 | printk(BIOS_DEBUG, "MCU frequency is set at : %d MHz\n", |
| 439 | (1000 << 8) / ctrl->tCK); |
| 440 | return; |
| 441 | } |
| 442 | printk(BIOS_DEBUG, "PLL didn't lock. Retrying at lower frequency\n"); |
| 443 | ctrl->tCK++; |
| 444 | } |
| 445 | } |
| 446 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 447 | static void dram_ioregs(ramctr_timing *ctrl) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 448 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 449 | u32 reg; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 450 | |
| 451 | int channel; |
| 452 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 453 | /* IO clock */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 454 | FOR_ALL_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 455 | MCHBAR32(GDCRCLKRANKSUSED_ch(channel)) = ctrl->rankmap[channel]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 456 | } |
| 457 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 458 | /* IO command */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 459 | FOR_ALL_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 460 | MCHBAR32(GDCRCTLRANKSUSED_ch(channel)) = ctrl->rankmap[channel]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 461 | } |
| 462 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 463 | /* IO control */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 464 | FOR_ALL_POPULATED_CHANNELS { |
| 465 | program_timings(ctrl, channel); |
| 466 | } |
| 467 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 468 | /* Perform RCOMP */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 469 | printram("RCOMP..."); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 470 | while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) |
| 471 | ; |
| 472 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 473 | printram("done\n"); |
| 474 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 475 | /* Set COMP2 */ |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 476 | MCHBAR32(CRCOMPOFST2) = get_COMP2(ctrl->FRQ, ctrl->base_freq); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 477 | printram("COMP2 done\n"); |
| 478 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 479 | /* Set COMP1 */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 480 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 481 | reg = MCHBAR32(CRCOMPOFST1_ch(channel)); |
| 482 | reg = (reg & ~0x00000e00) | (1 << 9); /* ODT */ |
| 483 | reg = (reg & ~0x00e00000) | (1 << 21); /* clk drive up */ |
| 484 | reg = (reg & ~0x38000000) | (1 << 27); /* ctl drive up */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 485 | MCHBAR32(CRCOMPOFST1_ch(channel)) = reg; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 486 | } |
| 487 | printram("COMP1 done\n"); |
| 488 | |
| 489 | printram("FORCE RCOMP and wait 20us..."); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 490 | MCHBAR32(M_COMP) |= (1 << 8); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 491 | udelay(20); |
| 492 | printram("done\n"); |
| 493 | } |
| 494 | |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 495 | int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_uma_size) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 496 | { |
| 497 | int err; |
| 498 | |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 499 | printk(BIOS_DEBUG, "Starting %s Bridge RAM training (%s).\n", |
| 500 | IS_SANDY_CPU(ctrl->cpu) ? "Sandy" : "Ivy", |
| 501 | fast_boot ? "fast boot" : "full initialization"); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 502 | |
| 503 | if (!fast_boot) { |
| 504 | /* Find fastest common supported parameters */ |
| 505 | dram_find_common_params(ctrl); |
| 506 | |
| 507 | dram_dimm_mapping(ctrl); |
| 508 | } |
| 509 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 510 | /* Set MC frequency */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 511 | dram_freq(ctrl); |
| 512 | |
| 513 | if (!fast_boot) { |
| 514 | /* Calculate timings */ |
| 515 | dram_timing(ctrl); |
| 516 | } |
| 517 | |
| 518 | /* Set version register */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 519 | MCHBAR32(MRC_REVISION) = 0xc04eb002; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 520 | |
| 521 | /* Enable crossover */ |
| 522 | dram_xover(ctrl); |
| 523 | |
| 524 | /* Set timing and refresh registers */ |
| 525 | dram_timing_regs(ctrl); |
| 526 | |
| 527 | /* Power mode preset */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 528 | MCHBAR32(PM_THML_STAT) = 0x5500; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 529 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 530 | /* Set scheduler chicken bits */ |
| 531 | MCHBAR32(SCHED_CBIT) = 0x10100005; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 532 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 533 | /* Set up watermarks and starvation counter */ |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 534 | set_wmm_behavior(ctrl->cpu); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 535 | |
| 536 | /* Clear IO reset bit */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 537 | MCHBAR32(MC_INIT_STATE_G) &= ~(1 << 5); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 538 | |
| 539 | /* Set MAD-DIMM registers */ |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame^] | 540 | dram_dimm_set_mapping(ctrl, 1); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 541 | printk(BIOS_DEBUG, "Done dimm mapping\n"); |
| 542 | |
| 543 | /* Zone config */ |
| 544 | dram_zones(ctrl, 1); |
| 545 | |
| 546 | /* Set memory map */ |
| 547 | dram_memorymap(ctrl, me_uma_size); |
| 548 | printk(BIOS_DEBUG, "Done memory map\n"); |
| 549 | |
| 550 | /* Set IO registers */ |
| 551 | dram_ioregs(ctrl); |
| 552 | printk(BIOS_DEBUG, "Done io registers\n"); |
| 553 | |
| 554 | udelay(1); |
| 555 | |
| 556 | if (fast_boot) { |
| 557 | restore_timings(ctrl); |
| 558 | } else { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 559 | /* Do JEDEC DDR3 reset sequence */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 560 | dram_jedecreset(ctrl); |
| 561 | printk(BIOS_DEBUG, "Done jedec reset\n"); |
| 562 | |
| 563 | /* MRS commands */ |
| 564 | dram_mrscommands(ctrl); |
| 565 | printk(BIOS_DEBUG, "Done MRS commands\n"); |
| 566 | |
| 567 | /* Prepare for memory training */ |
| 568 | prepare_training(ctrl); |
| 569 | |
| 570 | err = read_training(ctrl); |
| 571 | if (err) |
| 572 | return err; |
| 573 | |
| 574 | err = write_training(ctrl); |
| 575 | if (err) |
| 576 | return err; |
| 577 | |
| 578 | printram("CP5a\n"); |
| 579 | |
| 580 | err = discover_edges(ctrl); |
| 581 | if (err) |
| 582 | return err; |
| 583 | |
| 584 | printram("CP5b\n"); |
| 585 | |
| 586 | err = command_training(ctrl); |
| 587 | if (err) |
| 588 | return err; |
| 589 | |
| 590 | printram("CP5c\n"); |
| 591 | |
| 592 | err = discover_edges_write(ctrl); |
| 593 | if (err) |
| 594 | return err; |
| 595 | |
| 596 | err = discover_timC_write(ctrl); |
| 597 | if (err) |
| 598 | return err; |
| 599 | |
| 600 | normalize_training(ctrl); |
| 601 | } |
| 602 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 603 | set_read_write_timings(ctrl); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 604 | |
| 605 | write_controller_mr(ctrl); |
| 606 | |
Angel Pons | efbed26 | 2020-03-23 23:18:03 +0100 | [diff] [blame] | 607 | if (!s3resume) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 608 | err = channel_test(ctrl); |
| 609 | if (err) |
| 610 | return err; |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame^] | 611 | |
| 612 | if (ctrl->ecc_enabled) |
| 613 | channel_scrub(ctrl); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 614 | } |
| 615 | |
Patrick Rudolph | dd66287 | 2017-10-28 18:20:11 +0200 | [diff] [blame^] | 616 | /* Set MAD-DIMM registers */ |
| 617 | dram_dimm_set_mapping(ctrl, 0); |
| 618 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 619 | return 0; |
| 620 | } |