Angel Pons | 6e5aabd | 2020-03-23 23:44:42 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | /* This file is part of the coreboot project. */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 3 | |
Angel Pons | a6c8b4b | 2020-03-23 22:38:08 +0100 | [diff] [blame] | 4 | #include <commonlib/clamp.h> |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 5 | #include <console/console.h> |
| 6 | #include <console/usb.h> |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 7 | #include <delay.h> |
Patrick Rudolph | cab4d3d | 2016-11-24 19:40:23 +0100 | [diff] [blame] | 8 | #include <device/pci_ops.h> |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 9 | #include "raminit_native.h" |
| 10 | #include "raminit_common.h" |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 11 | #include "raminit_tables.h" |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 12 | |
Angel Pons | a6c8b4b | 2020-03-23 22:38:08 +0100 | [diff] [blame] | 13 | #define IVB_MIN_DCLK_133_MULT 3 |
| 14 | #define IVB_MAX_DCLK_133_MULT 10 |
| 15 | #define IVB_MIN_DCLK_100_MULT 7 |
| 16 | #define IVB_MAX_DCLK_100_MULT 12 |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 17 | |
Angel Pons | a6c8b4b | 2020-03-23 22:38:08 +0100 | [diff] [blame] | 18 | /* Frequency multiplier */ |
| 19 | static u32 get_FRQ(const ramctr_timing *ctrl) |
| 20 | { |
| 21 | const u32 FRQ = 256000 / (ctrl->tCK * ctrl->base_freq); |
| 22 | |
| 23 | if (IS_IVY_CPU(ctrl->cpu)) { |
| 24 | if (ctrl->base_freq == 100) |
| 25 | return clamp_u32(IVB_MIN_DCLK_100_MULT, FRQ, IVB_MAX_DCLK_100_MULT); |
| 26 | |
| 27 | if (ctrl->base_freq == 133) |
| 28 | return clamp_u32(IVB_MIN_DCLK_133_MULT, FRQ, IVB_MAX_DCLK_133_MULT); |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 29 | } |
| 30 | |
Angel Pons | a6c8b4b | 2020-03-23 22:38:08 +0100 | [diff] [blame] | 31 | die("Unsupported CPU or base frequency."); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 32 | } |
| 33 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 34 | /* Get REFI based on frequency index, tREFI = 7.8usec */ |
| 35 | static u32 get_REFI(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 36 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 37 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 38 | return frq_refi_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 39 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 40 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 41 | return frq_refi_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 42 | } |
| 43 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 44 | /* Get XSOffset based on frequency index, tXS-Offset: tXS = tRFC + 10ns */ |
| 45 | static u8 get_XSOffset(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 46 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 47 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 48 | return frq_xs_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 49 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 50 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 51 | return frq_xs_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 52 | } |
| 53 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 54 | /* Get MOD based on frequency index */ |
| 55 | static u8 get_MOD(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 56 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 57 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 58 | return frq_mod_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 59 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 60 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 61 | return frq_mod_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 62 | } |
| 63 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 64 | /* Get Write Leveling Output delay based on frequency index */ |
| 65 | static u8 get_WLO(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 66 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 67 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 68 | return frq_wlo_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 69 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 70 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 71 | return frq_wlo_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 72 | } |
| 73 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 74 | /* Get CKE based on frequency index */ |
| 75 | static u8 get_CKE(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 76 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 77 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 78 | return frq_cke_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 79 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 80 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 81 | return frq_cke_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 82 | } |
| 83 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 84 | /* Get XPDLL based on frequency index */ |
| 85 | static u8 get_XPDLL(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 86 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 87 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 88 | return frq_xpdll_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 89 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 90 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 91 | return frq_xpdll_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 92 | } |
| 93 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 94 | /* Get XP based on frequency index */ |
| 95 | static u8 get_XP(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 96 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 97 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 98 | return frq_xp_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 99 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 100 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 101 | return frq_xp_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 102 | } |
| 103 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 104 | /* Get AONPD based on frequency index */ |
| 105 | static u8 get_AONPD(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 106 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 107 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 108 | return frq_aonpd_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 109 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 110 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 111 | return frq_aonpd_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 112 | } |
| 113 | |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 114 | /* Get COMP2 based on frequency index */ |
| 115 | static u32 get_COMP2(u32 FRQ, u8 base_freq) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 116 | { |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 117 | if (base_freq == 100) |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 118 | return frq_comp2_map[1][FRQ - 7]; |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 119 | |
Angel Pons | 825332d | 2020-03-21 19:31:53 +0100 | [diff] [blame] | 120 | else |
Angel Pons | df09bdb | 2020-03-21 16:40:41 +0100 | [diff] [blame] | 121 | return frq_comp2_map[0][FRQ - 3]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 122 | } |
| 123 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 124 | static void ivb_normalize_tclk(ramctr_timing *ctrl, bool ref_100mhz_support) |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 125 | { |
| 126 | if (ctrl->tCK <= TCK_1200MHZ) { |
| 127 | ctrl->tCK = TCK_1200MHZ; |
| 128 | ctrl->base_freq = 100; |
| 129 | } else if (ctrl->tCK <= TCK_1100MHZ) { |
| 130 | ctrl->tCK = TCK_1100MHZ; |
| 131 | ctrl->base_freq = 100; |
| 132 | } else if (ctrl->tCK <= TCK_1066MHZ) { |
| 133 | ctrl->tCK = TCK_1066MHZ; |
| 134 | ctrl->base_freq = 133; |
| 135 | } else if (ctrl->tCK <= TCK_1000MHZ) { |
| 136 | ctrl->tCK = TCK_1000MHZ; |
| 137 | ctrl->base_freq = 100; |
| 138 | } else if (ctrl->tCK <= TCK_933MHZ) { |
| 139 | ctrl->tCK = TCK_933MHZ; |
| 140 | ctrl->base_freq = 133; |
| 141 | } else if (ctrl->tCK <= TCK_900MHZ) { |
| 142 | ctrl->tCK = TCK_900MHZ; |
| 143 | ctrl->base_freq = 100; |
| 144 | } else if (ctrl->tCK <= TCK_800MHZ) { |
| 145 | ctrl->tCK = TCK_800MHZ; |
| 146 | ctrl->base_freq = 133; |
| 147 | } else if (ctrl->tCK <= TCK_700MHZ) { |
| 148 | ctrl->tCK = TCK_700MHZ; |
| 149 | ctrl->base_freq = 100; |
| 150 | } else if (ctrl->tCK <= TCK_666MHZ) { |
| 151 | ctrl->tCK = TCK_666MHZ; |
| 152 | ctrl->base_freq = 133; |
| 153 | } else if (ctrl->tCK <= TCK_533MHZ) { |
| 154 | ctrl->tCK = TCK_533MHZ; |
| 155 | ctrl->base_freq = 133; |
| 156 | } else if (ctrl->tCK <= TCK_400MHZ) { |
| 157 | ctrl->tCK = TCK_400MHZ; |
| 158 | ctrl->base_freq = 133; |
| 159 | } else { |
| 160 | ctrl->tCK = 0; |
| 161 | return; |
| 162 | } |
| 163 | |
| 164 | if (!ref_100mhz_support && ctrl->base_freq == 100) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 165 | /* Skip unsupported frequency */ |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 166 | ctrl->tCK++; |
| 167 | ivb_normalize_tclk(ctrl, ref_100mhz_support); |
| 168 | } |
| 169 | } |
| 170 | |
| 171 | static void find_cas_tck(ramctr_timing *ctrl) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 172 | { |
| 173 | u8 val; |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 174 | u32 reg32; |
| 175 | u8 ref_100mhz_support; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 176 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 177 | /* 100 MHz reference clock supported */ |
| 178 | reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B); |
Angel Pons | 29f391ec | 2020-03-23 22:51:05 +0100 | [diff] [blame^] | 179 | ref_100mhz_support = (reg32 >> 21) & 0x7; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 180 | printk(BIOS_DEBUG, "100MHz reference clock support: %s\n", ref_100mhz_support ? "yes" |
| 181 | : "no"); |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 182 | |
Angel Pons | 29f391ec | 2020-03-23 22:51:05 +0100 | [diff] [blame^] | 183 | printk(BIOS_DEBUG, "PLL_REF100_CFG value: 0x%x\n", ref_100mhz_support); |
| 184 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 185 | /* Find CAS latency */ |
| 186 | while (1) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 187 | /* |
| 188 | * Normalising tCK before computing clock could potentially |
| 189 | * result in a lower selected CAS, which is desired. |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 190 | */ |
| 191 | ivb_normalize_tclk(ctrl, ref_100mhz_support); |
| 192 | if (!(ctrl->tCK)) |
| 193 | die("Couldn't find compatible clock / CAS settings\n"); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 194 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 195 | val = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK); |
| 196 | printk(BIOS_DEBUG, "Trying CAS %u, tCK %u.\n", val, ctrl->tCK); |
| 197 | for (; val <= MAX_CAS; val++) |
| 198 | if ((ctrl->cas_supported >> (val - MIN_CAS)) & 1) |
| 199 | break; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 200 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 201 | if (val == (MAX_CAS + 1)) { |
| 202 | ctrl->tCK++; |
| 203 | continue; |
| 204 | } else { |
| 205 | printk(BIOS_DEBUG, "Found compatible clock, CAS pair.\n"); |
| 206 | break; |
| 207 | } |
| 208 | } |
| 209 | |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 210 | /* Frequency multiplier */ |
Angel Pons | a6c8b4b | 2020-03-23 22:38:08 +0100 | [diff] [blame] | 211 | ctrl->FRQ = get_FRQ(ctrl); |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 212 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 213 | printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", NS2MHZ_DIV256 / ctrl->tCK); |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 214 | printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", val); |
| 215 | ctrl->CAS = val; |
| 216 | } |
| 217 | |
| 218 | |
| 219 | static void dram_timing(ramctr_timing *ctrl) |
| 220 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 221 | /* |
| 222 | * On Ivy Bridge, the maximum supported DDR3 frequency is 1400MHz (DDR3 2800). |
| 223 | * Cap it at 1200MHz (DDR3 2400), and align it to the closest JEDEC standard frequency. |
| 224 | */ |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 225 | if (ctrl->tCK == TCK_1200MHZ) { |
Patrick Rudolph | cb7d6a1 | 2016-11-25 15:40:49 +0100 | [diff] [blame] | 226 | ctrl->edge_offset[0] = 18; //XXX: guessed |
| 227 | ctrl->edge_offset[1] = 8; |
| 228 | ctrl->edge_offset[2] = 8; |
| 229 | ctrl->timC_offset[0] = 20; //XXX: guessed |
| 230 | ctrl->timC_offset[1] = 8; |
| 231 | ctrl->timC_offset[2] = 8; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 232 | ctrl->pi_coding_threshold = 10; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 233 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 234 | } else if (ctrl->tCK == TCK_1100MHZ) { |
Patrick Rudolph | cb7d6a1 | 2016-11-25 15:40:49 +0100 | [diff] [blame] | 235 | ctrl->edge_offset[0] = 17; //XXX: guessed |
| 236 | ctrl->edge_offset[1] = 7; |
| 237 | ctrl->edge_offset[2] = 7; |
| 238 | ctrl->timC_offset[0] = 19; //XXX: guessed |
| 239 | ctrl->timC_offset[1] = 7; |
| 240 | ctrl->timC_offset[2] = 7; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 241 | ctrl->pi_coding_threshold = 13; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 242 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 243 | } else if (ctrl->tCK == TCK_1066MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 244 | ctrl->edge_offset[0] = 16; |
| 245 | ctrl->edge_offset[1] = 7; |
| 246 | ctrl->edge_offset[2] = 7; |
| 247 | ctrl->timC_offset[0] = 18; |
| 248 | ctrl->timC_offset[1] = 7; |
| 249 | ctrl->timC_offset[2] = 7; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 250 | ctrl->pi_coding_threshold = 13; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 251 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 252 | } else if (ctrl->tCK == TCK_1000MHZ) { |
Patrick Rudolph | cb7d6a1 | 2016-11-25 15:40:49 +0100 | [diff] [blame] | 253 | ctrl->edge_offset[0] = 15; //XXX: guessed |
| 254 | ctrl->edge_offset[1] = 6; |
| 255 | ctrl->edge_offset[2] = 6; |
| 256 | ctrl->timC_offset[0] = 17; //XXX: guessed |
| 257 | ctrl->timC_offset[1] = 6; |
| 258 | ctrl->timC_offset[2] = 6; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 259 | ctrl->pi_coding_threshold = 13; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 260 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 261 | } else if (ctrl->tCK == TCK_933MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 262 | ctrl->edge_offset[0] = 14; |
| 263 | ctrl->edge_offset[1] = 6; |
| 264 | ctrl->edge_offset[2] = 6; |
| 265 | ctrl->timC_offset[0] = 15; |
| 266 | ctrl->timC_offset[1] = 6; |
| 267 | ctrl->timC_offset[2] = 6; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 268 | ctrl->pi_coding_threshold = 15; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 269 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 270 | } else if (ctrl->tCK == TCK_900MHZ) { |
Patrick Rudolph | cb7d6a1 | 2016-11-25 15:40:49 +0100 | [diff] [blame] | 271 | ctrl->edge_offset[0] = 14; //XXX: guessed |
| 272 | ctrl->edge_offset[1] = 6; |
| 273 | ctrl->edge_offset[2] = 6; |
| 274 | ctrl->timC_offset[0] = 15; //XXX: guessed |
| 275 | ctrl->timC_offset[1] = 6; |
| 276 | ctrl->timC_offset[2] = 6; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 277 | ctrl->pi_coding_threshold = 12; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 278 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 279 | } else if (ctrl->tCK == TCK_800MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 280 | ctrl->edge_offset[0] = 13; |
| 281 | ctrl->edge_offset[1] = 5; |
| 282 | ctrl->edge_offset[2] = 5; |
| 283 | ctrl->timC_offset[0] = 14; |
| 284 | ctrl->timC_offset[1] = 5; |
| 285 | ctrl->timC_offset[2] = 5; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 286 | ctrl->pi_coding_threshold = 15; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 287 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 288 | } else if (ctrl->tCK == TCK_700MHZ) { |
Patrick Rudolph | cb7d6a1 | 2016-11-25 15:40:49 +0100 | [diff] [blame] | 289 | ctrl->edge_offset[0] = 13; //XXX: guessed |
| 290 | ctrl->edge_offset[1] = 5; |
| 291 | ctrl->edge_offset[2] = 5; |
| 292 | ctrl->timC_offset[0] = 14; //XXX: guessed |
| 293 | ctrl->timC_offset[1] = 5; |
| 294 | ctrl->timC_offset[2] = 5; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 295 | ctrl->pi_coding_threshold = 16; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 296 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 297 | } else if (ctrl->tCK == TCK_666MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 298 | ctrl->edge_offset[0] = 10; |
| 299 | ctrl->edge_offset[1] = 4; |
| 300 | ctrl->edge_offset[2] = 4; |
| 301 | ctrl->timC_offset[0] = 11; |
| 302 | ctrl->timC_offset[1] = 4; |
| 303 | ctrl->timC_offset[2] = 4; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 304 | ctrl->pi_coding_threshold = 16; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 305 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 306 | } else if (ctrl->tCK == TCK_533MHZ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 307 | ctrl->edge_offset[0] = 8; |
| 308 | ctrl->edge_offset[1] = 3; |
| 309 | ctrl->edge_offset[2] = 3; |
| 310 | ctrl->timC_offset[0] = 9; |
| 311 | ctrl->timC_offset[1] = 3; |
| 312 | ctrl->timC_offset[2] = 3; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 313 | ctrl->pi_coding_threshold = 17; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 314 | |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 315 | } else { /* TCK_400MHZ */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 316 | ctrl->edge_offset[0] = 6; |
| 317 | ctrl->edge_offset[1] = 2; |
| 318 | ctrl->edge_offset[2] = 2; |
| 319 | ctrl->timC_offset[0] = 6; |
| 320 | ctrl->timC_offset[1] = 2; |
| 321 | ctrl->timC_offset[2] = 2; |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 322 | ctrl->pi_coding_threshold = 17; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 323 | } |
| 324 | |
| 325 | /* Initial phase between CLK/CMD pins */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 326 | ctrl->pi_code_offset = (256000 / ctrl->tCK) / 66; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 327 | |
| 328 | /* DLL_CONFIG_MDLL_W_TIMER */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 329 | ctrl->mdll_wake_delay = (128000 / ctrl->tCK) + 3; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 330 | |
Dan Elkouby | dabebc3 | 2018-04-13 18:47:10 +0300 | [diff] [blame] | 331 | if (ctrl->tCWL) |
| 332 | ctrl->CWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK); |
| 333 | else |
| 334 | ctrl->CWL = get_CWL(ctrl->tCK); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 335 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 336 | printk(BIOS_DEBUG, "Selected CWL latency : %uT\n", ctrl->CWL); |
| 337 | |
| 338 | /* Find tRCD */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 339 | ctrl->tRCD = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 340 | printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD); |
| 341 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 342 | ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 343 | printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP); |
| 344 | |
| 345 | /* Find tRAS */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 346 | ctrl->tRAS = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 347 | printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS); |
| 348 | |
| 349 | /* Find tWR */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 350 | ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 351 | printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR); |
| 352 | |
| 353 | /* Find tFAW */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 354 | ctrl->tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 355 | printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW); |
| 356 | |
| 357 | /* Find tRRD */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 358 | ctrl->tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 359 | printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD); |
| 360 | |
| 361 | /* Find tRTP */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 362 | ctrl->tRTP = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 363 | printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP); |
| 364 | |
| 365 | /* Find tWTR */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 366 | ctrl->tWTR = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 367 | printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR); |
| 368 | |
| 369 | /* Refresh-to-Active or Refresh-to-Refresh (tRFC) */ |
Arthur Heymans | 50db9c9 | 2017-03-23 18:53:38 +0100 | [diff] [blame] | 370 | ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 371 | printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC); |
| 372 | |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 373 | ctrl->tREFI = get_REFI(ctrl->FRQ, ctrl->base_freq); |
| 374 | ctrl->tMOD = get_MOD(ctrl->FRQ, ctrl->base_freq); |
| 375 | ctrl->tXSOffset = get_XSOffset(ctrl->FRQ, ctrl->base_freq); |
| 376 | ctrl->tWLO = get_WLO(ctrl->FRQ, ctrl->base_freq); |
| 377 | ctrl->tCKE = get_CKE(ctrl->FRQ, ctrl->base_freq); |
| 378 | ctrl->tXPDLL = get_XPDLL(ctrl->FRQ, ctrl->base_freq); |
| 379 | ctrl->tXP = get_XP(ctrl->FRQ, ctrl->base_freq); |
| 380 | ctrl->tAONPD = get_AONPD(ctrl->FRQ, ctrl->base_freq); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 381 | } |
| 382 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 383 | static void dram_freq(ramctr_timing *ctrl) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 384 | { |
| 385 | if (ctrl->tCK > TCK_400MHZ) { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 386 | printk(BIOS_ERR, |
| 387 | "DRAM frequency is under lowest supported frequency (400 MHz). " |
| 388 | "Increasing to 400 MHz as last resort"); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 389 | ctrl->tCK = TCK_400MHZ; |
| 390 | } |
Patrick Rudolph | 77eaba3 | 2016-11-11 18:55:54 +0100 | [diff] [blame] | 391 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 392 | while (1) { |
| 393 | u8 val2; |
| 394 | u32 reg1 = 0; |
| 395 | |
| 396 | /* Step 1 - Set target PCU frequency */ |
Arthur Heymans | 9ed74b5 | 2017-05-16 19:56:49 +0200 | [diff] [blame] | 397 | find_cas_tck(ctrl); |
Patrick Rudolph | cab4d3d | 2016-11-24 19:40:23 +0100 | [diff] [blame] | 398 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 399 | /* |
| 400 | * The PLL will never lock if the required frequency is already set. |
| 401 | * Exit early to prevent a system hang. |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 402 | */ |
| 403 | reg1 = MCHBAR32(MC_BIOS_DATA); |
| 404 | val2 = (u8) reg1; |
| 405 | if (val2) |
| 406 | return; |
| 407 | |
| 408 | /* Step 2 - Select frequency in the MCU */ |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 409 | reg1 = ctrl->FRQ; |
Patrick Rudolph | cab4d3d | 2016-11-24 19:40:23 +0100 | [diff] [blame] | 410 | if (ctrl->base_freq == 100) |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 411 | reg1 |= 0x100; /* Enable 100Mhz REF clock */ |
| 412 | |
| 413 | reg1 |= 0x80000000; /* set running bit */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 414 | MCHBAR32(MC_BIOS_REQ) = reg1; |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 415 | int i = 0; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 416 | printk(BIOS_DEBUG, "PLL busy... "); |
| 417 | while (reg1 & 0x80000000) { |
| 418 | udelay(10); |
| 419 | i++; |
| 420 | reg1 = MCHBAR32(MC_BIOS_REQ); |
| 421 | } |
| 422 | printk(BIOS_DEBUG, "done in %d us\n", i * 10); |
| 423 | |
| 424 | /* Step 3 - Verify lock frequency */ |
| 425 | reg1 = MCHBAR32(MC_BIOS_DATA); |
| 426 | val2 = (u8) reg1; |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 427 | if (val2 >= ctrl->FRQ) { |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 428 | printk(BIOS_DEBUG, "MCU frequency is set at : %d MHz\n", |
| 429 | (1000 << 8) / ctrl->tCK); |
| 430 | return; |
| 431 | } |
| 432 | printk(BIOS_DEBUG, "PLL didn't lock. Retrying at lower frequency\n"); |
| 433 | ctrl->tCK++; |
| 434 | } |
| 435 | } |
| 436 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 437 | static void dram_ioregs(ramctr_timing *ctrl) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 438 | { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 439 | u32 reg; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 440 | |
| 441 | int channel; |
| 442 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 443 | /* IO clock */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 444 | FOR_ALL_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 445 | MCHBAR32(GDCRCLKRANKSUSED_ch(channel)) = ctrl->rankmap[channel]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 446 | } |
| 447 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 448 | /* IO command */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 449 | FOR_ALL_CHANNELS { |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 450 | MCHBAR32(GDCRCTLRANKSUSED_ch(channel)) = ctrl->rankmap[channel]; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 451 | } |
| 452 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 453 | /* IO control */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 454 | FOR_ALL_POPULATED_CHANNELS { |
| 455 | program_timings(ctrl, channel); |
| 456 | } |
| 457 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 458 | /* Perform RCOMP */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 459 | printram("RCOMP..."); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 460 | while (!(MCHBAR32(RCOMP_TIMER) & (1 << 16))) |
| 461 | ; |
| 462 | |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 463 | printram("done\n"); |
| 464 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 465 | /* Set COMP2 */ |
Angel Pons | 48409b8 | 2020-03-23 22:19:29 +0100 | [diff] [blame] | 466 | MCHBAR32(CRCOMPOFST2) = get_COMP2(ctrl->FRQ, ctrl->base_freq); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 467 | printram("COMP2 done\n"); |
| 468 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 469 | /* Set COMP1 */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 470 | FOR_ALL_POPULATED_CHANNELS { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 471 | reg = MCHBAR32(CRCOMPOFST1_ch(channel)); |
| 472 | reg = (reg & ~0x00000e00) | (1 << 9); /* ODT */ |
| 473 | reg = (reg & ~0x00e00000) | (1 << 21); /* clk drive up */ |
| 474 | reg = (reg & ~0x38000000) | (1 << 27); /* ctl drive up */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 475 | MCHBAR32(CRCOMPOFST1_ch(channel)) = reg; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 476 | } |
| 477 | printram("COMP1 done\n"); |
| 478 | |
| 479 | printram("FORCE RCOMP and wait 20us..."); |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 480 | MCHBAR32(M_COMP) |= (1 << 8); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 481 | udelay(20); |
| 482 | printram("done\n"); |
| 483 | } |
| 484 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 485 | int try_init_dram_ddr3_ivb(ramctr_timing *ctrl, int fast_boot, int s3_resume, int me_uma_size) |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 486 | { |
| 487 | int err; |
| 488 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 489 | printk(BIOS_DEBUG, "Starting Ivybridge RAM training (%d).\n", fast_boot); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 490 | |
| 491 | if (!fast_boot) { |
| 492 | /* Find fastest common supported parameters */ |
| 493 | dram_find_common_params(ctrl); |
| 494 | |
| 495 | dram_dimm_mapping(ctrl); |
| 496 | } |
| 497 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 498 | /* Set MC frequency */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 499 | dram_freq(ctrl); |
| 500 | |
| 501 | if (!fast_boot) { |
| 502 | /* Calculate timings */ |
| 503 | dram_timing(ctrl); |
| 504 | } |
| 505 | |
| 506 | /* Set version register */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 507 | MCHBAR32(MRC_REVISION) = 0xc04eb002; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 508 | |
| 509 | /* Enable crossover */ |
| 510 | dram_xover(ctrl); |
| 511 | |
| 512 | /* Set timing and refresh registers */ |
| 513 | dram_timing_regs(ctrl); |
| 514 | |
| 515 | /* Power mode preset */ |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 516 | MCHBAR32(PM_THML_STAT) = 0x5500; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 517 | |
Angel Pons | 8852188 | 2020-01-05 20:21:20 +0100 | [diff] [blame] | 518 | /* Set scheduler chicken bits */ |
| 519 | MCHBAR32(SCHED_CBIT) = 0x10100005; |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 520 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 521 | /* Set up watermarks and starvation counter */ |
Angel Pons | 89ae6b8 | 2020-03-21 13:23:32 +0100 | [diff] [blame] | 522 | set_wmm_behavior(ctrl->cpu); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 523 | |
| 524 | /* Clear IO reset bit */ |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 525 | MCHBAR32(MC_INIT_STATE_G) &= ~(1 << 5); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 526 | |
| 527 | /* Set MAD-DIMM registers */ |
| 528 | dram_dimm_set_mapping(ctrl); |
| 529 | printk(BIOS_DEBUG, "Done dimm mapping\n"); |
| 530 | |
| 531 | /* Zone config */ |
| 532 | dram_zones(ctrl, 1); |
| 533 | |
| 534 | /* Set memory map */ |
| 535 | dram_memorymap(ctrl, me_uma_size); |
| 536 | printk(BIOS_DEBUG, "Done memory map\n"); |
| 537 | |
| 538 | /* Set IO registers */ |
| 539 | dram_ioregs(ctrl); |
| 540 | printk(BIOS_DEBUG, "Done io registers\n"); |
| 541 | |
| 542 | udelay(1); |
| 543 | |
| 544 | if (fast_boot) { |
| 545 | restore_timings(ctrl); |
| 546 | } else { |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 547 | /* Do JEDEC DDR3 reset sequence */ |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 548 | dram_jedecreset(ctrl); |
| 549 | printk(BIOS_DEBUG, "Done jedec reset\n"); |
| 550 | |
| 551 | /* MRS commands */ |
| 552 | dram_mrscommands(ctrl); |
| 553 | printk(BIOS_DEBUG, "Done MRS commands\n"); |
| 554 | |
| 555 | /* Prepare for memory training */ |
| 556 | prepare_training(ctrl); |
| 557 | |
| 558 | err = read_training(ctrl); |
| 559 | if (err) |
| 560 | return err; |
| 561 | |
| 562 | err = write_training(ctrl); |
| 563 | if (err) |
| 564 | return err; |
| 565 | |
| 566 | printram("CP5a\n"); |
| 567 | |
| 568 | err = discover_edges(ctrl); |
| 569 | if (err) |
| 570 | return err; |
| 571 | |
| 572 | printram("CP5b\n"); |
| 573 | |
| 574 | err = command_training(ctrl); |
| 575 | if (err) |
| 576 | return err; |
| 577 | |
| 578 | printram("CP5c\n"); |
| 579 | |
| 580 | err = discover_edges_write(ctrl); |
| 581 | if (err) |
| 582 | return err; |
| 583 | |
| 584 | err = discover_timC_write(ctrl); |
| 585 | if (err) |
| 586 | return err; |
| 587 | |
| 588 | normalize_training(ctrl); |
| 589 | } |
| 590 | |
Angel Pons | 7c49cb8 | 2020-03-16 23:17:32 +0100 | [diff] [blame] | 591 | set_read_write_timings(ctrl); |
Patrick Rudolph | 305035c | 2016-11-11 18:38:50 +0100 | [diff] [blame] | 592 | |
| 593 | write_controller_mr(ctrl); |
| 594 | |
| 595 | if (!s3_resume) { |
| 596 | err = channel_test(ctrl); |
| 597 | if (err) |
| 598 | return err; |
| 599 | } |
| 600 | |
| 601 | return 0; |
| 602 | } |