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Angel Pons8a3453f2020-04-02 23:48:19 +02001/* SPDX-License-Identifier: GPL-2.0-only */
efdesign984b508342011-07-13 17:16:13 -07002
efdesign987c0c64e2011-06-20 19:56:06 -07003/******************************************************************************
4 * AMD Generic Encapsulated Software Architecture
5 *
Kyösti Mälkki7076aa52017-09-02 16:20:15 +03006 * $Workfile:: cache_as_ram.S
efdesign987c0c64e2011-06-20 19:56:06 -07007 *
Martin Roth0949e732021-10-01 14:28:22 -06008 * Description: cache_as_ram.S - AGESA Module Entry Point for GCC compiler
efdesign987c0c64e2011-06-20 19:56:06 -07009 *
10 ******************************************************************************
efdesign984b508342011-07-13 17:16:13 -070011 */
12
Michał Żygowski3aa17f72019-11-24 16:32:05 +010013#include <cpu/x86/lapic_def.h>
Kyösti Mälkki7076aa52017-09-02 16:20:15 +030014#include <cpu/x86/post_code.h>
Martin Rothbf3f94d2022-12-31 16:31:01 -070015#include <amdblocks/post_codes.h>
efdesign987c0c64e2011-06-20 19:56:06 -070016
Kyösti Mälkki7522a8f2020-11-20 16:47:38 +020017.section .init
18
efdesign987c0c64e2011-06-20 19:56:06 -070019.code32
Kyösti Mälkki7522a8f2020-11-20 16:47:38 +020020
Michał Żygowski1b12b642019-11-24 16:32:05 +010021.global bootblock_pre_c_entry
efdesign987c0c64e2011-06-20 19:56:06 -070022
Kyösti Mälkki7076aa52017-09-02 16:20:15 +030023_cache_as_ram_setup:
efdesign984b508342011-07-13 17:16:13 -070024
Kyösti Mälkki7522a8f2020-11-20 16:47:38 +020025#include "gcccar.inc"
26
Michał Żygowski1b12b642019-11-24 16:32:05 +010027/*
28 * on entry:
29 * mm0: BIST (ignored)
Kyösti Mälkki6c7441f2020-12-05 08:39:57 +020030 * mm2_mm1: timestamp
Michał Żygowski1b12b642019-11-24 16:32:05 +010031 */
32bootblock_pre_c_entry:
33
Martin Rothbf3f94d2022-12-31 16:31:01 -070034 post_code(POST_BOOTBLOCK_PRE_C_ENTRY)
efdesign984b508342011-07-13 17:16:13 -070035
Elyes HAOUASdea45c12018-12-27 09:14:07 +010036 AMD_ENABLE_STACK
Kyösti Mälkkif6fe2f12016-11-21 11:26:48 +020037
Michał Żygowski3aa17f72019-11-24 16:32:05 +010038 /*
39 * Set up bootblock stack on BSP.
40 * AMD_ENABLE_STACK macro sets up a stack for BSP at BSP_STACK_BASE_ADDR
41 * which is 0x30000 (_car_region_end), but for C bootblock the stack
42 * begins at _ecar_stack (see arch/x86/car.ld)
43 */
44 mov $LAPIC_BASE_MSR, %ecx
45 rdmsr
46 test $LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR, %eax
47 jz ap_entry
48
49 mov $_ecar_stack, %esp
50
Kyösti Mälkki33d0fb82019-11-29 06:38:46 +020051 /* Align the stack and keep aligned for call to bootblock_c_entry() */
52 and $0xfffffff0, %esp
53 sub $8, %esp
Kyösti Mälkki26929bd2016-11-23 20:40:53 +020054
Michał Żygowski1b12b642019-11-24 16:32:05 +010055 movd %mm2, %eax
56 pushl %eax /* tsc[63:32] */
57 movd %mm1, %eax
58 pushl %eax /* tsc[31:0] */
Kyösti Mälkki33d0fb82019-11-29 06:38:46 +020059
Martin Rothbf3f94d2022-12-31 16:31:01 -070060 post_code(POST_BOOTBLOCK_PRE_C_DONE)
Kyösti Mälkki33d0fb82019-11-29 06:38:46 +020061
62 call bootblock_c_entry
Kyösti Mälkki63fac812017-09-02 16:41:43 +030063
Michał Żygowski3aa17f72019-11-24 16:32:05 +010064 /* Never reached. */
Kyösti Mälkki63fac812017-09-02 16:41:43 +030065
Kyösti Mälkkiba22e152016-11-23 06:47:15 +020066stop:
lilacious40cb3fe2023-06-21 23:24:14 +020067 post_code(POSTCODE_DEAD_CODE)
Elyes HAOUASdea45c12018-12-27 09:14:07 +010068 hlt
69 jmp stop
Kyösti Mälkki63fac812017-09-02 16:41:43 +030070
Michał Żygowski3aa17f72019-11-24 16:32:05 +010071ap_entry:
Kyösti Mälkki33d0fb82019-11-29 06:38:46 +020072 /* Align the stack for call to ap_bootblock_c_entry() */
Michał Żygowski3aa17f72019-11-24 16:32:05 +010073 and $0xfffffff0, %esp
Kyösti Mälkki33d0fb82019-11-29 06:38:46 +020074 call ap_bootblock_c_entry
Michał Żygowski3aa17f72019-11-24 16:32:05 +010075
76 /* Never reached. */
77 jmp stop
78
Kyösti Mälkki7076aa52017-09-02 16:20:15 +030079_cache_as_ram_setup_end: