Aamir Bohra | a23e0c9 | 2020-03-25 15:31:12 +0530 | [diff] [blame] | 1 | config SOC_INTEL_JASPERLAKE |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 2 | bool |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 3 | help |
| 4 | Intel Jasperlake support |
| 5 | |
Aamir Bohra | a23e0c9 | 2020-03-25 15:31:12 +0530 | [diff] [blame] | 6 | if SOC_INTEL_JASPERLAKE |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 7 | |
| 8 | config CPU_SPECIFIC_OPTIONS |
| 9 | def_bool y |
| 10 | select ACPI_INTEL_HARDWARE_SLEEP_VALUES |
Angel Pons | a32df26 | 2020-09-25 10:20:11 +0200 | [diff] [blame] | 11 | select ARCH_ALL_STAGES_X86_32 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 12 | select BOOT_DEVICE_SUPPORTS_WRITES |
| 13 | select CACHE_MRC_SETTINGS |
Sumeet R Pawnikar | e8d1bef | 2020-05-08 21:31:44 +0530 | [diff] [blame] | 14 | select CPU_INTEL_COMMON |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 15 | select CPU_INTEL_FIRMWARE_INTERFACE_TABLE |
Michael Niewöhner | fe6070f | 2020-10-04 15:16:04 +0200 | [diff] [blame] | 16 | select CPU_SUPPORTS_PM_TIMER_EMULATION |
Aamir Bohra | 522ba1b | 2020-07-22 14:15:36 +0530 | [diff] [blame] | 17 | select COS_MAPPED_TO_MSB |
Karthikeyan Ramasubramanian | 8021b47 | 2020-06-16 23:54:46 -0600 | [diff] [blame] | 18 | select FSP_COMPRESS_FSP_S_LZ4 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 19 | select FSP_M_XIP |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 20 | select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 21 | select GENERIC_GPIO_LIB |
| 22 | select HAVE_FSP_GOP |
| 23 | select INTEL_DESCRIPTOR_MODE_CAPABLE |
| 24 | select HAVE_SMI_HANDLER |
| 25 | select IDT_IN_EVERY_STAGE |
Shreesh Chhabbi | 87c7ec7 | 2020-12-03 14:07:15 -0800 | [diff] [blame] | 26 | select INTEL_CAR_NEM_ENHANCED |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 27 | select INTEL_GMA_ACPI |
| 28 | select INTEL_GMA_ADD_VBT if RUN_FSP_GOP |
| 29 | select IOAPIC |
Furquan Shaikh | 5f262be | 2021-02-03 23:10:22 -0800 | [diff] [blame^] | 30 | select MP_SERVICES_PPI |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 31 | select MRC_SETTINGS_PROTECT |
| 32 | select PARALLEL_MP |
| 33 | select PARALLEL_MP_AP_WORK |
| 34 | select MICROCODE_BLOB_UNDISCLOSED |
Ronak Kanabar | 8c4ad35 | 2020-07-24 17:46:19 +0530 | [diff] [blame] | 35 | select PLATFORM_USES_FSP2_2 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 36 | select REG_SCRIPT |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 37 | select PMC_GLOBAL_RESET_ENABLE_LOCK |
Subrata Banik | 0359d9d | 2020-09-28 18:43:47 +0530 | [diff] [blame] | 38 | select PMC_LOW_POWER_MODE_PROGRAM |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 39 | select SOC_INTEL_COMMON |
| 40 | select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE |
| 41 | select SOC_INTEL_COMMON_BLOCK |
| 42 | select SOC_INTEL_COMMON_BLOCK_ACPI |
Michael Niewöhner | 8a6c34e | 2021-01-01 21:26:42 +0100 | [diff] [blame] | 43 | select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT |
Subrata Banik | 21974ab | 2020-10-31 21:40:43 +0530 | [diff] [blame] | 44 | select SOC_INTEL_COMMON_BLOCK_CAR |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 45 | select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG |
Furquan Shaikh | 23e8813 | 2020-10-08 23:44:20 -0700 | [diff] [blame] | 46 | select SOC_INTEL_COMMON_BLOCK_CNVI |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 47 | select SOC_INTEL_COMMON_BLOCK_CPU |
| 48 | select SOC_INTEL_COMMON_BLOCK_CPU_MPINIT |
| 49 | select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT |
| 50 | select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 |
| 51 | select SOC_INTEL_COMMON_BLOCK_HDA |
| 52 | select SOC_INTEL_COMMON_BLOCK_SA |
Duncan Laurie | 1e06611 | 2020-04-08 11:35:52 -0700 | [diff] [blame] | 53 | select SOC_INTEL_COMMON_BLOCK_SCS |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 54 | select SOC_INTEL_COMMON_BLOCK_SMM |
Sumeet R Pawnikar | e8d1bef | 2020-05-08 21:31:44 +0530 | [diff] [blame] | 55 | select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 56 | select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP |
Karthikeyan Ramasubramanian | af0d516 | 2020-11-04 17:05:35 -0700 | [diff] [blame] | 57 | select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG |
Subrata Banik | 4ed9f9a | 2020-10-31 22:01:55 +0530 | [diff] [blame] | 58 | select SOC_INTEL_COMMON_FSP_RESET |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 59 | select SOC_INTEL_COMMON_PCH_BASE |
| 60 | select SOC_INTEL_COMMON_RESET |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 61 | select SSE2 |
| 62 | select SUPPORT_CPU_UCODE_IN_CBFS |
| 63 | select TSC_MONOTONIC_TIMER |
| 64 | select UDELAY_TSC |
Ronak Kanabar | a360aad | 2020-08-19 14:40:08 +0530 | [diff] [blame] | 65 | select UDK_202005_BINDING |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 66 | select DISPLAY_FSP_VERSION_INFO |
| 67 | select HECI_DISABLE_USING_SMM |
| 68 | |
| 69 | config DCACHE_RAM_BASE |
| 70 | default 0xfef00000 |
| 71 | |
| 72 | config DCACHE_RAM_SIZE |
| 73 | default 0x80000 |
| 74 | help |
| 75 | The size of the cache-as-ram region required during bootblock |
| 76 | and/or romstage. |
| 77 | |
| 78 | config DCACHE_BSP_STACK_SIZE |
| 79 | hex |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 80 | default 0x30400 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 81 | help |
| 82 | The amount of anticipated stack usage in CAR by bootblock and |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 83 | other stages. In the case of FSP_USES_CB_STACK default value |
| 84 | will be sum of FSP-M stack requirement(192 KiB) and CB romstage |
| 85 | stack requirement(~1KiB). |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 86 | |
| 87 | config FSP_TEMP_RAM_SIZE |
| 88 | hex |
| 89 | default 0x20000 |
| 90 | help |
| 91 | The amount of anticipated heap usage in CAR by FSP. |
| 92 | Refer to Platform FSP integration guide document to know |
| 93 | the exact FSP requirement for Heap setup. |
| 94 | |
| 95 | config IFD_CHIPSET |
| 96 | string |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 97 | default "jsl" |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 98 | |
| 99 | config IED_REGION_SIZE |
| 100 | hex |
| 101 | default 0x400000 |
| 102 | |
| 103 | config HEAP_SIZE |
| 104 | hex |
| 105 | default 0x8000 |
| 106 | |
| 107 | config MAX_ROOT_PORTS |
| 108 | int |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 109 | default 8 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 110 | |
| 111 | config MAX_PCIE_CLOCKS |
| 112 | int |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 113 | default 6 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 114 | |
| 115 | config SMM_TSEG_SIZE |
| 116 | hex |
| 117 | default 0x800000 |
| 118 | |
| 119 | config SMM_RESERVED_SIZE |
| 120 | hex |
| 121 | default 0x200000 |
| 122 | |
| 123 | config PCR_BASE_ADDRESS |
| 124 | hex |
| 125 | default 0xfd000000 |
| 126 | help |
| 127 | This option allows you to select MMIO Base Address of sideband bus. |
| 128 | |
| 129 | config MMCONF_BASE_ADDRESS |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 130 | default 0xc0000000 |
| 131 | |
| 132 | config CPU_BCLK_MHZ |
| 133 | int |
| 134 | default 100 |
| 135 | |
| 136 | config SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ |
| 137 | int |
| 138 | default 120 |
| 139 | |
| 140 | config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ |
| 141 | int |
| 142 | default 133 |
| 143 | |
Michael Niewöhner | dadcbfb | 2020-10-04 14:48:05 +0200 | [diff] [blame] | 144 | config CPU_XTAL_HZ |
| 145 | default 38400000 |
| 146 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 147 | config SOC_INTEL_COMMON_BLOCK_GSPI_MAX |
| 148 | int |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 149 | default 3 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 150 | |
| 151 | config SOC_INTEL_I2C_DEV_MAX |
| 152 | int |
| 153 | default 6 |
| 154 | |
| 155 | config SOC_INTEL_UART_DEV_MAX |
| 156 | int |
| 157 | default 3 |
| 158 | |
| 159 | config CONSOLE_UART_BASE_ADDRESS |
| 160 | hex |
| 161 | default 0xfe032000 |
| 162 | depends on INTEL_LPSS_UART_FOR_CONSOLE |
| 163 | |
| 164 | # Clock divider parameters for 115200 baud rate |
| 165 | # Baudrate = (UART source clcok * M) /(N *16) |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 166 | # JSL UART source clock: 100MHz |
| 167 | config SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL |
| 168 | hex |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 169 | default 0x30 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 170 | |
| 171 | config SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL |
| 172 | hex |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 173 | default 0xc35 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 174 | |
| 175 | config CHROMEOS |
| 176 | select CHROMEOS_RAMOOPS_DYNAMIC |
| 177 | |
| 178 | config VBOOT |
| 179 | select VBOOT_SEPARATE_VERSTAGE |
| 180 | select VBOOT_MUST_REQUEST_DISPLAY |
| 181 | select VBOOT_STARTS_IN_BOOTBLOCK |
| 182 | select VBOOT_VBNV_CMOS |
| 183 | select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH |
| 184 | |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 185 | config CBFS_SIZE |
| 186 | hex |
| 187 | default 0x200000 |
| 188 | |
| 189 | config FSP_HEADER_PATH |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 190 | default "src/vendorcode/intel/fsp/fsp2_0/jasperlake/" |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 191 | |
| 192 | config FSP_FD_PATH |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 193 | default "3rdparty/fsp/JasperLakeFspBinPkg/Fsp.fd" |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 194 | |
Aamir Bohra | a23e0c9 | 2020-03-25 15:31:12 +0530 | [diff] [blame] | 195 | config SOC_INTEL_JASPERLAKE_DEBUG_CONSENT |
Aamir Bohra | 512b77a | 2020-03-25 13:20:34 +0530 | [diff] [blame] | 196 | int "Debug Consent for JSL" |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 197 | # USB DBC is more common for developers so make this default to 3 if |
| 198 | # SOC_INTEL_DEBUG_CONSENT=y |
| 199 | default 3 if SOC_INTEL_DEBUG_CONSENT |
| 200 | default 0 |
| 201 | help |
| 202 | This is to control debug interface on SOC. |
| 203 | Setting non-zero value will allow to use DBC or DCI to debug SOC. |
| 204 | PlatformDebugConsent in FspmUpd.h has the details. |
| 205 | |
| 206 | Desired platform debug type are |
| 207 | 0:Disabled, 1:Enabled (DCI OOB+[DbC]), 2:Enabled (DCI OOB), |
| 208 | 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled (USB2 DbC), |
| 209 | 6:Enable (2-wire DCI OOB), 7:Manual |
Subrata Banik | ebf1daa | 2020-05-19 12:32:41 +0530 | [diff] [blame] | 210 | |
| 211 | config PRERAM_CBMEM_CONSOLE_SIZE |
| 212 | hex |
Meera Ravindranath | 6aa6f1f | 2020-08-10 15:19:23 +0530 | [diff] [blame] | 213 | default 0x1400 |
Aamir Bohra | dd7acaa | 2020-03-25 11:36:22 +0530 | [diff] [blame] | 214 | endif |