Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 1 | /* |
| 2 | * This file is part of the coreboot project. |
| 3 | * |
| 4 | * Copyright (C) 2007-2010 coresystems GmbH |
| 5 | * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; version 2 of the License. |
| 10 | * |
| 11 | * This program is distributed in the hope that it will be useful, |
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 14 | * GNU General Public License for more details. |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 15 | */ |
| 16 | |
| 17 | #include <stdint.h> |
Kyösti Mälkki | f1b58b7 | 2019-03-01 13:43:02 +0200 | [diff] [blame] | 18 | #include <device/pci_ops.h> |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 19 | #include <device/pci_def.h> |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 20 | #include <cpu/x86/lapic.h> |
| 21 | #include <pc80/mc146818rtc.h> |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 22 | #include <console/console.h> |
Kyösti Mälkki | e3ddee0 | 2014-05-03 10:45:28 +0300 | [diff] [blame] | 23 | #include <bootmode.h> |
Edward O'Callaghan | 1b3acb1 | 2014-06-01 18:04:05 +1000 | [diff] [blame] | 24 | #include <superio/ite/common/ite.h> |
| 25 | #include <superio/ite/it8772f/it8772f.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 26 | #include <northbridge/intel/sandybridge/sandybridge.h> |
| 27 | #include <northbridge/intel/sandybridge/raminit.h> |
Vladimir Serbinenko | d2990c9 | 2016-02-10 02:52:42 +0100 | [diff] [blame] | 28 | #include <northbridge/intel/sandybridge/raminit_native.h> |
Edward O'Callaghan | 77757c2 | 2015-01-04 21:33:39 +1100 | [diff] [blame] | 29 | #include <southbridge/intel/bd82x6x/pch.h> |
Patrick Rudolph | e8e66f4 | 2016-02-06 17:42:42 +0100 | [diff] [blame] | 30 | #include <southbridge/intel/common/gpio.h> |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 31 | #if CONFIG(DRIVERS_UART_8250IO) |
Edward O'Callaghan | 74834e0 | 2015-01-04 04:17:35 +1100 | [diff] [blame] | 32 | #include <superio/smsc/lpc47n207/lpc47n207.h> |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 33 | #endif |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 34 | |
| 35 | /* Stumpy USB Reset Disable defined in cmos.layout */ |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 36 | #if CONFIG(USE_OPTION_TABLE) |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 37 | #include "option_table.h" |
| 38 | #define CMOS_USB_RESET_DISABLE (CMOS_VSTART_stumpy_usb_reset_disable >> 3) |
| 39 | #else |
| 40 | #define CMOS_USB_RESET_DISABLE (400 >> 3) |
| 41 | #endif |
| 42 | #define USB_RESET_DISABLE_MAGIC (0xdd) /* Disable if set to this */ |
| 43 | |
Elyes HAOUAS | f5f1b38 | 2018-04-26 09:43:03 +0200 | [diff] [blame] | 44 | #define SUPERIO_DEV PNP_DEV(0x2e, 0) |
Edward O'Callaghan | 1b3acb1 | 2014-06-01 18:04:05 +1000 | [diff] [blame] | 45 | #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1) |
| 46 | #define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO) |
| 47 | |
Arthur Heymans | 2b28a16 | 2019-11-12 17:21:08 +0100 | [diff] [blame^] | 48 | void mainboard_pch_lpc_setup(void) |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 49 | { |
| 50 | /* Set COM1/COM2 decode range */ |
| 51 | pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); |
| 52 | |
Julius Werner | cd49cce | 2019-03-05 16:53:33 -0800 | [diff] [blame] | 53 | #if CONFIG(DRIVERS_UART_8250IO) |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 54 | /* Enable SuperIO + PS/2 Keyboard/Mouse + COM1 + lpc47n207 config*/ |
| 55 | pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN |\ |
| 56 | CNF2_LPC_EN | COMA_LPC_EN); |
| 57 | |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 58 | try_enabling_LPC47N207_uart(); |
| 59 | #else |
| 60 | /* Enable SuperIO + PS/2 Keyboard/Mouse */ |
| 61 | pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN); |
| 62 | #endif |
| 63 | } |
| 64 | |
Arthur Heymans | 9c53834 | 2019-11-12 16:42:33 +0100 | [diff] [blame] | 65 | void mainboard_late_rcba_config(void) |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 66 | { |
Kyösti Mälkki | 6f49906 | 2015-06-06 11:52:24 +0300 | [diff] [blame] | 67 | /* |
| 68 | * GFX INTA -> PIRQA (MSI) |
| 69 | * D28IP_P1IP WLAN INTA -> PIRQB |
| 70 | * D28IP_P4IP ETH0 INTB -> PIRQC |
| 71 | * D29IP_E1P EHCI1 INTA -> PIRQD |
| 72 | * D26IP_E2P EHCI2 INTA -> PIRQE |
| 73 | * D31IP_SIP SATA INTA -> PIRQF (MSI) |
| 74 | * D31IP_SMIP SMBUS INTB -> PIRQG |
| 75 | * D31IP_TTIP THRT INTC -> PIRQH |
| 76 | * D27IP_ZIP HDA INTA -> PIRQG (MSI) |
| 77 | */ |
| 78 | |
| 79 | /* Device interrupt pin register (board specific) */ |
| 80 | RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | |
| 81 | (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); |
| 82 | RCBA32(D30IP) = (NOINT << D30IP_PIP); |
| 83 | RCBA32(D29IP) = (INTA << D29IP_E1P); |
| 84 | RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | |
| 85 | (INTB << D28IP_P4IP); |
| 86 | RCBA32(D27IP) = (INTA << D27IP_ZIP); |
| 87 | RCBA32(D26IP) = (INTA << D26IP_E2P); |
| 88 | RCBA32(D25IP) = (NOINT << D25IP_LIP); |
| 89 | RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); |
| 90 | |
| 91 | /* Device interrupt route registers */ |
| 92 | DIR_ROUTE(D31IR, PIRQF, PIRQG, PIRQH, PIRQA); |
| 93 | DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); |
| 94 | DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE); |
| 95 | DIR_ROUTE(D27IR, PIRQG, PIRQH, PIRQA, PIRQB); |
| 96 | DIR_ROUTE(D26IR, PIRQE, PIRQF, PIRQG, PIRQH); |
| 97 | DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 98 | DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); |
| 99 | |
| 100 | /* Enable IOAPIC (generic) */ |
Arthur Heymans | 58a8953 | 2018-06-12 22:58:19 +0200 | [diff] [blame] | 101 | RCBA16(OIC) = 0x0100; |
Kyösti Mälkki | 6f49906 | 2015-06-06 11:52:24 +0300 | [diff] [blame] | 102 | /* PCH BWG says to read back the IOAPIC enable register */ |
Arthur Heymans | 58a8953 | 2018-06-12 22:58:19 +0200 | [diff] [blame] | 103 | (void) RCBA16(OIC); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 104 | } |
| 105 | |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 106 | static void setup_sio_gpios(void) |
| 107 | { |
| 108 | /* |
| 109 | * GPIO10 as USBPWRON12# |
| 110 | * GPIO12 as USBPWRON13# |
| 111 | */ |
Elyes HAOUAS | f5f1b38 | 2018-04-26 09:43:03 +0200 | [diff] [blame] | 112 | it8772f_gpio_setup(SUPERIO_DEV, 1, 0x05, 0x05, 0x00, 0x05, 0x05); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 113 | |
| 114 | /* |
| 115 | * GPIO22 as wake SCI# |
| 116 | */ |
Elyes HAOUAS | f5f1b38 | 2018-04-26 09:43:03 +0200 | [diff] [blame] | 117 | it8772f_gpio_setup(SUPERIO_DEV, 2, 0x04, 0x04, 0x00, 0x04, 0x04); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 118 | |
| 119 | /* |
| 120 | * GPIO32 as EXTSMI# |
| 121 | */ |
Elyes HAOUAS | f5f1b38 | 2018-04-26 09:43:03 +0200 | [diff] [blame] | 122 | it8772f_gpio_setup(SUPERIO_DEV, 3, 0x04, 0x04, 0x00, 0x04, 0x04); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 123 | |
| 124 | /* |
| 125 | * GPIO45 as LED_POWER# |
| 126 | */ |
Matt DeVillier | ffae746 | 2016-11-07 16:43:03 -0600 | [diff] [blame] | 127 | it8772f_gpio_led(GPIO_DEV, 4 /* set */, (0x1 << 5) /* select */, |
| 128 | (0x1 << 5) /* polarity */, (0x1 << 5) /* 1 = pullup */, |
Elyes HAOUAS | a5aad2e | 2016-09-19 09:47:16 -0600 | [diff] [blame] | 129 | (0x1 << 5) /* output */, (0x1 << 5) /* 1 = Simple IO function */, |
david | 80ef7b7 | 2015-01-19 17:11:36 +0800 | [diff] [blame] | 130 | SIO_GPIO_BLINK_GPIO45, IT8772F_GPIO_BLINK_FREQUENCY_1_HZ); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 131 | |
| 132 | /* |
| 133 | * GPIO51 as USBPWRON8# |
| 134 | * GPIO52 as USBPWRON1# |
| 135 | */ |
Elyes HAOUAS | f5f1b38 | 2018-04-26 09:43:03 +0200 | [diff] [blame] | 136 | it8772f_gpio_setup(SUPERIO_DEV, 5, 0x06, 0x06, 0x00, 0x06, 0x06); |
| 137 | it8772f_gpio_setup(SUPERIO_DEV, 6, 0x00, 0x00, 0x00, 0x00, 0x00); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 138 | } |
| 139 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 140 | void mainboard_fill_pei_data(struct pei_data *pei_data) |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 141 | { |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 142 | struct pei_data pei_data_template = { |
Edward O'Callaghan | b27d360 | 2014-05-24 02:40:31 +1000 | [diff] [blame] | 143 | .pei_version = PEI_VERSION, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 144 | .mchbar = (uintptr_t)DEFAULT_MCHBAR, |
| 145 | .dmibar = (uintptr_t)DEFAULT_DMIBAR, |
Edward O'Callaghan | b27d360 | 2014-05-24 02:40:31 +1000 | [diff] [blame] | 146 | .epbar = DEFAULT_EPBAR, |
| 147 | .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, |
| 148 | .smbusbar = SMBUS_IO_BASE, |
| 149 | .wdbbar = 0x4000000, |
| 150 | .wdbsize = 0x1000, |
| 151 | .hpet_address = CONFIG_HPET_ADDRESS, |
Kevin Paul Herbert | bde6d30 | 2014-12-24 18:43:20 -0800 | [diff] [blame] | 152 | .rcba = (uintptr_t)DEFAULT_RCBABASE, |
Edward O'Callaghan | b27d360 | 2014-05-24 02:40:31 +1000 | [diff] [blame] | 153 | .pmbase = DEFAULT_PMBASE, |
| 154 | .gpiobase = DEFAULT_GPIOBASE, |
| 155 | .thermalbase = 0xfed08000, |
| 156 | .system_type = 0, // 0 Mobile, 1 Desktop/Server |
| 157 | .tseg_size = CONFIG_SMM_TSEG_SIZE, |
| 158 | .spd_addresses = { 0xa0, 0x00,0xa4,0x00 }, |
| 159 | .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, |
| 160 | .ec_present = 0, |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 161 | // 0 = leave channel enabled |
| 162 | // 1 = disable dimm 0 on channel |
| 163 | // 2 = disable dimm 1 on channel |
| 164 | // 3 = disable dimm 0+1 on channel |
Edward O'Callaghan | b27d360 | 2014-05-24 02:40:31 +1000 | [diff] [blame] | 165 | .dimm_channel0_disabled = 2, |
| 166 | .dimm_channel1_disabled = 2, |
| 167 | .max_ddr3_freq = 1333, |
| 168 | .usb_port_config = { |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 169 | { 1, 0, 0x0080 }, /* P0: Front port (OC0) */ |
| 170 | { 1, 1, 0x0040 }, /* P1: Back port (OC1) */ |
| 171 | { 1, 0, 0x0040 }, /* P2: MINIPCIE1 (no OC) */ |
| 172 | { 1, 0, 0x0040 }, /* P3: MMC (no OC) */ |
| 173 | { 1, 2, 0x0080 }, /* P4: Front port (OC2) */ |
| 174 | { 0, 0, 0x0000 }, /* P5: Empty */ |
| 175 | { 0, 0, 0x0000 }, /* P6: Empty */ |
| 176 | { 0, 0, 0x0000 }, /* P7: Empty */ |
| 177 | { 1, 4, 0x0040 }, /* P8: Back port (OC4) */ |
| 178 | { 1, 4, 0x0040 }, /* P9: MINIPCIE3 (no OC) */ |
| 179 | { 1, 4, 0x0040 }, /* P10: BLUETOOTH (no OC) */ |
| 180 | { 0, 4, 0x0000 }, /* P11: Empty */ |
| 181 | { 1, 6, 0x0040 }, /* P12: Back port (OC6) */ |
| 182 | { 1, 5, 0x0040 }, /* P13: Back port (OC5) */ |
| 183 | }, |
| 184 | }; |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 185 | *pei_data = pei_data_template; |
| 186 | } |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 187 | |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 188 | void mainboard_get_spd(spd_raw_data *spd, bool id_only) |
Vladimir Serbinenko | d2990c9 | 2016-02-10 02:52:42 +0100 | [diff] [blame] | 189 | { |
Kyösti Mälkki | e258b9a | 2016-11-18 19:59:23 +0200 | [diff] [blame] | 190 | read_spd(&spd[0], 0x50, id_only); |
| 191 | read_spd(&spd[2], 0x52, id_only); |
Vladimir Serbinenko | d2990c9 | 2016-02-10 02:52:42 +0100 | [diff] [blame] | 192 | } |
| 193 | |
| 194 | const struct southbridge_usb_port mainboard_usb_ports[] = { |
| 195 | /* enabled power usb oc pin */ |
| 196 | { 1, 1, 0 }, /* P0: Front port (OC0) */ |
| 197 | { 1, 0, 1 }, /* P1: Back port (OC1) */ |
| 198 | { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ |
| 199 | { 1, 0, -1 }, /* P3: MMC (no OC) */ |
| 200 | { 1, 1, 2 }, /* P4: Front port (OC2) */ |
| 201 | { 0, 0, -1 }, /* P5: Empty */ |
| 202 | { 0, 0, -1 }, /* P6: Empty */ |
| 203 | { 0, 0, -1 }, /* P7: Empty */ |
| 204 | { 1, 0, 4 }, /* P8: Back port (OC4) */ |
| 205 | { 1, 0, -1 }, /* P9: MINIPCIE3 (no OC) */ |
| 206 | { 1, 0, -1 }, /* P10: BLUETOOTH (no OC) */ |
| 207 | { 0, 0, -1 }, /* P11: Empty */ |
| 208 | { 1, 0, 6 }, /* P12: Back port (OC6) */ |
| 209 | { 1, 0, 5 }, /* P13: Back port (OC5) */ |
| 210 | }; |
| 211 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 212 | void mainboard_early_init(int s3resume) |
| 213 | { |
Kyösti Mälkki | e3ddee0 | 2014-05-03 10:45:28 +0300 | [diff] [blame] | 214 | init_bootmode_straps(); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 215 | } |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 216 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 217 | int mainboard_should_reset_usb(int s3resume) |
| 218 | { |
| 219 | if (s3resume) { |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 220 | /* |
| 221 | * For Stumpy the back USB ports are reset on resume |
| 222 | * so default to resetting the controller to make the |
| 223 | * kernel happy. There is a CMOS flag to disable the |
| 224 | * controller reset in case the kernel can tolerate |
| 225 | * the device power loss better in the future. |
| 226 | */ |
| 227 | u8 magic = cmos_read(CMOS_USB_RESET_DISABLE); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 228 | if (magic == USB_RESET_DISABLE_MAGIC) { |
| 229 | printk(BIOS_DEBUG, "USB Controller Reset Disabled\n"); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 230 | return 0; |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 231 | } else { |
| 232 | printk(BIOS_DEBUG, "USB Controller Reset Enabled\n"); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 233 | return 1; |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 234 | } |
| 235 | } else { |
| 236 | /* Ensure USB reset on resume is enabled at boot */ |
| 237 | cmos_write(0, CMOS_USB_RESET_DISABLE); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 238 | return 1; |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 239 | } |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 240 | } |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 241 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 242 | void mainboard_config_superio(void) |
| 243 | { |
| 244 | setup_sio_gpios(); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 245 | |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 246 | /* Early SuperIO setup */ |
Elyes HAOUAS | f5f1b38 | 2018-04-26 09:43:03 +0200 | [diff] [blame] | 247 | it8772f_ac_resume_southbridge(SUPERIO_DEV); |
Vladimir Serbinenko | ffbb3c0 | 2016-02-10 01:36:25 +0100 | [diff] [blame] | 248 | ite_kill_watchdog(GPIO_DEV); |
| 249 | ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); |
Stefan Reinauer | e1ae4b2 | 2012-04-27 23:20:58 +0200 | [diff] [blame] | 250 | } |