Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"
In the end it does not look like RCBA register offsets are fully
compatible over southbridges.
This reverts commit d2d2aef6a3222af909183fb96dc7bc908fac3cd4.
Is squashed with revert of "sb/intel/common: Fix conflicting OIC
register definition" 8aaa00401b68e5c5b6c07b0984e3e7c3027e3c2f.
Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c
index 9f1e3f6..f502cc3 100644
--- a/src/mainboard/samsung/stumpy/romstage.c
+++ b/src/mainboard/samsung/stumpy/romstage.c
@@ -32,7 +32,6 @@
#include <northbridge/intel/sandybridge/sandybridge.h>
#include <northbridge/intel/sandybridge/raminit.h>
#include <northbridge/intel/sandybridge/raminit_native.h>
-#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/bd82x6x/pch.h>
#include <southbridge/intel/common/gpio.h>
#include <arch/cpu.h>
@@ -112,9 +111,9 @@
DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
/* Enable IOAPIC (generic) */
- RCBA16(EOIC) = 0x0100;
+ RCBA16(OIC) = 0x0100;
/* PCH BWG says to read back the IOAPIC enable register */
- (void) RCBA16(EOIC);
+ (void) RCBA16(OIC);
}
static void setup_sio_gpios(void)