Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
| 2 | |
| 3 | #include <assert.h> |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 4 | #include <cbfs.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 5 | #include <console/console.h> |
Subrata Banik | 7b523a4 | 2021-09-22 16:46:16 +0530 | [diff] [blame] | 6 | #include <cpu/intel/microcode.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 7 | #include <device/device.h> |
| 8 | #include <device/pci.h> |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 9 | #include <device/pci_ids.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 10 | #include <fsp/api.h> |
| 11 | #include <fsp/ppi/mp_service_ppi.h> |
| 12 | #include <fsp/util.h> |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 13 | #include <option.h> |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 14 | #include <intelblocks/irq.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 15 | #include <intelblocks/lpss.h> |
Tim Wawrzynczak | ab0e081 | 2021-09-21 10:28:16 -0600 | [diff] [blame] | 16 | #include <intelblocks/pmclib.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 17 | #include <intelblocks/xdci.h> |
| 18 | #include <intelpch/lockdown.h> |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 19 | #include <intelblocks/tcss.h> |
Tim Wawrzynczak | e2b8f30 | 2021-07-19 15:35:47 -0600 | [diff] [blame] | 20 | #include <soc/cpu.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 21 | #include <soc/gpio_soc_defs.h> |
| 22 | #include <soc/intel/common/vbt.h> |
| 23 | #include <soc/pci_devs.h> |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 24 | #include <soc/pcie.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 25 | #include <soc/ramstage.h> |
| 26 | #include <soc/soc_chip.h> |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 27 | #include <stdlib.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 28 | #include <string.h> |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 29 | #include <types.h> |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 30 | |
| 31 | /* THC assignment definition */ |
| 32 | #define THC_NONE 0 |
| 33 | #define THC_0 1 |
| 34 | #define THC_1 2 |
| 35 | |
| 36 | /* SATA DEVSLP idle timeout default values */ |
| 37 | #define DEF_DMVAL 15 |
| 38 | #define DEF_DITOVAL 625 |
| 39 | |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 40 | /* VccIn Aux Imon IccMax values in mA */ |
| 41 | #define MILLIAMPS_TO_AMPS 1000 |
| 42 | #define ICC_MAX_ID_ADL_P_3_MA 34250 |
| 43 | #define ICC_MAX_ID_ADL_P_5_MA 32000 |
Tracy Wu | 697d6a8 | 2021-09-27 16:48:32 +0800 | [diff] [blame] | 44 | #define ICC_MAX_ID_ADL_P_6_MA 32000 |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 45 | #define ICC_MAX_ID_ADL_P_7_MA 32000 |
| 46 | |
Tim Wawrzynczak | c0e82e7 | 2021-06-17 12:42:35 -0600 | [diff] [blame] | 47 | /* |
| 48 | * ME End of Post configuration |
| 49 | * 0 - Disable EOP. |
| 50 | * 1 - Send in PEI (Applicable for FSP in API mode) |
| 51 | * 2 - Send in DXE (Not applicable for FSP in API mode) |
| 52 | */ |
| 53 | enum fsp_end_of_post { |
| 54 | EOP_DISABLE = 0, |
| 55 | EOP_PEI = 1, |
| 56 | EOP_DXE = 2, |
| 57 | }; |
| 58 | |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 59 | static const struct slot_irq_constraints irq_constraints[] = { |
| 60 | { |
| 61 | .slot = SA_DEV_SLOT_IGD, |
| 62 | .fns = { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 63 | /* INTERRUPT_PIN is RO/0x01 */ |
| 64 | FIXED_INT_ANY_PIRQ(SA_DEVFN_IGD, PCI_INT_A), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 65 | }, |
| 66 | }, |
| 67 | { |
| 68 | .slot = SA_DEV_SLOT_DPTF, |
| 69 | .fns = { |
| 70 | ANY_PIRQ(SA_DEVFN_DPTF), |
| 71 | }, |
| 72 | }, |
| 73 | { |
| 74 | .slot = SA_DEV_SLOT_IPU, |
| 75 | .fns = { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 76 | /* INTERRUPT_PIN is RO/0x01, and INTERRUPT_LINE is RW, |
| 77 | but S0ix fails when not set to 16 (b/193434192) */ |
| 78 | FIXED_INT_PIRQ(SA_DEVFN_IPU, PCI_INT_A, PIRQ_A), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 79 | }, |
| 80 | }, |
| 81 | { |
| 82 | .slot = SA_DEV_SLOT_CPU_6, |
| 83 | .fns = { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 84 | FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_0, PCI_INT_A, PIRQ_A), |
| 85 | FIXED_INT_PIRQ(SA_DEVFN_CPU_PCIE6_2, PCI_INT_C, PIRQ_C), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 86 | }, |
| 87 | }, |
| 88 | { |
| 89 | .slot = SA_DEV_SLOT_TBT, |
| 90 | .fns = { |
| 91 | ANY_PIRQ(SA_DEVFN_TBT0), |
| 92 | ANY_PIRQ(SA_DEVFN_TBT1), |
| 93 | ANY_PIRQ(SA_DEVFN_TBT2), |
| 94 | ANY_PIRQ(SA_DEVFN_TBT3), |
| 95 | }, |
| 96 | }, |
| 97 | { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 98 | .slot = SA_DEV_SLOT_GNA, |
| 99 | .fns = { |
| 100 | /* INTERRUPT_PIN is RO/0x01 */ |
| 101 | FIXED_INT_ANY_PIRQ(SA_DEVFN_GNA, PCI_INT_A), |
| 102 | }, |
| 103 | }, |
| 104 | { |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 105 | .slot = SA_DEV_SLOT_TCSS, |
| 106 | .fns = { |
| 107 | ANY_PIRQ(SA_DEVFN_TCSS_XHCI), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 108 | ANY_PIRQ(SA_DEVFN_TCSS_XDCI), |
| 109 | }, |
| 110 | }, |
| 111 | { |
| 112 | .slot = PCH_DEV_SLOT_SIO0, |
| 113 | .fns = { |
| 114 | DIRECT_IRQ(PCH_DEVFN_I2C6), |
| 115 | DIRECT_IRQ(PCH_DEVFN_I2C7), |
| 116 | ANY_PIRQ(PCH_DEVFN_THC0), |
| 117 | ANY_PIRQ(PCH_DEVFN_THC1), |
| 118 | }, |
| 119 | }, |
| 120 | { |
| 121 | .slot = PCH_DEV_SLOT_SIO6, |
| 122 | .fns = { |
| 123 | DIRECT_IRQ(PCH_DEVFN_UART3), |
| 124 | DIRECT_IRQ(PCH_DEVFN_UART4), |
| 125 | DIRECT_IRQ(PCH_DEVFN_UART5), |
| 126 | DIRECT_IRQ(PCH_DEVFN_UART6), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 127 | }, |
| 128 | }, |
| 129 | { |
| 130 | .slot = PCH_DEV_SLOT_ISH, |
| 131 | .fns = { |
| 132 | DIRECT_IRQ(PCH_DEVFN_ISH), |
| 133 | DIRECT_IRQ(PCH_DEVFN_GSPI2), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 134 | ANY_PIRQ(PCH_DEVFN_UFS), |
| 135 | }, |
| 136 | }, |
| 137 | { |
| 138 | .slot = PCH_DEV_SLOT_SIO2, |
| 139 | .fns = { |
| 140 | DIRECT_IRQ(PCH_DEVFN_GSPI3), |
| 141 | DIRECT_IRQ(PCH_DEVFN_GSPI4), |
| 142 | DIRECT_IRQ(PCH_DEVFN_GSPI5), |
| 143 | DIRECT_IRQ(PCH_DEVFN_GSPI6), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 144 | }, |
| 145 | }, |
| 146 | { |
| 147 | .slot = PCH_DEV_SLOT_XHCI, |
| 148 | .fns = { |
| 149 | ANY_PIRQ(PCH_DEVFN_XHCI), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 150 | DIRECT_IRQ(PCH_DEVFN_USBOTG), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 151 | ANY_PIRQ(PCH_DEVFN_CNVI_WIFI), |
| 152 | }, |
| 153 | }, |
| 154 | { |
| 155 | .slot = PCH_DEV_SLOT_SIO3, |
| 156 | .fns = { |
| 157 | DIRECT_IRQ(PCH_DEVFN_I2C0), |
| 158 | DIRECT_IRQ(PCH_DEVFN_I2C1), |
| 159 | DIRECT_IRQ(PCH_DEVFN_I2C2), |
| 160 | DIRECT_IRQ(PCH_DEVFN_I2C3), |
| 161 | }, |
| 162 | }, |
| 163 | { |
| 164 | .slot = PCH_DEV_SLOT_CSE, |
| 165 | .fns = { |
| 166 | ANY_PIRQ(PCH_DEVFN_CSE), |
| 167 | ANY_PIRQ(PCH_DEVFN_CSE_2), |
| 168 | ANY_PIRQ(PCH_DEVFN_CSE_IDER), |
| 169 | ANY_PIRQ(PCH_DEVFN_CSE_KT), |
| 170 | ANY_PIRQ(PCH_DEVFN_CSE_3), |
| 171 | ANY_PIRQ(PCH_DEVFN_CSE_4), |
| 172 | }, |
| 173 | }, |
| 174 | { |
| 175 | .slot = PCH_DEV_SLOT_SATA, |
| 176 | .fns = { |
| 177 | ANY_PIRQ(PCH_DEVFN_SATA), |
| 178 | }, |
| 179 | }, |
| 180 | { |
| 181 | .slot = PCH_DEV_SLOT_SIO4, |
| 182 | .fns = { |
| 183 | DIRECT_IRQ(PCH_DEVFN_I2C4), |
| 184 | DIRECT_IRQ(PCH_DEVFN_I2C5), |
| 185 | DIRECT_IRQ(PCH_DEVFN_UART2), |
| 186 | }, |
| 187 | }, |
| 188 | { |
| 189 | .slot = PCH_DEV_SLOT_PCIE, |
| 190 | .fns = { |
| 191 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE1, PCI_INT_A, PIRQ_A), |
| 192 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE2, PCI_INT_B, PIRQ_B), |
| 193 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE3, PCI_INT_C, PIRQ_C), |
| 194 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE4, PCI_INT_D, PIRQ_D), |
| 195 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE5, PCI_INT_A, PIRQ_A), |
| 196 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE6, PCI_INT_B, PIRQ_B), |
| 197 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE7, PCI_INT_C, PIRQ_C), |
| 198 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE8, PCI_INT_D, PIRQ_D), |
| 199 | }, |
| 200 | }, |
| 201 | { |
| 202 | .slot = PCH_DEV_SLOT_PCIE_1, |
| 203 | .fns = { |
| 204 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE9, PCI_INT_A, PIRQ_A), |
| 205 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE10, PCI_INT_B, PIRQ_B), |
| 206 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE11, PCI_INT_C, PIRQ_C), |
| 207 | FIXED_INT_PIRQ(PCH_DEVFN_PCIE12, PCI_INT_D, PIRQ_D), |
| 208 | }, |
| 209 | }, |
| 210 | { |
| 211 | .slot = PCH_DEV_SLOT_SIO5, |
| 212 | .fns = { |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 213 | /* UART0 shares an interrupt line with TSN0, so must use |
| 214 | a PIRQ */ |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 215 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART0, PCI_INT_A), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 216 | /* UART1 shares an interrupt line with TSN1, so must use |
| 217 | a PIRQ */ |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 218 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_UART1, PCI_INT_B), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 219 | DIRECT_IRQ(PCH_DEVFN_GSPI0), |
| 220 | DIRECT_IRQ(PCH_DEVFN_GSPI1), |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 221 | }, |
| 222 | }, |
| 223 | { |
| 224 | .slot = PCH_DEV_SLOT_ESPI, |
| 225 | .fns = { |
| 226 | ANY_PIRQ(PCH_DEVFN_HDA), |
| 227 | ANY_PIRQ(PCH_DEVFN_SMBUS), |
| 228 | ANY_PIRQ(PCH_DEVFN_GBE), |
Tim Wawrzynczak | 82225b8 | 2021-07-09 10:23:10 -0600 | [diff] [blame] | 229 | /* INTERRUPT_PIN is RO/0x01 */ |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 230 | FIXED_INT_ANY_PIRQ(PCH_DEVFN_TRACEHUB, PCI_INT_A), |
| 231 | }, |
| 232 | }, |
| 233 | }; |
| 234 | |
| 235 | static const SI_PCH_DEVICE_INTERRUPT_CONFIG *pci_irq_to_fsp(size_t *out_count) |
| 236 | { |
| 237 | const struct pci_irq_entry *entry = get_cached_pci_irqs(); |
| 238 | SI_PCH_DEVICE_INTERRUPT_CONFIG *config; |
| 239 | size_t pch_total = 0; |
| 240 | size_t cfg_count = 0; |
| 241 | |
| 242 | if (!entry) |
| 243 | return NULL; |
| 244 | |
| 245 | /* Count PCH devices */ |
| 246 | while (entry) { |
| 247 | if (PCI_SLOT(entry->devfn) >= MIN_PCH_SLOT) |
| 248 | ++pch_total; |
| 249 | entry = entry->next; |
| 250 | } |
| 251 | |
| 252 | /* Convert PCH device entries to FSP format */ |
| 253 | config = calloc(pch_total, sizeof(*config)); |
| 254 | entry = get_cached_pci_irqs(); |
| 255 | while (entry) { |
| 256 | if (PCI_SLOT(entry->devfn) < MIN_PCH_SLOT) { |
| 257 | entry = entry->next; |
| 258 | continue; |
| 259 | } |
| 260 | |
| 261 | config[cfg_count].Device = PCI_SLOT(entry->devfn); |
| 262 | config[cfg_count].Function = PCI_FUNC(entry->devfn); |
| 263 | config[cfg_count].IntX = (SI_PCH_INT_PIN)entry->pin; |
| 264 | config[cfg_count].Irq = entry->irq; |
| 265 | ++cfg_count; |
| 266 | |
| 267 | entry = entry->next; |
| 268 | } |
| 269 | |
| 270 | *out_count = cfg_count; |
| 271 | |
| 272 | return config; |
| 273 | } |
| 274 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 275 | /* |
| 276 | * Chip config parameter PcieRpL1Substates uses (UPD value + 1) |
| 277 | * because UPD value of 0 for PcieRpL1Substates means disabled for FSP. |
| 278 | * In order to ensure that mainboard setting does not disable L1 substates |
| 279 | * incorrectly, chip config parameter values are offset by 1 with 0 meaning |
| 280 | * use FSP UPD default. get_l1_substate_control() ensures that the right UPD |
| 281 | * value is set in fsp_params. |
| 282 | * 0: Use FSP UPD default |
| 283 | * 1: Disable L1 substates |
| 284 | * 2: Use L1.1 |
| 285 | * 3: Use L1.2 (FSP UPD default) |
| 286 | */ |
| 287 | static int get_l1_substate_control(enum L1_substates_control ctl) |
| 288 | { |
| 289 | if ((ctl > L1_SS_L1_2) || (ctl == L1_SS_FSP_DEFAULT)) |
| 290 | ctl = L1_SS_L1_2; |
| 291 | return ctl - 1; |
| 292 | } |
| 293 | |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 294 | /* This function returns the VccIn Aux Imon IccMax values for ADL-P SKU's */ |
| 295 | static uint16_t get_vccin_aux_imon_iccmax(void) |
| 296 | { |
| 297 | uint16_t mch_id = 0; |
| 298 | |
| 299 | if (!mch_id) { |
| 300 | struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT); |
| 301 | mch_id = dev ? pci_read_config16(dev, PCI_DEVICE_ID) : 0xffff; |
| 302 | } |
| 303 | |
| 304 | switch (mch_id) { |
| 305 | case PCI_DEVICE_ID_INTEL_ADL_P_ID_3: |
| 306 | return ICC_MAX_ID_ADL_P_3_MA; |
| 307 | case PCI_DEVICE_ID_INTEL_ADL_P_ID_5: |
| 308 | return ICC_MAX_ID_ADL_P_5_MA; |
Tracy Wu | 697d6a8 | 2021-09-27 16:48:32 +0800 | [diff] [blame] | 309 | case PCI_DEVICE_ID_INTEL_ADL_P_ID_6: |
| 310 | return ICC_MAX_ID_ADL_P_6_MA; |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 311 | case PCI_DEVICE_ID_INTEL_ADL_P_ID_7: |
| 312 | return ICC_MAX_ID_ADL_P_7_MA; |
| 313 | default: |
| 314 | printk(BIOS_ERR, "Unknown MCH ID: 0x%4x, skipping VccInAuxImonIccMax config\n", |
| 315 | mch_id); |
| 316 | return 0; |
| 317 | } |
| 318 | } |
| 319 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 320 | __weak void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 321 | { |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 322 | /* Override settings per board. */ |
| 323 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 324 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 325 | static void fill_fsps_lpss_params(FSP_S_CONFIG *s_cfg, |
| 326 | const struct soc_intel_alderlake_config *config) |
| 327 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 328 | for (int i = 0; i < CONFIG_SOC_INTEL_I2C_DEV_MAX; i++) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 329 | s_cfg->SerialIoI2cMode[i] = config->SerialIoI2cMode[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 330 | |
| 331 | for (int i = 0; i < CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX; i++) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 332 | s_cfg->SerialIoSpiMode[i] = config->SerialIoGSpiMode[i]; |
| 333 | s_cfg->SerialIoSpiCsMode[i] = config->SerialIoGSpiCsMode[i]; |
| 334 | s_cfg->SerialIoSpiCsState[i] = config->SerialIoGSpiCsState[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 335 | } |
| 336 | |
| 337 | for (int i = 0; i < CONFIG_SOC_INTEL_UART_DEV_MAX; i++) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 338 | s_cfg->SerialIoUartMode[i] = config->SerialIoUartMode[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 339 | } |
| 340 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 341 | static void fill_fsps_cpu_params(FSP_S_CONFIG *s_cfg, |
| 342 | const struct soc_intel_alderlake_config *config) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 343 | { |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 344 | const struct microcode *microcode_file; |
| 345 | size_t microcode_len; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 346 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 347 | /* Locate microcode and pass to FSP-S for 2nd microcode loading */ |
Subrata Banik | 7b523a4 | 2021-09-22 16:46:16 +0530 | [diff] [blame] | 348 | microcode_file = intel_microcode_find(); |
| 349 | microcode_len = get_microcode_size(microcode_file); |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 350 | |
| 351 | if ((microcode_file != NULL) && (microcode_len != 0)) { |
| 352 | /* Update CPU Microcode patch base address/size */ |
Subrata Banik | 7b523a4 | 2021-09-22 16:46:16 +0530 | [diff] [blame] | 353 | s_cfg->MicrocodeRegionBase = (uint32_t)(uintptr_t)microcode_file; |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 354 | s_cfg->MicrocodeRegionSize = (uint32_t)microcode_len; |
Subrata Banik | 99289a8 | 2020-12-22 10:54:44 +0530 | [diff] [blame] | 355 | } |
| 356 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 357 | /* Use coreboot MP PPI services if Kconfig is enabled */ |
| 358 | if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI)) |
| 359 | s_cfg->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data(); |
| 360 | } |
| 361 | |
| 362 | static void fill_fsps_igd_params(FSP_S_CONFIG *s_cfg, |
| 363 | const struct soc_intel_alderlake_config *config) |
| 364 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 365 | /* Load VBT before devicetree-specific config. */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 366 | s_cfg->GraphicsConfigPtr = (uintptr_t)vbt_get(); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 367 | |
| 368 | /* Check if IGD is present and fill Graphics init param accordingly */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 369 | s_cfg->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); |
| 370 | s_cfg->LidStatus = CONFIG(RUN_FSP_GOP); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 371 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 372 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 373 | static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg, |
| 374 | const struct soc_intel_alderlake_config *config) |
| 375 | { |
Furquan Shaikh | eafca1f | 2021-09-22 13:59:39 -0700 | [diff] [blame] | 376 | const struct device *tcss_port_arr[] = { |
| 377 | DEV_PTR(tcss_usb3_port1), |
| 378 | DEV_PTR(tcss_usb3_port2), |
| 379 | DEV_PTR(tcss_usb3_port3), |
| 380 | DEV_PTR(tcss_usb3_port4), |
| 381 | }; |
| 382 | |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 383 | s_cfg->TcssAuxOri = config->TcssAuxOri; |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 384 | |
| 385 | /* Explicitly clear this field to avoid using defaults */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 386 | memset(s_cfg->IomTypeCPortPadCfg, 0, sizeof(s_cfg->IomTypeCPortPadCfg)); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 387 | |
| 388 | /* |
| 389 | * Set FSPS UPD ITbtConnectTopologyTimeoutInMs with value 0. FSP will |
| 390 | * evaluate this UPD value and skip sending command. There will be no |
| 391 | * delay for command completion. |
| 392 | */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 393 | s_cfg->ITbtConnectTopologyTimeoutInMs = 0; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 394 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 395 | /* D3Hot and D3Cold for TCSS */ |
| 396 | s_cfg->D3HotEnable = !config->TcssD3HotDisable; |
| 397 | s_cfg->D3ColdEnable = !config->TcssD3ColdDisable; |
Bernardo Perez Priego | 421ce56 | 2021-06-09 09:40:31 -0700 | [diff] [blame] | 398 | |
| 399 | s_cfg->UsbTcPortEn = 0; |
| 400 | for (int i = 0; i < MAX_TYPE_C_PORTS; i++) { |
Furquan Shaikh | eafca1f | 2021-09-22 13:59:39 -0700 | [diff] [blame] | 401 | if (is_dev_enabled(tcss_port_arr[i])) |
Bernardo Perez Priego | 421ce56 | 2021-06-09 09:40:31 -0700 | [diff] [blame] | 402 | s_cfg->UsbTcPortEn |= BIT(i); |
| 403 | } |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 404 | } |
| 405 | |
| 406 | static void fill_fsps_chipset_lockdown_params(FSP_S_CONFIG *s_cfg, |
| 407 | const struct soc_intel_alderlake_config *config) |
| 408 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 409 | /* Chipset Lockdown */ |
Felix Singer | f9d7dc7 | 2021-05-03 02:33:15 +0200 | [diff] [blame] | 410 | const bool lockdown_by_fsp = get_lockdown_config() == CHIPSET_LOCKDOWN_FSP; |
| 411 | s_cfg->PchLockDownGlobalSmi = lockdown_by_fsp; |
| 412 | s_cfg->PchLockDownBiosInterface = lockdown_by_fsp; |
| 413 | s_cfg->PchUnlockGpioPads = !lockdown_by_fsp; |
| 414 | s_cfg->RtcMemoryLock = lockdown_by_fsp; |
Tim Wawrzynczak | 091dfa1 | 2021-08-24 09:32:09 -0600 | [diff] [blame] | 415 | s_cfg->SkipPamLock = !lockdown_by_fsp; |
Tim Wawrzynczak | c0e82e7 | 2021-06-17 12:42:35 -0600 | [diff] [blame] | 416 | |
| 417 | /* coreboot will send EOP before loading payload */ |
| 418 | s_cfg->EndOfPostMessage = EOP_DISABLE; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 419 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 420 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 421 | static void fill_fsps_xhci_params(FSP_S_CONFIG *s_cfg, |
| 422 | const struct soc_intel_alderlake_config *config) |
| 423 | { |
| 424 | int i; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 425 | /* USB */ |
| 426 | for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 427 | s_cfg->PortUsb20Enable[i] = config->usb2_ports[i].enable; |
| 428 | s_cfg->Usb2PhyPetxiset[i] = config->usb2_ports[i].pre_emp_bias; |
| 429 | s_cfg->Usb2PhyTxiset[i] = config->usb2_ports[i].tx_bias; |
| 430 | s_cfg->Usb2PhyPredeemp[i] = config->usb2_ports[i].tx_emp_enable; |
| 431 | s_cfg->Usb2PhyPehalfbit[i] = config->usb2_ports[i].pre_emp_bit; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 432 | |
| 433 | if (config->usb2_ports[i].enable) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 434 | s_cfg->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 435 | else |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 436 | s_cfg->Usb2OverCurrentPin[i] = OC_SKIP; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 437 | } |
| 438 | |
| 439 | for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 440 | s_cfg->PortUsb30Enable[i] = config->usb3_ports[i].enable; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 441 | if (config->usb3_ports[i].enable) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 442 | s_cfg->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 443 | else |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 444 | s_cfg->Usb3OverCurrentPin[i] = OC_SKIP; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 445 | |
| 446 | if (config->usb3_ports[i].tx_de_emp) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 447 | s_cfg->Usb3HsioTxDeEmphEnable[i] = 1; |
| 448 | s_cfg->Usb3HsioTxDeEmph[i] = config->usb3_ports[i].tx_de_emp; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 449 | } |
| 450 | if (config->usb3_ports[i].tx_downscale_amp) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 451 | s_cfg->Usb3HsioTxDownscaleAmpEnable[i] = 1; |
| 452 | s_cfg->Usb3HsioTxDownscaleAmp[i] = |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 453 | config->usb3_ports[i].tx_downscale_amp; |
| 454 | } |
| 455 | } |
| 456 | |
Maulik V Vaghela | 6935350 | 2021-04-14 14:01:02 +0530 | [diff] [blame] | 457 | for (i = 0; i < ARRAY_SIZE(config->tcss_ports); i++) { |
| 458 | if (config->tcss_ports[i].enable) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 459 | s_cfg->CpuUsb3OverCurrentPin[i] = config->tcss_ports[i].ocpin; |
Maulik V Vaghela | 6935350 | 2021-04-14 14:01:02 +0530 | [diff] [blame] | 460 | } |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 461 | } |
Maulik V Vaghela | 6935350 | 2021-04-14 14:01:02 +0530 | [diff] [blame] | 462 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 463 | static void fill_fsps_xdci_params(FSP_S_CONFIG *s_cfg, |
| 464 | const struct soc_intel_alderlake_config *config) |
| 465 | { |
Angel Pons | c7cfe0b | 2021-06-23 12:39:22 +0200 | [diff] [blame] | 466 | s_cfg->XdciEnable = xdci_can_enable(PCH_DEVFN_USBOTG); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 467 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 468 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 469 | static void fill_fsps_uart_params(FSP_S_CONFIG *s_cfg, |
| 470 | const struct soc_intel_alderlake_config *config) |
| 471 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 472 | /* PCH UART selection for FSP Debug */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 473 | s_cfg->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; |
| 474 | ASSERT(ARRAY_SIZE(s_cfg->SerialIoUartAutoFlow) > CONFIG_UART_FOR_CONSOLE); |
| 475 | s_cfg->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 476 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 477 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 478 | static void fill_fsps_sata_params(FSP_S_CONFIG *s_cfg, |
| 479 | const struct soc_intel_alderlake_config *config) |
| 480 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 481 | /* SATA */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 482 | s_cfg->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA); |
| 483 | if (s_cfg->SataEnable) { |
| 484 | s_cfg->SataMode = config->SataMode; |
| 485 | s_cfg->SataSalpSupport = config->SataSalpSupport; |
| 486 | memcpy(s_cfg->SataPortsEnable, config->SataPortsEnable, |
| 487 | sizeof(s_cfg->SataPortsEnable)); |
| 488 | memcpy(s_cfg->SataPortsDevSlp, config->SataPortsDevSlp, |
| 489 | sizeof(s_cfg->SataPortsDevSlp)); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 490 | } |
| 491 | |
| 492 | /* |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 493 | * Power Optimizer for SATA. |
| 494 | * SataPwrOptimizeDisable is default to 0. |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 495 | * Boards not needing the optimizers explicitly disables them by setting |
| 496 | * these disable variables to 1 in devicetree overrides. |
| 497 | */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 498 | s_cfg->SataPwrOptEnable = !(config->SataPwrOptimizeDisable); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 499 | /* |
| 500 | * Enable DEVSLP Idle Timeout settings DmVal and DitoVal. |
| 501 | * SataPortsDmVal is the DITO multiplier. Default is 15. |
| 502 | * SataPortsDitoVal is the DEVSLP Idle Timeout (DITO), Default is 625ms. |
| 503 | * The default values can be changed from devicetree. |
| 504 | */ |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 505 | for (size_t i = 0; i < ARRAY_SIZE(config->SataPortsEnableDitoConfig); i++) { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 506 | if (config->SataPortsEnableDitoConfig[i]) { |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 507 | s_cfg->SataPortsDmVal[i] = config->SataPortsDmVal[i]; |
| 508 | s_cfg->SataPortsDitoVal[i] = config->SataPortsDitoVal[i]; |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 509 | } |
| 510 | } |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 511 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 512 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 513 | static void fill_fsps_thermal_params(FSP_S_CONFIG *s_cfg, |
| 514 | const struct soc_intel_alderlake_config *config) |
| 515 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 516 | /* Enable TCPU for processor thermal control */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 517 | s_cfg->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 518 | |
| 519 | /* Set TccActivationOffset */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 520 | s_cfg->TccActivationOffset = config->tcc_offset; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 521 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 522 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 523 | static void fill_fsps_lan_params(FSP_S_CONFIG *s_cfg, |
| 524 | const struct soc_intel_alderlake_config *config) |
| 525 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 526 | /* LAN */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 527 | s_cfg->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 528 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 529 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 530 | static void fill_fsps_cnvi_params(FSP_S_CONFIG *s_cfg, |
| 531 | const struct soc_intel_alderlake_config *config) |
| 532 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 533 | /* CNVi */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 534 | s_cfg->CnviMode = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI); |
| 535 | s_cfg->CnviBtCore = config->CnviBtCore; |
| 536 | s_cfg->CnviBtAudioOffload = config->CnviBtAudioOffload; |
Cliff Huang | bc1941f | 2021-02-10 17:41:41 -0800 | [diff] [blame] | 537 | /* Assert if CNVi BT is enabled without CNVi being enabled. */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 538 | assert(s_cfg->CnviMode || !s_cfg->CnviBtCore); |
Cliff Huang | bc1941f | 2021-02-10 17:41:41 -0800 | [diff] [blame] | 539 | /* Assert if CNVi BT offload is enabled without CNVi BT being enabled. */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 540 | assert(s_cfg->CnviBtCore || !s_cfg->CnviBtAudioOffload); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 541 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 542 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 543 | static void fill_fsps_vmd_params(FSP_S_CONFIG *s_cfg, |
| 544 | const struct soc_intel_alderlake_config *config) |
| 545 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 546 | /* VMD */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 547 | s_cfg->VmdEnable = is_devfn_enabled(SA_DEVFN_VMD); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 548 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 549 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 550 | static void fill_fsps_thc_params(FSP_S_CONFIG *s_cfg, |
| 551 | const struct soc_intel_alderlake_config *config) |
| 552 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 553 | /* THC */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 554 | s_cfg->ThcPort0Assignment = is_devfn_enabled(PCH_DEVFN_THC0) ? THC_0 : THC_NONE; |
| 555 | s_cfg->ThcPort1Assignment = is_devfn_enabled(PCH_DEVFN_THC1) ? THC_1 : THC_NONE; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 556 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 557 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 558 | static void fill_fsps_tbt_params(FSP_S_CONFIG *s_cfg, |
| 559 | const struct soc_intel_alderlake_config *config) |
| 560 | { |
Bernardo Perez Priego | 095f97b | 2021-05-18 18:39:19 -0700 | [diff] [blame] | 561 | /* USB4/TBT */ |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 562 | for (int i = 0; i < ARRAY_SIZE(s_cfg->ITbtPcieRootPortEn); i++) |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 563 | s_cfg->ITbtPcieRootPortEn[i] = is_devfn_enabled(SA_DEVFN_TBT(i)); |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 564 | } |
Bernardo Perez Priego | 095f97b | 2021-05-18 18:39:19 -0700 | [diff] [blame] | 565 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 566 | static void fill_fsps_8254_params(FSP_S_CONFIG *s_cfg, |
| 567 | const struct soc_intel_alderlake_config *config) |
| 568 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 569 | /* Legacy 8254 timer support */ |
Sean Rhodes | bc35bed | 2021-07-13 13:36:28 +0100 | [diff] [blame] | 570 | bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); |
| 571 | s_cfg->Enable8254ClockGating = !use_8254; |
| 572 | s_cfg->Enable8254ClockGatingOnS3 = !use_8254; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 573 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 574 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 575 | static void fill_fsps_storage_params(FSP_S_CONFIG *s_cfg, |
| 576 | const struct soc_intel_alderlake_config *config) |
| 577 | { |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 578 | /* Enable Hybrid storage auto detection */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 579 | s_cfg->HybridStorageMode = config->HybridStorageMode; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 580 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 581 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 582 | static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, |
| 583 | const struct soc_intel_alderlake_config *config) |
| 584 | { |
| 585 | uint32_t enable_mask = pcie_rp_enable_mask(get_pch_pcie_rp_table()); |
| 586 | for (int i = 0; i < CONFIG_MAX_PCH_ROOT_PORTS; i++) { |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 587 | if (!(enable_mask & BIT(i))) |
| 588 | continue; |
| 589 | const struct pcie_rp_config *rp_cfg = &config->pch_pcie_rp[i]; |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 590 | s_cfg->PcieRpL1Substates[i] = |
Eric Lai | 5b302b2 | 2020-12-05 16:49:43 +0800 | [diff] [blame] | 591 | get_l1_substate_control(rp_cfg->PcieRpL1Substates); |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 592 | s_cfg->PcieRpLtrEnable[i] = !!(rp_cfg->flags & PCIE_RP_LTR); |
| 593 | s_cfg->PcieRpAdvancedErrorReporting[i] = !!(rp_cfg->flags & PCIE_RP_AER); |
| 594 | s_cfg->PcieRpHotPlug[i] = !!(rp_cfg->flags & PCIE_RP_HOTPLUG); |
| 595 | s_cfg->PcieRpClkReqDetect[i] = !!(rp_cfg->flags & PCIE_RP_CLK_REQ_DETECT); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 596 | } |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 597 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 598 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 599 | static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, |
| 600 | const struct soc_intel_alderlake_config *config) |
| 601 | { |
Subrata Banik | d6da4ef | 2021-10-07 00:39:31 +0530 | [diff] [blame] | 602 | /* Skip setting D0I3 bit for all HECI devices */ |
| 603 | s_cfg->DisableD0I3SettingForHeci = 1; |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 604 | /* |
| 605 | * Power Optimizer for DMI |
| 606 | * DmiPwrOptimizeDisable is default to 0. |
| 607 | * Boards not needing the optimizers explicitly disables them by setting |
| 608 | * these disable variables to 1 in devicetree overrides. |
| 609 | */ |
| 610 | s_cfg->PchPwrOptEnable = !(config->DmiPwrOptimizeDisable); |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 611 | s_cfg->PmSupport = 1; |
| 612 | s_cfg->Hwp = 1; |
| 613 | s_cfg->Cx = 1; |
| 614 | s_cfg->PsOnEnable = 1; |
V Sowmya | 844dcb3 | 2021-06-21 10:03:53 +0530 | [diff] [blame] | 615 | /* Enable the energy efficient turbo mode */ |
| 616 | s_cfg->EnergyEfficientTurbo = 1; |
V Sowmya | af42906 | 2021-06-21 10:23:33 +0530 | [diff] [blame] | 617 | s_cfg->PkgCStateLimit = LIMIT_AUTO; |
V Sowmya | 458708f | 2021-07-09 22:11:04 +0530 | [diff] [blame] | 618 | |
| 619 | /* VccIn Aux Imon IccMax. Values are in 1/4 Amp increments and range is 0-512. */ |
| 620 | s_cfg->VccInAuxImonIccImax = get_vccin_aux_imon_iccmax() * 4 / MILLIAMPS_TO_AMPS; |
V Sowmya | c6d7166 | 2021-07-15 08:11:08 +0530 | [diff] [blame] | 621 | |
| 622 | /* VrConfig Settings for IA and GT domains */ |
| 623 | for (size_t i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) |
| 624 | fill_vr_domain_config(s_cfg, i, &config->domain_vr_config[i]); |
Tim Wawrzynczak | e2b8f30 | 2021-07-19 15:35:47 -0600 | [diff] [blame] | 625 | |
| 626 | s_cfg->LpmStateEnableMask = get_supported_lpm_mask(); |
Tim Wawrzynczak | ab0e081 | 2021-09-21 10:28:16 -0600 | [diff] [blame] | 627 | |
| 628 | /* Apply minimum assertion width settings */ |
| 629 | if (config->pch_slp_s3_min_assertion_width == SLP_S3_ASSERTION_DEFAULT) |
| 630 | s_cfg->PchPmSlpS3MinAssert = SLP_S3_ASSERTION_50_MS; |
| 631 | else |
| 632 | s_cfg->PchPmSlpS3MinAssert = config->pch_slp_s3_min_assertion_width; |
| 633 | |
| 634 | if (config->pch_slp_s4_min_assertion_width == SLP_S4_ASSERTION_DEFAULT) |
| 635 | s_cfg->PchPmSlpS4MinAssert = SLP_S4_ASSERTION_1S; |
| 636 | else |
| 637 | s_cfg->PchPmSlpS4MinAssert = config->pch_slp_s4_min_assertion_width; |
| 638 | |
| 639 | if (config->pch_slp_sus_min_assertion_width == SLP_SUS_ASSERTION_DEFAULT) |
| 640 | s_cfg->PchPmSlpSusMinAssert = SLP_SUS_ASSERTION_4_S; |
| 641 | else |
| 642 | s_cfg->PchPmSlpSusMinAssert = config->pch_slp_sus_min_assertion_width; |
| 643 | |
| 644 | if (config->pch_slp_a_min_assertion_width == SLP_A_ASSERTION_DEFAULT) |
| 645 | s_cfg->PchPmSlpAMinAssert = SLP_A_ASSERTION_2_S; |
| 646 | else |
| 647 | s_cfg->PchPmSlpAMinAssert = config->pch_slp_a_min_assertion_width; |
| 648 | |
| 649 | unsigned int power_cycle_duration = config->pch_reset_power_cycle_duration; |
| 650 | if (power_cycle_duration == POWER_CYCLE_DURATION_DEFAULT) |
| 651 | power_cycle_duration = POWER_CYCLE_DURATION_4S; |
| 652 | |
| 653 | s_cfg->PchPmPwrCycDur = get_pm_pwr_cyc_dur(s_cfg->PchPmSlpS4MinAssert, |
| 654 | s_cfg->PchPmSlpS3MinAssert, |
| 655 | s_cfg->PchPmSlpAMinAssert, |
| 656 | power_cycle_duration); |
Ryan Lin | 4a48dbe | 2021-09-28 15:59:34 +0800 | [diff] [blame] | 657 | |
| 658 | /* Set PsysPmax if it is available from DT */ |
| 659 | if (config->PsysPmax) { |
| 660 | printk(BIOS_DEBUG, "PsysPmax = %dW\n", config->PsysPmax); |
| 661 | /* PsysPmax is in unit of 1/8 Watt */ |
| 662 | s_cfg->PsysPmax = config->PsysPmax * 8; |
| 663 | } |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 664 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 665 | |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 666 | static void fill_fsps_irq_params(FSP_S_CONFIG *s_cfg, |
| 667 | const struct soc_intel_alderlake_config *config) |
| 668 | { |
| 669 | if (!assign_pci_irqs(irq_constraints, ARRAY_SIZE(irq_constraints))) |
| 670 | die("ERROR: Unable to assign PCI IRQs, and no _PRT table available\n"); |
| 671 | |
| 672 | size_t pch_count = 0; |
| 673 | const SI_PCH_DEVICE_INTERRUPT_CONFIG *upd_irqs = pci_irq_to_fsp(&pch_count); |
| 674 | |
| 675 | s_cfg->DevIntConfigPtr = (UINT32)((uintptr_t)upd_irqs); |
| 676 | s_cfg->NumOfDevIntConfig = pch_count; |
| 677 | printk(BIOS_INFO, "IRQ: Using dynamically assigned PCI IO-APIC IRQs\n"); |
| 678 | } |
| 679 | |
V Sowmya | 418d37e | 2021-06-21 08:47:17 +0530 | [diff] [blame] | 680 | static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg, |
| 681 | const struct soc_intel_alderlake_config *config) |
| 682 | { |
| 683 | /* PCH FIVR settings override */ |
| 684 | if (!config->ext_fivr_settings.configure_ext_fivr) |
| 685 | return; |
| 686 | |
| 687 | s_cfg->PchFivrExtV1p05RailEnabledStates = |
| 688 | config->ext_fivr_settings.v1p05_enable_bitmap; |
| 689 | |
| 690 | s_cfg->PchFivrExtV1p05RailSupportedVoltageStates = |
| 691 | config->ext_fivr_settings.v1p05_supported_voltage_bitmap; |
| 692 | |
| 693 | s_cfg->PchFivrExtVnnRailEnabledStates = |
| 694 | config->ext_fivr_settings.vnn_enable_bitmap; |
| 695 | |
| 696 | s_cfg->PchFivrExtVnnRailSupportedVoltageStates = |
| 697 | config->ext_fivr_settings.vnn_supported_voltage_bitmap; |
| 698 | |
| 699 | s_cfg->PchFivrExtVnnRailSxEnabledStates = |
| 700 | config->ext_fivr_settings.vnn_enable_bitmap; |
| 701 | |
| 702 | /* Convert the voltages to increments of 2.5mv */ |
| 703 | s_cfg->PchFivrExtV1p05RailVoltage = |
| 704 | (config->ext_fivr_settings.v1p05_voltage_mv * 10) / 25; |
| 705 | |
| 706 | s_cfg->PchFivrExtVnnRailVoltage = |
| 707 | (config->ext_fivr_settings.vnn_voltage_mv * 10) / 25; |
| 708 | |
| 709 | s_cfg->PchFivrExtVnnRailSxVoltage = |
| 710 | (config->ext_fivr_settings.vnn_sx_voltage_mv * 10 / 25); |
| 711 | |
| 712 | s_cfg->PchFivrExtV1p05RailIccMaximum = |
| 713 | config->ext_fivr_settings.v1p05_icc_max_ma; |
| 714 | |
| 715 | s_cfg->PchFivrExtVnnRailIccMaximum = |
| 716 | config->ext_fivr_settings.vnn_icc_max_ma; |
| 717 | } |
| 718 | |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 719 | static void soc_silicon_init_params(FSP_S_CONFIG *s_cfg, |
| 720 | struct soc_intel_alderlake_config *config) |
| 721 | { |
| 722 | /* Override settings per board if required. */ |
| 723 | mainboard_update_soc_chip_config(config); |
| 724 | |
V Sowmya | 6464c2a | 2021-06-25 10:20:25 +0530 | [diff] [blame] | 725 | const void (*fill_fsps_params[])(FSP_S_CONFIG *s_cfg, |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 726 | const struct soc_intel_alderlake_config *config) = { |
| 727 | fill_fsps_lpss_params, |
| 728 | fill_fsps_cpu_params, |
| 729 | fill_fsps_igd_params, |
| 730 | fill_fsps_tcss_params, |
| 731 | fill_fsps_chipset_lockdown_params, |
| 732 | fill_fsps_xhci_params, |
| 733 | fill_fsps_xdci_params, |
| 734 | fill_fsps_uart_params, |
| 735 | fill_fsps_sata_params, |
| 736 | fill_fsps_thermal_params, |
| 737 | fill_fsps_lan_params, |
| 738 | fill_fsps_cnvi_params, |
| 739 | fill_fsps_vmd_params, |
| 740 | fill_fsps_thc_params, |
| 741 | fill_fsps_tbt_params, |
| 742 | fill_fsps_8254_params, |
| 743 | fill_fsps_storage_params, |
| 744 | fill_fsps_pcie_params, |
| 745 | fill_fsps_misc_power_params, |
Tim Wawrzynczak | 43607e4 | 2021-05-18 09:04:42 -0600 | [diff] [blame] | 746 | fill_fsps_irq_params, |
V Sowmya | 418d37e | 2021-06-21 08:47:17 +0530 | [diff] [blame] | 747 | fill_fsps_fivr_params, |
Subrata Banik | b03cadf | 2021-06-09 22:19:04 +0530 | [diff] [blame] | 748 | }; |
| 749 | |
| 750 | for (size_t i = 0; i < ARRAY_SIZE(fill_fsps_params); i++) |
| 751 | fill_fsps_params[i](s_cfg, config); |
| 752 | } |
| 753 | |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 754 | /* UPD parameters to be initialized before SiliconInit */ |
| 755 | void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) |
| 756 | { |
| 757 | struct soc_intel_alderlake_config *config; |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 758 | FSP_S_CONFIG *s_cfg = &supd->FspsConfig; |
Subrata Banik | 6f1cb40 | 2021-06-09 22:11:12 +0530 | [diff] [blame] | 759 | |
| 760 | config = config_of_soc(); |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 761 | soc_silicon_init_params(s_cfg, config); |
| 762 | mainboard_silicon_init_params(s_cfg); |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 763 | } |
| 764 | |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 765 | /* |
| 766 | * Callbacks for SoC/Mainboard specific overrides for FspMultiPhaseSiInit |
| 767 | * This platform supports below MultiPhaseSIInit Phase(s): |
| 768 | * Phase | FSP return point | Purpose |
| 769 | * ------- + ------------------------------------------------ + ------------------------------- |
| 770 | * 1 | After TCSS initialization completed | for TCSS specific init |
| 771 | */ |
| 772 | void platform_fsp_multi_phase_init_cb(uint32_t phase_index) |
| 773 | { |
| 774 | switch (phase_index) { |
| 775 | case 1: |
| 776 | /* TCSS specific initialization here */ |
Deepti Deshatty | 8e7facf | 2021-05-12 17:45:37 +0530 | [diff] [blame] | 777 | printk(BIOS_DEBUG, "FSP MultiPhaseSiInit %s/%s called\n", |
| 778 | __FILE__, __func__); |
| 779 | |
| 780 | if (CONFIG(SOC_INTEL_COMMON_BLOCK_TCSS)) { |
| 781 | const config_t *config = config_of_soc(); |
| 782 | tcss_configure(config->typec_aux_bias_pads); |
| 783 | } |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 784 | break; |
| 785 | default: |
| 786 | break; |
| 787 | } |
| 788 | } |
| 789 | |
| 790 | /* Mainboard GPIO Configuration */ |
Subrata Banik | c0983c9 | 2021-06-15 13:02:01 +0530 | [diff] [blame] | 791 | __weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg) |
Subrata Banik | 2871e0e | 2020-09-27 11:30:58 +0530 | [diff] [blame] | 792 | { |
| 793 | printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); |
| 794 | } |