Patrick Georgi | 593124d | 2020-05-10 19:44:08 +0200 | [diff] [blame] | 1 | /* SPDX-License-Identifier: BSD-3-Clause */ |
| 2 | /* This is a driver for a SPI interfaced TPM2 device. |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 3 | * |
| 4 | * It assumes that the required SPI interface has been initialized before the |
| 5 | * driver is started. A 'sruct spi_slave' pointer passed at initialization is |
Martin Roth | 0949e73 | 2021-10-01 14:28:22 -0600 | [diff] [blame] | 6 | * used to direct traffic to the correct SPI interface. This driver does not |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 7 | * provide a way to instantiate multiple TPM devices. Also, to keep things |
| 8 | * simple, the driver unconditionally uses of TPM locality zero. |
| 9 | * |
| 10 | * References to documentation are based on the TCG issued "TPM Profile (PTP) |
| 11 | * Specification Revision 00.43". |
| 12 | */ |
| 13 | |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame] | 14 | #include <assert.h> |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 15 | #include <commonlib/endian.h> |
| 16 | #include <console/console.h> |
| 17 | #include <delay.h> |
| 18 | #include <endian.h> |
| 19 | #include <string.h> |
| 20 | #include <timer.h> |
Philipp Deppenwiese | d88fb36 | 2017-10-18 20:26:18 +0200 | [diff] [blame] | 21 | #include <security/tpm/tis.h> |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 22 | |
| 23 | #include "tpm.h" |
| 24 | |
Vadim Bendebury | 05155c0 | 2016-06-23 12:03:18 -0700 | [diff] [blame] | 25 | #define TPM_LOCALITY_0_SPI_BASE 0x00d40000 |
| 26 | |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 27 | /* Assorted TPM2 registers for interface type FIFO. */ |
Vadim Bendebury | 05155c0 | 2016-06-23 12:03:18 -0700 | [diff] [blame] | 28 | #define TPM_ACCESS_REG (TPM_LOCALITY_0_SPI_BASE + 0) |
| 29 | #define TPM_STS_REG (TPM_LOCALITY_0_SPI_BASE + 0x18) |
| 30 | #define TPM_DATA_FIFO_REG (TPM_LOCALITY_0_SPI_BASE + 0x24) |
| 31 | #define TPM_DID_VID_REG (TPM_LOCALITY_0_SPI_BASE + 0xf00) |
| 32 | #define TPM_RID_REG (TPM_LOCALITY_0_SPI_BASE + 0xf04) |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 33 | #define TPM_FW_VER (TPM_LOCALITY_0_SPI_BASE + 0xf90) |
Jes Klinke | dcae807 | 2020-07-29 14:22:41 -0700 | [diff] [blame] | 34 | #define CR50_BOARD_CFG (TPM_LOCALITY_0_SPI_BASE + 0xfe0) |
| 35 | |
| 36 | #define CR50_BOARD_CFG_LOCKBIT_MASK 0x80000000U |
| 37 | #define CR50_BOARD_CFG_FEATUREBITS_MASK 0x3FFFFFFFU |
| 38 | |
| 39 | #define CR50_BOARD_CFG_100US_READY_PULSE 0x00000001U |
| 40 | #define CR50_BOARD_CFG_VALUE \ |
| 41 | (CONFIG(CR50_USE_LONG_INTERRUPT_PULSES) \ |
| 42 | ? CR50_BOARD_CFG_100US_READY_PULSE : 0) |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 43 | |
Shelley Chen | 85eb031 | 2017-11-07 14:24:19 -0800 | [diff] [blame] | 44 | #define CR50_TIMEOUT_INIT_MS 30000 /* Very long timeout for TPM init */ |
| 45 | |
Furquan Shaikh | bdf86a6 | 2017-04-03 23:52:01 -0700 | [diff] [blame] | 46 | /* SPI slave structure for TPM device. */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 47 | static struct spi_slave spi_slave; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 48 | |
| 49 | /* Cached TPM device identification. */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 50 | static struct tpm2_info tpm_info; |
Jes Klinke | dcae807 | 2020-07-29 14:22:41 -0700 | [diff] [blame] | 51 | static struct cr50_firmware_version cr50_firmware_version; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 52 | |
| 53 | /* |
Martin Roth | f48acbd | 2020-07-24 12:24:27 -0600 | [diff] [blame] | 54 | * TODO(vbendeb): make CONFIG(DEBUG_TPM) an int to allow different level of |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 55 | * debug traces. Right now it is either 0 or 1. |
| 56 | */ |
Martin Roth | c25c1eb | 2020-07-24 12:26:21 -0600 | [diff] [blame] | 57 | static const int debug_level_ = CONFIG(DEBUG_TPM); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 58 | |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 59 | /* |
| 60 | * SPI frame header for TPM transactions is 4 bytes in size, it is described |
| 61 | * in section "6.4.6 Spi Bit Protocol". |
| 62 | */ |
| 63 | typedef struct { |
| 64 | unsigned char body[4]; |
| 65 | } spi_frame_header; |
| 66 | |
| 67 | void tpm2_get_info(struct tpm2_info *info) |
| 68 | { |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 69 | *info = tpm_info; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 70 | } |
| 71 | |
Aaron Durbin | 6403167 | 2018-04-21 14:45:32 -0600 | [diff] [blame] | 72 | __weak int tis_plat_irq_status(void) |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 73 | { |
Arthur Heymans | 0ca944b | 2019-11-20 19:51:06 +0100 | [diff] [blame] | 74 | static int warning_displayed; |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 75 | |
Arthur Heymans | 0ca944b | 2019-11-20 19:51:06 +0100 | [diff] [blame] | 76 | if (!warning_displayed) { |
Elyes HAOUAS | 103c120 | 2021-01-16 17:30:42 +0100 | [diff] [blame] | 77 | printk(BIOS_WARNING, "WARNING: %s() not implemented, wasting 10ms to wait on" |
| 78 | " Cr50!\n", __func__); |
Arthur Heymans | 0ca944b | 2019-11-20 19:51:06 +0100 | [diff] [blame] | 79 | warning_displayed = 1; |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 80 | } |
| 81 | mdelay(10); |
| 82 | |
| 83 | return 1; |
| 84 | } |
| 85 | |
| 86 | /* |
Elyes HAOUAS | 6688f46 | 2018-08-29 17:22:44 +0200 | [diff] [blame] | 87 | * TPM may trigger a IRQ after finish processing previous transfer. |
| 88 | * Waiting for this IRQ to sync TPM status. |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 89 | * |
| 90 | * Returns 1 on success, 0 on failure (timeout). |
| 91 | */ |
| 92 | static int tpm_sync(void) |
| 93 | { |
| 94 | struct stopwatch sw; |
| 95 | |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame] | 96 | stopwatch_init_msecs_expire(&sw, 10); |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 97 | while (!tis_plat_irq_status()) { |
| 98 | if (stopwatch_expired(&sw)) { |
Elyes HAOUAS | 6688f46 | 2018-08-29 17:22:44 +0200 | [diff] [blame] | 99 | printk(BIOS_ERR, "Timeout wait for TPM IRQ!\n"); |
Jeffy Chen | 19e3d33 | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 100 | return 0; |
| 101 | } |
| 102 | } |
| 103 | return 1; |
| 104 | } |
| 105 | |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 106 | /* |
| 107 | * Each TPM2 SPI transaction starts the same: CS is asserted, the 4 byte |
| 108 | * header is sent to the TPM, the master waits til TPM is ready to continue. |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 109 | * |
| 110 | * Returns 1 on success, 0 on failure (TPM SPI flow control timeout.) |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 111 | */ |
Martin Roth | 38ddbfb | 2019-10-23 21:41:00 -0600 | [diff] [blame] | 112 | static int start_transaction(int read_write, size_t bytes, unsigned int addr) |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 113 | { |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 114 | spi_frame_header header, header_resp; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 115 | uint8_t byte; |
| 116 | int i; |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 117 | int ret; |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 118 | struct stopwatch sw; |
Arthur Heymans | 0ca944b | 2019-11-20 19:51:06 +0100 | [diff] [blame] | 119 | static int tpm_sync_needed; |
| 120 | static struct stopwatch wake_up_sw; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 121 | |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 122 | if (CONFIG(TPM_CR50)) { |
Vadim Bendebury | 3b62d6b | 2017-10-30 18:29:03 -0700 | [diff] [blame] | 123 | /* |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 124 | * First Cr50 access in each coreboot stage where TPM is used will be |
| 125 | * prepended by a wake up pulse on the CS line. |
Vadim Bendebury | 3b62d6b | 2017-10-30 18:29:03 -0700 | [diff] [blame] | 126 | */ |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 127 | int wakeup_needed = 1; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 128 | |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 129 | /* Wait for TPM to finish previous transaction if needed */ |
| 130 | if (tpm_sync_needed) { |
| 131 | tpm_sync(); |
| 132 | /* |
| 133 | * During the first invocation of this function on each stage |
| 134 | * this if () clause code does not run (as tpm_sync_needed |
| 135 | * value is zero), during all following invocations the |
| 136 | * stopwatch below is guaranteed to be started. |
| 137 | */ |
| 138 | if (!stopwatch_expired(&wake_up_sw)) |
| 139 | wakeup_needed = 0; |
| 140 | } else { |
| 141 | tpm_sync_needed = 1; |
| 142 | } |
Vadim Bendebury | 3b62d6b | 2017-10-30 18:29:03 -0700 | [diff] [blame] | 143 | |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 144 | if (wakeup_needed) { |
| 145 | /* Just in case Cr50 is asleep. */ |
| 146 | spi_claim_bus(&spi_slave); |
| 147 | udelay(1); |
| 148 | spi_release_bus(&spi_slave); |
| 149 | udelay(100); |
| 150 | } |
| 151 | |
| 152 | /* |
| 153 | * The Cr50 on H1 does not go to sleep for 1 second after any |
| 154 | * SPI slave activity, let's be conservative and limit the |
| 155 | * window to 900 ms. |
| 156 | */ |
| 157 | stopwatch_init_msecs_expire(&wake_up_sw, 900); |
| 158 | } |
Jeffy Chen | f9a40ea | 2017-03-03 18:24:02 +0800 | [diff] [blame] | 159 | |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 160 | /* |
| 161 | * The first byte of the frame header encodes the transaction type |
Martin Roth | 0949e73 | 2021-10-01 14:28:22 -0600 | [diff] [blame] | 162 | * (read or write) and transfer size (set to length - 1), limited to |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 163 | * 64 bytes. |
| 164 | */ |
| 165 | header.body[0] = (read_write ? 0x80 : 0) | 0x40 | (bytes - 1); |
| 166 | |
| 167 | /* The rest of the frame header is the TPM register address. */ |
| 168 | for (i = 0; i < 3; i++) |
| 169 | header.body[i + 1] = (addr >> (8 * (2 - i))) & 0xff; |
| 170 | |
| 171 | /* CS assert wakes up the slave. */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 172 | spi_claim_bus(&spi_slave); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 173 | |
| 174 | /* |
| 175 | * The TCG TPM over SPI specification introduces the notion of SPI |
| 176 | * flow control (Section "6.4.5 Flow Control"). |
| 177 | * |
| 178 | * Again, the slave (TPM device) expects each transaction to start |
| 179 | * with a 4 byte header trasmitted by master. The header indicates if |
| 180 | * the master needs to read or write a register, and the register |
| 181 | * address. |
| 182 | * |
| 183 | * If the slave needs to stall the transaction (for instance it is not |
| 184 | * ready to send the register value to the master), it sets the MOSI |
| 185 | * line to 0 during the last clock of the 4 byte header. In this case |
| 186 | * the master is supposed to start polling the SPI bus, one byte at |
| 187 | * time, until the last bit in the received byte (transferred during |
| 188 | * the last clock of the byte) is set to 1. |
| 189 | * |
| 190 | * Due to some SPI controllers' shortcomings (Rockchip comes to |
Martin Roth | 0949e73 | 2021-10-01 14:28:22 -0600 | [diff] [blame] | 191 | * mind...) we transmit the 4 byte header without checking the byte |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 192 | * transmitted by the TPM during the transaction's last byte. |
| 193 | * |
| 194 | * We know that cr50 is guaranteed to set the flow control bit to 0 |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 195 | * during the header transfer. Real TPM2 are fast enough to not require |
| 196 | * to stall the master. They might still use this feature, so test the |
| 197 | * last bit after shifting in the address bytes. |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 198 | * crosbug.com/p/52132 has been opened to track this. |
| 199 | */ |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 200 | |
| 201 | header_resp.body[3] = 0; |
| 202 | if (CONFIG(TPM_CR50)) |
| 203 | ret = spi_xfer(&spi_slave, header.body, sizeof(header.body), NULL, 0); |
| 204 | else |
| 205 | ret = spi_xfer(&spi_slave, header.body, sizeof(header.body), |
| 206 | header_resp.body, sizeof(header_resp.body)); |
| 207 | if (ret) { |
| 208 | printk(BIOS_ERR, "SPI-TPM: transfer error\n"); |
| 209 | spi_release_bus(&spi_slave); |
| 210 | return 0; |
| 211 | } |
| 212 | |
| 213 | if (header_resp.body[3] & 1) |
| 214 | return 1; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 215 | |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 216 | /* |
| 217 | * Now poll the bus until TPM removes the stall bit. Give it up to 100 |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 218 | * ms to sort it out - it could be saving stuff in nvram at some point. |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 219 | */ |
| 220 | stopwatch_init_msecs_expire(&sw, 100); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 221 | do { |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 222 | if (stopwatch_expired(&sw)) { |
| 223 | printk(BIOS_ERR, "TPM flow control failure\n"); |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 224 | spi_release_bus(&spi_slave); |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 225 | return 0; |
| 226 | } |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 227 | spi_xfer(&spi_slave, NULL, 0, &byte, 1); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 228 | } while (!(byte & 1)); |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 229 | |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 230 | return 1; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 231 | } |
| 232 | |
| 233 | /* |
| 234 | * Print out the contents of a buffer, if debug is enabled. Skip registers |
| 235 | * other than FIFO, unless debug_level_ is 2. |
| 236 | */ |
| 237 | static void trace_dump(const char *prefix, uint32_t reg, |
| 238 | size_t bytes, const uint8_t *buffer, |
| 239 | int force) |
| 240 | { |
Arthur Heymans | 0ca944b | 2019-11-20 19:51:06 +0100 | [diff] [blame] | 241 | static char prev_prefix; |
| 242 | static unsigned int prev_reg; |
| 243 | static int current_char; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 244 | const int BYTES_PER_LINE = 32; |
| 245 | |
| 246 | if (!force) { |
| 247 | if (!debug_level_) |
| 248 | return; |
| 249 | |
| 250 | if ((debug_level_ < 2) && (reg != TPM_DATA_FIFO_REG)) |
| 251 | return; |
| 252 | } |
| 253 | |
| 254 | /* |
| 255 | * Do not print register address again if the last dump print was for |
| 256 | * that register. |
| 257 | */ |
Arthur Heymans | 0ca944b | 2019-11-20 19:51:06 +0100 | [diff] [blame] | 258 | if (prev_prefix != *prefix || (prev_reg != reg)) { |
| 259 | prev_prefix = *prefix; |
| 260 | prev_reg = reg; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 261 | printk(BIOS_DEBUG, "\n%s %2.2x:", prefix, reg); |
Arthur Heymans | 0ca944b | 2019-11-20 19:51:06 +0100 | [diff] [blame] | 262 | current_char = 0; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 263 | } |
| 264 | |
| 265 | if ((reg != TPM_DATA_FIFO_REG) && (bytes == 4)) { |
| 266 | /* |
| 267 | * This must be a regular register address, print the 32 bit |
| 268 | * value. |
| 269 | */ |
| 270 | printk(BIOS_DEBUG, " %8.8x", *(const uint32_t *)buffer); |
| 271 | } else { |
| 272 | int i; |
| 273 | |
| 274 | /* |
| 275 | * Data read from or written to FIFO or not in 4 byte |
| 276 | * quantiites is printed byte at a time. |
| 277 | */ |
| 278 | for (i = 0; i < bytes; i++) { |
Arthur Heymans | 0ca944b | 2019-11-20 19:51:06 +0100 | [diff] [blame] | 279 | if (current_char && |
| 280 | !(current_char % BYTES_PER_LINE)) { |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 281 | printk(BIOS_DEBUG, "\n "); |
Arthur Heymans | 0ca944b | 2019-11-20 19:51:06 +0100 | [diff] [blame] | 282 | current_char = 0; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 283 | } |
Arthur Heymans | 0ca944b | 2019-11-20 19:51:06 +0100 | [diff] [blame] | 284 | (current_char)++; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 285 | printk(BIOS_DEBUG, " %2.2x", buffer[i]); |
| 286 | } |
| 287 | } |
| 288 | } |
| 289 | |
| 290 | /* |
| 291 | * Once transaction is initiated and the TPM indicated that it is ready to go, |
| 292 | * write the actual bytes to the register. |
| 293 | */ |
| 294 | static void write_bytes(const void *buffer, size_t bytes) |
| 295 | { |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 296 | spi_xfer(&spi_slave, buffer, bytes, NULL, 0); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 297 | } |
| 298 | |
| 299 | /* |
| 300 | * Once transaction is initiated and the TPM indicated that it is ready to go, |
| 301 | * read the actual bytes from the register. |
| 302 | */ |
| 303 | static void read_bytes(void *buffer, size_t bytes) |
| 304 | { |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 305 | spi_xfer(&spi_slave, NULL, 0, buffer, bytes); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 306 | } |
| 307 | |
| 308 | /* |
| 309 | * To write a register, start transaction, transfer data to the TPM, deassert |
| 310 | * CS when done. |
| 311 | * |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 312 | * Returns one to indicate success, zero to indicate failure. |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 313 | */ |
Martin Roth | 38ddbfb | 2019-10-23 21:41:00 -0600 | [diff] [blame] | 314 | static int tpm2_write_reg(unsigned int reg_number, const void *buffer, size_t bytes) |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 315 | { |
| 316 | trace_dump("W", reg_number, bytes, buffer, 0); |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 317 | if (!start_transaction(false, bytes, reg_number)) |
| 318 | return 0; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 319 | write_bytes(buffer, bytes); |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 320 | spi_release_bus(&spi_slave); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 321 | return 1; |
| 322 | } |
| 323 | |
| 324 | /* |
| 325 | * To read a register, start transaction, transfer data from the TPM, deassert |
| 326 | * CS when done. |
| 327 | * |
Vadim Bendebury | 9a506d5 | 2017-10-25 15:45:00 -0700 | [diff] [blame] | 328 | * Returns one to indicate success, zero to indicate failure. In case of |
| 329 | * failure zero out the user buffer. |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 330 | */ |
Martin Roth | 38ddbfb | 2019-10-23 21:41:00 -0600 | [diff] [blame] | 331 | static int tpm2_read_reg(unsigned int reg_number, void *buffer, size_t bytes) |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 332 | { |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 333 | if (!start_transaction(true, bytes, reg_number)) { |
| 334 | memset(buffer, 0, bytes); |
| 335 | return 0; |
| 336 | } |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 337 | read_bytes(buffer, bytes); |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 338 | spi_release_bus(&spi_slave); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 339 | trace_dump("R", reg_number, bytes, buffer, 0); |
| 340 | return 1; |
| 341 | } |
| 342 | |
| 343 | /* |
| 344 | * Status register is accessed often, wrap reading and writing it into |
| 345 | * dedicated functions. |
| 346 | */ |
| 347 | static int read_tpm_sts(uint32_t *status) |
| 348 | { |
| 349 | return tpm2_read_reg(TPM_STS_REG, status, sizeof(*status)); |
| 350 | } |
| 351 | |
Caveh Jalali | 8274c29 | 2020-09-10 01:25:29 -0700 | [diff] [blame] | 352 | static int __must_check write_tpm_sts(uint32_t status) |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 353 | { |
| 354 | return tpm2_write_reg(TPM_STS_REG, &status, sizeof(status)); |
| 355 | } |
| 356 | |
| 357 | /* |
| 358 | * The TPM may limit the transaction bytes count (burst count) below the 64 |
| 359 | * bytes max. The current value is available as a field of the status |
| 360 | * register. |
| 361 | */ |
| 362 | static uint32_t get_burst_count(void) |
| 363 | { |
| 364 | uint32_t status; |
| 365 | |
| 366 | read_tpm_sts(&status); |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame] | 367 | return (status & TPM_STS_BURST_COUNT_MASK) >> TPM_STS_BURST_COUNT_SHIFT; |
| 368 | } |
| 369 | |
| 370 | static uint8_t tpm2_read_access_reg(void) |
| 371 | { |
| 372 | uint8_t access; |
| 373 | tpm2_read_reg(TPM_ACCESS_REG, &access, sizeof(access)); |
| 374 | /* We do not care about access establishment bit state. Ignore it. */ |
| 375 | return access & ~TPM_ACCESS_ESTABLISHMENT; |
| 376 | } |
| 377 | |
| 378 | static void tpm2_write_access_reg(uint8_t cmd) |
| 379 | { |
| 380 | /* Writes to access register can set only 1 bit at a time. */ |
| 381 | assert (!(cmd & (cmd - 1))); |
| 382 | |
| 383 | tpm2_write_reg(TPM_ACCESS_REG, &cmd, sizeof(cmd)); |
| 384 | } |
| 385 | |
| 386 | static int tpm2_claim_locality(void) |
| 387 | { |
| 388 | uint8_t access; |
Shelley Chen | 85eb031 | 2017-11-07 14:24:19 -0800 | [diff] [blame] | 389 | struct stopwatch sw; |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame] | 390 | |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame] | 391 | /* |
Vadim Bendebury | 8727e64 | 2017-11-16 21:00:41 -0800 | [diff] [blame] | 392 | * Locality is released by TPM reset. |
| 393 | * |
| 394 | * If locality is taken at this point, this could be due to the fact |
| 395 | * that the TPM is performing a long operation and has not processed |
| 396 | * reset request yet. We'll wait up to CR50_TIMEOUT_INIT_MS and see if |
| 397 | * it releases locality when reset is processed. |
Shelley Chen | 85eb031 | 2017-11-07 14:24:19 -0800 | [diff] [blame] | 398 | */ |
| 399 | stopwatch_init_msecs_expire(&sw, CR50_TIMEOUT_INIT_MS); |
Vadim Bendebury | 8727e64 | 2017-11-16 21:00:41 -0800 | [diff] [blame] | 400 | do { |
Shelley Chen | 85eb031 | 2017-11-07 14:24:19 -0800 | [diff] [blame] | 401 | access = tpm2_read_access_reg(); |
Vadim Bendebury | 8727e64 | 2017-11-16 21:00:41 -0800 | [diff] [blame] | 402 | if (access & TPM_ACCESS_ACTIVE_LOCALITY) { |
| 403 | /* |
| 404 | * Don't bombard the chip with traffic, let it keep |
| 405 | * processing the command. |
| 406 | */ |
| 407 | mdelay(2); |
| 408 | continue; |
| 409 | } |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame] | 410 | |
Vadim Bendebury | 8727e64 | 2017-11-16 21:00:41 -0800 | [diff] [blame] | 411 | /* |
| 412 | * Ok, the locality is free, TPM must be reset, let's claim |
| 413 | * it. |
| 414 | */ |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame] | 415 | |
Vadim Bendebury | 8727e64 | 2017-11-16 21:00:41 -0800 | [diff] [blame] | 416 | tpm2_write_access_reg(TPM_ACCESS_REQUEST_USE); |
| 417 | access = tpm2_read_access_reg(); |
| 418 | if (access != (TPM_ACCESS_VALID | TPM_ACCESS_ACTIVE_LOCALITY)) { |
| 419 | break; |
| 420 | } |
| 421 | |
| 422 | printk(BIOS_INFO, "TPM ready after %ld ms\n", |
| 423 | stopwatch_duration_msecs(&sw)); |
| 424 | |
| 425 | return 1; |
| 426 | } while (!stopwatch_expired(&sw)); |
| 427 | |
| 428 | printk(BIOS_ERR, |
| 429 | "Failed to claim locality 0 after %ld ms, status: %#x\n", |
| 430 | stopwatch_duration_msecs(&sw), access); |
| 431 | |
| 432 | return 0; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 433 | } |
| 434 | |
Jes Klinke | dcae807 | 2020-07-29 14:22:41 -0700 | [diff] [blame] | 435 | static int cr50_parse_fw_version(const char *version_str, struct cr50_firmware_version *ver) |
| 436 | { |
| 437 | int epoch, major, minor; |
| 438 | |
| 439 | char *number = strstr(version_str, " RW_A:"); |
| 440 | if (!number) |
| 441 | number = strstr(version_str, " RW_B:"); |
| 442 | if (!number) |
| 443 | return -1; |
| 444 | number += 6; /* Skip past the colon. */ |
| 445 | |
| 446 | epoch = skip_atoi(&number); |
| 447 | if (*number++ != '.') |
| 448 | return -2; |
| 449 | major = skip_atoi(&number); |
| 450 | if (*number++ != '.') |
| 451 | return -2; |
| 452 | minor = skip_atoi(&number); |
| 453 | |
| 454 | ver->epoch = epoch; |
| 455 | ver->major = major; |
| 456 | ver->minor = minor; |
| 457 | return 0; |
| 458 | } |
| 459 | |
| 460 | static int cr50_fw_supports_board_cfg(struct cr50_firmware_version *version) |
| 461 | { |
| 462 | /* Cr50 supports the CR50_BOARD_CFG register from version 0.5.5 / 0.6.5 |
| 463 | * and onwards. */ |
| 464 | if (version->epoch > 0 || version->major >= 7 |
| 465 | || (version->major >= 5 && version->minor >= 5)) |
| 466 | return 1; |
| 467 | printk(BIOS_INFO, "Cr50 firmware does not support CR50_BOARD_CFG, version: %d.%d.%d\n", |
| 468 | version->epoch, version->major, version->minor); |
| 469 | return 0; |
| 470 | } |
| 471 | |
| 472 | /** |
| 473 | * Set the BOARD_CFG register on the TPM chip to a particular compile-time constant value. |
| 474 | */ |
| 475 | static void cr50_set_board_cfg(void) |
| 476 | { |
| 477 | uint32_t board_cfg_value; |
| 478 | if (!cr50_fw_supports_board_cfg(&cr50_firmware_version)) |
| 479 | return; |
| 480 | /* Set the CR50_BOARD_CFG register, for e.g. asking cr50 to use longer ready pulses. */ |
| 481 | if (!tpm2_read_reg(CR50_BOARD_CFG, &board_cfg_value, sizeof(board_cfg_value))) { |
| 482 | printk(BIOS_INFO, "Error reading from cr50\n"); |
| 483 | return; |
| 484 | } |
| 485 | if ((board_cfg_value & CR50_BOARD_CFG_FEATUREBITS_MASK) == CR50_BOARD_CFG_VALUE) { |
| 486 | printk(BIOS_INFO, |
| 487 | "Current CR50_BOARD_CFG = 0x%08x, matches desired = 0x%08x\n", |
| 488 | board_cfg_value, CR50_BOARD_CFG_VALUE); |
| 489 | return; |
| 490 | } |
| 491 | if (board_cfg_value & CR50_BOARD_CFG_LOCKBIT_MASK) { |
| 492 | /* The high bit is set, meaning that the Cr50 is already locked on a particular |
| 493 | * value for the register, but not the one we wanted. */ |
| 494 | printk(BIOS_ERR, |
| 495 | "ERROR: Current CR50_BOARD_CFG = 0x%08x, does not match desired = 0x%08x\n", |
| 496 | board_cfg_value, CR50_BOARD_CFG_VALUE); |
| 497 | return; |
| 498 | } |
| 499 | printk(BIOS_INFO, "Current CR50_BOARD_CFG = 0x%08x, setting to 0x%08x\n", |
| 500 | board_cfg_value, CR50_BOARD_CFG_VALUE); |
| 501 | board_cfg_value = CR50_BOARD_CFG_VALUE; |
| 502 | if (!tpm2_write_reg(CR50_BOARD_CFG, &board_cfg_value, sizeof(board_cfg_value))) |
| 503 | printk(BIOS_INFO, "Error writing to cr50\n"); |
| 504 | } |
| 505 | |
| 506 | /* |
| 507 | * Expose method to read the CR50_BOARD_CFG register, will return zero if |
| 508 | * register not supported by Cr50 firmware. |
| 509 | */ |
| 510 | static uint32_t cr50_get_board_cfg(void) |
| 511 | { |
| 512 | uint32_t board_cfg_value; |
| 513 | if (!cr50_fw_supports_board_cfg(&cr50_firmware_version)) |
| 514 | return 0; |
| 515 | if (!tpm2_read_reg(CR50_BOARD_CFG, &board_cfg_value, sizeof(board_cfg_value))) { |
| 516 | printk(BIOS_INFO, "Error reading from cr50\n"); |
| 517 | return 0; |
| 518 | } |
| 519 | return board_cfg_value & CR50_BOARD_CFG_FEATUREBITS_MASK; |
| 520 | } |
| 521 | |
| 522 | bool cr50_is_long_interrupt_pulse_enabled(void) |
| 523 | { |
| 524 | return cr50_get_board_cfg() & CR50_BOARD_CFG_100US_READY_PULSE; |
| 525 | } |
| 526 | |
Vadim Bendebury | 9a506d5 | 2017-10-25 15:45:00 -0700 | [diff] [blame] | 527 | /* Device/vendor ID values of the TPM devices this driver supports. */ |
| 528 | static const uint32_t supported_did_vids[] = { |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 529 | 0x00281ae0, /* H1 based Cr50 security chip. */ |
| 530 | 0x0000104a /* ST33HTPH2E32 */ |
Vadim Bendebury | 9a506d5 | 2017-10-25 15:45:00 -0700 | [diff] [blame] | 531 | }; |
| 532 | |
Jes Klinke | dcae807 | 2020-07-29 14:22:41 -0700 | [diff] [blame] | 533 | static int first_access_this_boot(void) |
| 534 | { |
| 535 | return ENV_SEPARATE_VERSTAGE || ENV_BOOTBLOCK || !CONFIG(VBOOT); |
| 536 | } |
| 537 | |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 538 | int tpm2_init(struct spi_slave *spi_if) |
| 539 | { |
| 540 | uint32_t did_vid, status; |
| 541 | uint8_t cmd; |
Vadim Bendebury | 9a506d5 | 2017-10-25 15:45:00 -0700 | [diff] [blame] | 542 | int retries; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 543 | |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 544 | memcpy(&spi_slave, spi_if, sizeof(*spi_if)); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 545 | |
Elyes HAOUAS | 6688f46 | 2018-08-29 17:22:44 +0200 | [diff] [blame] | 546 | /* clear any pending IRQs */ |
Shelley Chen | f2e7b37 | 2017-12-15 15:25:08 -0800 | [diff] [blame] | 547 | tis_plat_irq_status(); |
| 548 | |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 549 | /* |
Vadim Bendebury | 9a506d5 | 2017-10-25 15:45:00 -0700 | [diff] [blame] | 550 | * 150 ms should be enough to synchronize with the TPM even under the |
| 551 | * worst nested reset request conditions. In vast majority of cases |
| 552 | * there would be no wait at all. |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 553 | */ |
Vadim Bendebury | 9a506d5 | 2017-10-25 15:45:00 -0700 | [diff] [blame] | 554 | printk(BIOS_INFO, "Probing TPM: "); |
| 555 | for (retries = 15; retries > 0; retries--) { |
| 556 | int i; |
| 557 | |
Elyes HAOUAS | 6688f46 | 2018-08-29 17:22:44 +0200 | [diff] [blame] | 558 | /* In case of failure to read div_vid is set to zero. */ |
Vadim Bendebury | 9a506d5 | 2017-10-25 15:45:00 -0700 | [diff] [blame] | 559 | tpm2_read_reg(TPM_DID_VID_REG, &did_vid, sizeof(did_vid)); |
| 560 | |
| 561 | for (i = 0; i < ARRAY_SIZE(supported_did_vids); i++) |
| 562 | if (did_vid == supported_did_vids[i]) |
Elyes HAOUAS | 6688f46 | 2018-08-29 17:22:44 +0200 | [diff] [blame] | 563 | break; /* TPM is up and ready. */ |
Vadim Bendebury | 9a506d5 | 2017-10-25 15:45:00 -0700 | [diff] [blame] | 564 | |
| 565 | if (i < ARRAY_SIZE(supported_did_vids)) |
| 566 | break; |
| 567 | |
| 568 | /* TPM might be resetting, let's retry in a bit. */ |
| 569 | mdelay(10); |
| 570 | printk(BIOS_INFO, "."); |
| 571 | } |
| 572 | |
| 573 | if (!retries) { |
| 574 | printk(BIOS_ERR, "\n%s: Failed to connect to the TPM\n", |
| 575 | __func__); |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 576 | return -1; |
Vadim Bendebury | 9a506d5 | 2017-10-25 15:45:00 -0700 | [diff] [blame] | 577 | } |
| 578 | |
| 579 | printk(BIOS_INFO, " done!\n"); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 580 | |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 581 | // FIXME: Move this to tpm_setup() |
Jes Klinke | dcae807 | 2020-07-29 14:22:41 -0700 | [diff] [blame] | 582 | if (first_access_this_boot()) |
Vadim Bendebury | 8727e64 | 2017-11-16 21:00:41 -0800 | [diff] [blame] | 583 | /* |
| 584 | * Claim locality 0, do it only during the first |
| 585 | * initialization after reset. |
| 586 | */ |
| 587 | if (!tpm2_claim_locality()) |
| 588 | return -1; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 589 | |
Patrick Rudolph | 7bcd9a1 | 2020-03-20 09:55:43 +0100 | [diff] [blame] | 590 | if (!read_tpm_sts(&status)) { |
| 591 | printk(BIOS_ERR, "Reading status reg failed\n"); |
| 592 | return -1; |
| 593 | } |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame] | 594 | if ((status & TPM_STS_FAMILY_MASK) != TPM_STS_FAMILY_TPM_2_0) { |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 595 | printk(BIOS_ERR, "unexpected TPM family value, status: %#x\n", |
| 596 | status); |
| 597 | return -1; |
| 598 | } |
| 599 | |
| 600 | /* |
| 601 | * Locality claimed, read the revision value and set up the tpm_info |
| 602 | * structure. |
| 603 | */ |
| 604 | tpm2_read_reg(TPM_RID_REG, &cmd, sizeof(cmd)); |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 605 | tpm_info.vendor_id = did_vid & 0xffff; |
| 606 | tpm_info.device_id = did_vid >> 16; |
| 607 | tpm_info.revision = cmd; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 608 | |
| 609 | printk(BIOS_INFO, "Connected to device vid:did:rid of %4.4x:%4.4x:%2.2x\n", |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 610 | tpm_info.vendor_id, tpm_info.device_id, tpm_info.revision); |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 611 | |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 612 | /* Let's report device FW version if available. */ |
Jes Klinke | dcae807 | 2020-07-29 14:22:41 -0700 | [diff] [blame] | 613 | if (CONFIG(TPM_CR50) && tpm_info.vendor_id == 0x1ae0) { |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 614 | int chunk_count = 0; |
Jes Klinke | dcae807 | 2020-07-29 14:22:41 -0700 | [diff] [blame] | 615 | size_t chunk_size = 50; |
| 616 | char version_str[301]; |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 617 | |
| 618 | /* |
| 619 | * Does not really matter what's written, this just makes sure |
| 620 | * the version is reported from the beginning. |
| 621 | */ |
Vadim Bendebury | 9e561f8 | 2016-07-31 11:19:20 -0700 | [diff] [blame] | 622 | tpm2_write_reg(TPM_FW_VER, &chunk_size, 1); |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 623 | |
Jes Klinke | dcae807 | 2020-07-29 14:22:41 -0700 | [diff] [blame] | 624 | /* |
| 625 | * Read chunk_size bytes at a time, last chunk will be zero padded. |
| 626 | */ |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 627 | do { |
Jes Klinke | dcae807 | 2020-07-29 14:22:41 -0700 | [diff] [blame] | 628 | tpm2_read_reg(TPM_FW_VER, |
| 629 | version_str + chunk_count * chunk_size, |
| 630 | chunk_size); |
| 631 | if (!version_str[++chunk_count * chunk_size - 1]) |
| 632 | /* Zero padding detected: end of string. */ |
| 633 | break; |
| 634 | /* Check if there is enough room for reading one more chunk. */ |
| 635 | } while (chunk_count * chunk_size < sizeof(version_str) - chunk_size); |
| 636 | version_str[chunk_count * chunk_size] = '\0'; |
| 637 | printk(BIOS_INFO, "Firmware version: %s\n", version_str); |
| 638 | if (cr50_parse_fw_version(version_str, &cr50_firmware_version)) { |
| 639 | printk(BIOS_ERR, "Did not recognize Cr50 version format\n"); |
| 640 | return -1; |
| 641 | } |
| 642 | if (CR50_BOARD_CFG_VALUE) { |
| 643 | if (first_access_this_boot()) |
| 644 | cr50_set_board_cfg(); |
| 645 | } |
Vadim Bendebury | 58826fc | 2016-06-23 18:17:33 -0700 | [diff] [blame] | 646 | } |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 647 | return 0; |
| 648 | } |
| 649 | |
| 650 | /* |
| 651 | * This is in seconds, certain TPM commands, like key generation, can take |
| 652 | * long time to complete. |
| 653 | * |
| 654 | * Returns one to indicate success, zero (not yet implemented) to indicate |
| 655 | * failure. |
| 656 | */ |
| 657 | #define MAX_STATUS_TIMEOUT 120 |
| 658 | static int wait_for_status(uint32_t status_mask, uint32_t status_expected) |
| 659 | { |
| 660 | uint32_t status; |
| 661 | struct stopwatch sw; |
| 662 | |
| 663 | stopwatch_init_usecs_expire(&sw, MAX_STATUS_TIMEOUT * 1000 * 1000); |
| 664 | do { |
| 665 | udelay(1000); |
| 666 | if (stopwatch_expired(&sw)) { |
| 667 | printk(BIOS_ERR, "failed to get expected status %x\n", |
| 668 | status_expected); |
| 669 | return false; |
| 670 | } |
| 671 | read_tpm_sts(&status); |
| 672 | } while ((status & status_mask) != status_expected); |
| 673 | |
| 674 | return 1; |
| 675 | } |
| 676 | |
| 677 | enum fifo_transfer_direction { |
| 678 | fifo_transmit = 0, |
| 679 | fifo_receive = 1 |
| 680 | }; |
| 681 | |
| 682 | /* Union allows to avoid casting away 'const' on transmit buffers. */ |
| 683 | union fifo_transfer_buffer { |
| 684 | uint8_t *rx_buffer; |
| 685 | const uint8_t *tx_buffer; |
| 686 | }; |
| 687 | |
| 688 | /* |
| 689 | * Transfer requested number of bytes to or from TPM FIFO, accounting for the |
| 690 | * current burst count value. |
| 691 | */ |
Caveh Jalali | 8274c29 | 2020-09-10 01:25:29 -0700 | [diff] [blame] | 692 | static int __must_check fifo_transfer(size_t transfer_size, |
| 693 | union fifo_transfer_buffer buffer, |
| 694 | enum fifo_transfer_direction direction) |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 695 | { |
| 696 | size_t transaction_size; |
| 697 | size_t burst_count; |
| 698 | size_t handled_so_far = 0; |
| 699 | |
| 700 | do { |
| 701 | do { |
| 702 | /* Could be zero when TPM is busy. */ |
| 703 | burst_count = get_burst_count(); |
| 704 | } while (!burst_count); |
| 705 | |
| 706 | transaction_size = transfer_size - handled_so_far; |
| 707 | transaction_size = MIN(transaction_size, burst_count); |
| 708 | |
| 709 | /* |
| 710 | * The SPI frame header does not allow to pass more than 64 |
| 711 | * bytes. |
| 712 | */ |
| 713 | transaction_size = MIN(transaction_size, 64); |
| 714 | |
Caveh Jalali | 8274c29 | 2020-09-10 01:25:29 -0700 | [diff] [blame] | 715 | if (direction == fifo_receive) { |
| 716 | if (!tpm2_read_reg(TPM_DATA_FIFO_REG, |
| 717 | buffer.rx_buffer + handled_so_far, |
| 718 | transaction_size)) |
| 719 | return 0; |
| 720 | } else { |
| 721 | if (!tpm2_write_reg(TPM_DATA_FIFO_REG, |
| 722 | buffer.tx_buffer + handled_so_far, |
| 723 | transaction_size)) |
| 724 | return 0; |
| 725 | } |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 726 | |
| 727 | handled_so_far += transaction_size; |
| 728 | |
| 729 | } while (handled_so_far != transfer_size); |
Caveh Jalali | 8274c29 | 2020-09-10 01:25:29 -0700 | [diff] [blame] | 730 | |
| 731 | return 1; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 732 | } |
| 733 | |
| 734 | size_t tpm2_process_command(const void *tpm2_command, size_t command_size, |
| 735 | void *tpm2_response, size_t max_response) |
| 736 | { |
| 737 | uint32_t status; |
| 738 | uint32_t expected_status_bits; |
| 739 | size_t payload_size; |
| 740 | size_t bytes_to_go; |
| 741 | const uint8_t *cmd_body = tpm2_command; |
| 742 | uint8_t *rsp_body = tpm2_response; |
| 743 | union fifo_transfer_buffer fifo_buffer; |
| 744 | const int HEADER_SIZE = 6; |
| 745 | |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 746 | /* Do not try using an uninitialized TPM. */ |
Patrick Georgi | c9b1359 | 2019-11-29 11:47:47 +0100 | [diff] [blame] | 747 | if (!tpm_info.vendor_id) |
Vadim Bendebury | 731ef9b | 2016-12-15 21:49:23 -0800 | [diff] [blame] | 748 | return 0; |
| 749 | |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 750 | /* Skip the two byte tag, read the size field. */ |
| 751 | payload_size = read_be32(cmd_body + 2); |
| 752 | |
| 753 | /* Sanity check. */ |
| 754 | if (payload_size != command_size) { |
| 755 | printk(BIOS_ERR, |
| 756 | "Command size mismatch: encoded %zd != requested %zd\n", |
| 757 | payload_size, command_size); |
| 758 | trace_dump("W", TPM_DATA_FIFO_REG, command_size, cmd_body, 1); |
| 759 | printk(BIOS_DEBUG, "\n"); |
| 760 | return 0; |
| 761 | } |
| 762 | |
| 763 | /* Let the TPM know that the command is coming. */ |
Caveh Jalali | 8274c29 | 2020-09-10 01:25:29 -0700 | [diff] [blame] | 764 | if (!write_tpm_sts(TPM_STS_COMMAND_READY)) { |
| 765 | printk(BIOS_ERR, "TPM_STS_COMMAND_READY failed\n"); |
| 766 | return 0; |
| 767 | } |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 768 | |
| 769 | /* |
Elyes HAOUAS | 6688f46 | 2018-08-29 17:22:44 +0200 | [diff] [blame] | 770 | * TPM commands and responses written to and read from the FIFO |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 771 | * register (0x24) are datagrams of variable size, prepended by a 6 |
| 772 | * byte header. |
| 773 | * |
| 774 | * The specification description of the state machine is a bit vague, |
| 775 | * but from experience it looks like there is no need to wait for the |
| 776 | * sts.expect bit to be set, at least with the 9670 and cr50 devices. |
| 777 | * Just write the command into FIFO, making sure not to exceed the |
| 778 | * burst count or the maximum PDU size, whatever is smaller. |
| 779 | */ |
| 780 | fifo_buffer.tx_buffer = cmd_body; |
Caveh Jalali | 8274c29 | 2020-09-10 01:25:29 -0700 | [diff] [blame] | 781 | if (!fifo_transfer(command_size, fifo_buffer, fifo_transmit)) { |
| 782 | printk(BIOS_ERR, "fifo_transfer %zd command bytes failed\n", |
| 783 | command_size); |
| 784 | return 0; |
| 785 | } |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 786 | |
| 787 | /* Now tell the TPM it can start processing the command. */ |
Caveh Jalali | 8274c29 | 2020-09-10 01:25:29 -0700 | [diff] [blame] | 788 | if (!write_tpm_sts(TPM_STS_GO)) { |
| 789 | printk(BIOS_ERR, "TPM_STS_GO failed\n"); |
| 790 | return 0; |
| 791 | } |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 792 | |
| 793 | /* Now wait for it to report that the response is ready. */ |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame] | 794 | expected_status_bits = TPM_STS_VALID | TPM_STS_DATA_AVAIL; |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 795 | if (!wait_for_status(expected_status_bits, expected_status_bits)) { |
| 796 | /* |
| 797 | * If timed out, which should never happen, let's at least |
| 798 | * print out the offending command. |
| 799 | */ |
| 800 | trace_dump("W", TPM_DATA_FIFO_REG, command_size, cmd_body, 1); |
| 801 | printk(BIOS_DEBUG, "\n"); |
| 802 | return 0; |
| 803 | } |
| 804 | |
| 805 | /* |
| 806 | * The response is ready, let's read it. First we read the FIFO |
| 807 | * payload header, to see how much data to expect. The response header |
| 808 | * size is fixed to six bytes, the total payload size is stored in |
| 809 | * network order in the last four bytes. |
| 810 | */ |
| 811 | tpm2_read_reg(TPM_DATA_FIFO_REG, rsp_body, HEADER_SIZE); |
| 812 | |
| 813 | /* Find out the total payload size, skipping the two byte tag. */ |
| 814 | payload_size = read_be32(rsp_body + 2); |
| 815 | |
| 816 | if (payload_size > max_response) { |
| 817 | /* |
| 818 | * TODO(vbendeb): at least drain the FIFO here or somehow let |
| 819 | * the TPM know that the response can be dropped. |
| 820 | */ |
Elyes HAOUAS | 6688f46 | 2018-08-29 17:22:44 +0200 | [diff] [blame] | 821 | printk(BIOS_ERR, " TPM response too long (%zd bytes)", |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 822 | payload_size); |
| 823 | return 0; |
| 824 | } |
| 825 | |
| 826 | /* |
| 827 | * Now let's read all but the last byte in the FIFO to make sure the |
| 828 | * status register is showing correct flow control bits: 'more data' |
| 829 | * until the last byte and then 'no more data' once the last byte is |
| 830 | * read. |
| 831 | */ |
| 832 | bytes_to_go = payload_size - 1 - HEADER_SIZE; |
| 833 | fifo_buffer.rx_buffer = rsp_body + HEADER_SIZE; |
Caveh Jalali | 8274c29 | 2020-09-10 01:25:29 -0700 | [diff] [blame] | 834 | if (!fifo_transfer(bytes_to_go, fifo_buffer, fifo_receive)) { |
| 835 | printk(BIOS_ERR, "fifo_transfer %zd receive bytes failed\n", |
| 836 | bytes_to_go); |
| 837 | return 0; |
| 838 | } |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 839 | |
| 840 | /* Verify that there is still data to read. */ |
| 841 | read_tpm_sts(&status); |
| 842 | if ((status & expected_status_bits) != expected_status_bits) { |
| 843 | printk(BIOS_ERR, "unexpected intermediate status %#x\n", |
| 844 | status); |
| 845 | return 0; |
| 846 | } |
| 847 | |
| 848 | /* Read the last byte of the PDU. */ |
| 849 | tpm2_read_reg(TPM_DATA_FIFO_REG, rsp_body + payload_size - 1, 1); |
| 850 | |
| 851 | /* Terminate the dump, if enabled. */ |
| 852 | if (debug_level_) |
| 853 | printk(BIOS_DEBUG, "\n"); |
| 854 | |
| 855 | /* Verify that 'data available' is not asseretd any more. */ |
| 856 | read_tpm_sts(&status); |
Furquan Shaikh | 260b297 | 2017-04-07 13:26:01 -0700 | [diff] [blame] | 857 | if ((status & expected_status_bits) != TPM_STS_VALID) { |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 858 | printk(BIOS_ERR, "unexpected final status %#x\n", status); |
| 859 | return 0; |
| 860 | } |
| 861 | |
| 862 | /* Move the TPM back to idle state. */ |
Caveh Jalali | 8274c29 | 2020-09-10 01:25:29 -0700 | [diff] [blame] | 863 | if (!write_tpm_sts(TPM_STS_COMMAND_READY)) { |
| 864 | printk(BIOS_ERR, "TPM_STS_COMMAND_READY failed\n"); |
| 865 | return 0; |
| 866 | } |
Vadim Bendebury | e31d243 | 2016-04-09 18:33:49 -0700 | [diff] [blame] | 867 | |
| 868 | return payload_size; |
| 869 | } |
Karthikeyan Ramasubramanian | 7b58f94 | 2020-08-20 22:53:00 -0600 | [diff] [blame] | 870 | |
| 871 | void cr50_get_firmware_version(struct cr50_firmware_version *version) |
| 872 | { |
| 873 | memcpy(version, &cr50_firmware_version, sizeof(*version)); |
| 874 | } |